stm32ral/stm32f7/peripherals/scb.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! System control block
4//!
5//! Used by: stm32f730, stm32f745, stm32f750, stm32f765, stm32f7x2, stm32f7x3, stm32f7x6, stm32f7x7, stm32f7x9
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// CPUID base register
12pub mod CPUID {
13
14 /// Revision number
15 pub mod Revision {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (4 bits: 0b1111 << 0)
19 pub const mask: u32 = 0b1111 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Part number of the processor
29 pub mod PartNo {
30 /// Offset (4 bits)
31 pub const offset: u32 = 4;
32 /// Mask (12 bits: 0xfff << 4)
33 pub const mask: u32 = 0xfff << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Reads as 0xF
43 pub mod Constant {
44 /// Offset (16 bits)
45 pub const offset: u32 = 16;
46 /// Mask (4 bits: 0b1111 << 16)
47 pub const mask: u32 = 0b1111 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Variant number
57 pub mod Variant {
58 /// Offset (20 bits)
59 pub const offset: u32 = 20;
60 /// Mask (4 bits: 0b1111 << 20)
61 pub const mask: u32 = 0b1111 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Implementer code
71 pub mod Implementer {
72 /// Offset (24 bits)
73 pub const offset: u32 = 24;
74 /// Mask (8 bits: 0xff << 24)
75 pub const mask: u32 = 0xff << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83}
84
85/// Interrupt control and state register
86pub mod ICSR {
87
88 /// Active vector
89 pub mod VECTACTIVE {
90 /// Offset (0 bits)
91 pub const offset: u32 = 0;
92 /// Mask (9 bits: 0x1ff << 0)
93 pub const mask: u32 = 0x1ff << offset;
94 /// Read-only values (empty)
95 pub mod R {}
96 /// Write-only values (empty)
97 pub mod W {}
98 /// Read-write values (empty)
99 pub mod RW {}
100 }
101
102 /// Return to base level
103 pub mod RETTOBASE {
104 /// Offset (11 bits)
105 pub const offset: u32 = 11;
106 /// Mask (1 bit: 1 << 11)
107 pub const mask: u32 = 1 << offset;
108 /// Read-only values (empty)
109 pub mod R {}
110 /// Write-only values (empty)
111 pub mod W {}
112 /// Read-write values (empty)
113 pub mod RW {}
114 }
115
116 /// Pending vector
117 pub mod VECTPENDING {
118 /// Offset (12 bits)
119 pub const offset: u32 = 12;
120 /// Mask (7 bits: 0x7f << 12)
121 pub const mask: u32 = 0x7f << offset;
122 /// Read-only values (empty)
123 pub mod R {}
124 /// Write-only values (empty)
125 pub mod W {}
126 /// Read-write values (empty)
127 pub mod RW {}
128 }
129
130 /// Interrupt pending flag
131 pub mod ISRPENDING {
132 /// Offset (22 bits)
133 pub const offset: u32 = 22;
134 /// Mask (1 bit: 1 << 22)
135 pub const mask: u32 = 1 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// SysTick exception clear-pending bit
145 pub mod PENDSTCLR {
146 /// Offset (25 bits)
147 pub const offset: u32 = 25;
148 /// Mask (1 bit: 1 << 25)
149 pub const mask: u32 = 1 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157
158 /// SysTick exception set-pending bit
159 pub mod PENDSTSET {
160 /// Offset (26 bits)
161 pub const offset: u32 = 26;
162 /// Mask (1 bit: 1 << 26)
163 pub const mask: u32 = 1 << offset;
164 /// Read-only values (empty)
165 pub mod R {}
166 /// Write-only values (empty)
167 pub mod W {}
168 /// Read-write values (empty)
169 pub mod RW {}
170 }
171
172 /// PendSV clear-pending bit
173 pub mod PENDSVCLR {
174 /// Offset (27 bits)
175 pub const offset: u32 = 27;
176 /// Mask (1 bit: 1 << 27)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// PendSV set-pending bit
187 pub mod PENDSVSET {
188 /// Offset (28 bits)
189 pub const offset: u32 = 28;
190 /// Mask (1 bit: 1 << 28)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// NMI set-pending bit.
201 pub mod NMIPENDSET {
202 /// Offset (31 bits)
203 pub const offset: u32 = 31;
204 /// Mask (1 bit: 1 << 31)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213}
214
215/// Vector table offset register
216pub mod VTOR {
217
218 /// Vector table base offset field
219 pub mod TBLOFF {
220 /// Offset (9 bits)
221 pub const offset: u32 = 9;
222 /// Mask (21 bits: 0x1fffff << 9)
223 pub const mask: u32 = 0x1fffff << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231}
232
233/// Application interrupt and reset control register
234pub mod AIRCR {
235
236 /// VECTRESET
237 pub mod VECTRESET {
238 /// Offset (0 bits)
239 pub const offset: u32 = 0;
240 /// Mask (1 bit: 1 << 0)
241 pub const mask: u32 = 1 << offset;
242 /// Read-only values (empty)
243 pub mod R {}
244 /// Write-only values (empty)
245 pub mod W {}
246 /// Read-write values (empty)
247 pub mod RW {}
248 }
249
250 /// VECTCLRACTIVE
251 pub mod VECTCLRACTIVE {
252 /// Offset (1 bits)
253 pub const offset: u32 = 1;
254 /// Mask (1 bit: 1 << 1)
255 pub const mask: u32 = 1 << offset;
256 /// Read-only values (empty)
257 pub mod R {}
258 /// Write-only values (empty)
259 pub mod W {}
260 /// Read-write values (empty)
261 pub mod RW {}
262 }
263
264 /// SYSRESETREQ
265 pub mod SYSRESETREQ {
266 /// Offset (2 bits)
267 pub const offset: u32 = 2;
268 /// Mask (1 bit: 1 << 2)
269 pub const mask: u32 = 1 << offset;
270 /// Read-only values (empty)
271 pub mod R {}
272 /// Write-only values (empty)
273 pub mod W {}
274 /// Read-write values (empty)
275 pub mod RW {}
276 }
277
278 /// PRIGROUP
279 pub mod PRIGROUP {
280 /// Offset (8 bits)
281 pub const offset: u32 = 8;
282 /// Mask (3 bits: 0b111 << 8)
283 pub const mask: u32 = 0b111 << offset;
284 /// Read-only values (empty)
285 pub mod R {}
286 /// Write-only values (empty)
287 pub mod W {}
288 /// Read-write values (empty)
289 pub mod RW {}
290 }
291
292 /// ENDIANESS
293 pub mod ENDIANESS {
294 /// Offset (15 bits)
295 pub const offset: u32 = 15;
296 /// Mask (1 bit: 1 << 15)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// Register key
307 pub mod VECTKEYSTAT {
308 /// Offset (16 bits)
309 pub const offset: u32 = 16;
310 /// Mask (16 bits: 0xffff << 16)
311 pub const mask: u32 = 0xffff << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319}
320
321/// System control register
322pub mod SCR {
323
324 /// SLEEPONEXIT
325 pub mod SLEEPONEXIT {
326 /// Offset (1 bits)
327 pub const offset: u32 = 1;
328 /// Mask (1 bit: 1 << 1)
329 pub const mask: u32 = 1 << offset;
330 /// Read-only values (empty)
331 pub mod R {}
332 /// Write-only values (empty)
333 pub mod W {}
334 /// Read-write values (empty)
335 pub mod RW {}
336 }
337
338 /// SLEEPDEEP
339 pub mod SLEEPDEEP {
340 /// Offset (2 bits)
341 pub const offset: u32 = 2;
342 /// Mask (1 bit: 1 << 2)
343 pub const mask: u32 = 1 << offset;
344 /// Read-only values (empty)
345 pub mod R {}
346 /// Write-only values (empty)
347 pub mod W {}
348 /// Read-write values (empty)
349 pub mod RW {}
350 }
351
352 /// Send Event on Pending bit
353 pub mod SEVEONPEND {
354 /// Offset (4 bits)
355 pub const offset: u32 = 4;
356 /// Mask (1 bit: 1 << 4)
357 pub const mask: u32 = 1 << offset;
358 /// Read-only values (empty)
359 pub mod R {}
360 /// Write-only values (empty)
361 pub mod W {}
362 /// Read-write values (empty)
363 pub mod RW {}
364 }
365}
366
367/// Configuration and control register
368pub mod CCR {
369
370 /// Configures how the processor enters Thread mode
371 pub mod NONBASETHRDENA {
372 /// Offset (0 bits)
373 pub const offset: u32 = 0;
374 /// Mask (1 bit: 1 << 0)
375 pub const mask: u32 = 1 << offset;
376 /// Read-only values (empty)
377 pub mod R {}
378 /// Write-only values (empty)
379 pub mod W {}
380 /// Read-write values (empty)
381 pub mod RW {}
382 }
383
384 /// USERSETMPEND
385 pub mod USERSETMPEND {
386 /// Offset (1 bits)
387 pub const offset: u32 = 1;
388 /// Mask (1 bit: 1 << 1)
389 pub const mask: u32 = 1 << offset;
390 /// Read-only values (empty)
391 pub mod R {}
392 /// Write-only values (empty)
393 pub mod W {}
394 /// Read-write values (empty)
395 pub mod RW {}
396 }
397
398 /// UNALIGN_ TRP
399 pub mod UNALIGN__TRP {
400 /// Offset (3 bits)
401 pub const offset: u32 = 3;
402 /// Mask (1 bit: 1 << 3)
403 pub const mask: u32 = 1 << offset;
404 /// Read-only values (empty)
405 pub mod R {}
406 /// Write-only values (empty)
407 pub mod W {}
408 /// Read-write values (empty)
409 pub mod RW {}
410 }
411
412 /// DIV_0_TRP
413 pub mod DIV_0_TRP {
414 /// Offset (4 bits)
415 pub const offset: u32 = 4;
416 /// Mask (1 bit: 1 << 4)
417 pub const mask: u32 = 1 << offset;
418 /// Read-only values (empty)
419 pub mod R {}
420 /// Write-only values (empty)
421 pub mod W {}
422 /// Read-write values (empty)
423 pub mod RW {}
424 }
425
426 /// BFHFNMIGN
427 pub mod BFHFNMIGN {
428 /// Offset (8 bits)
429 pub const offset: u32 = 8;
430 /// Mask (1 bit: 1 << 8)
431 pub const mask: u32 = 1 << offset;
432 /// Read-only values (empty)
433 pub mod R {}
434 /// Write-only values (empty)
435 pub mod W {}
436 /// Read-write values (empty)
437 pub mod RW {}
438 }
439
440 /// STKALIGN
441 pub mod STKALIGN {
442 /// Offset (9 bits)
443 pub const offset: u32 = 9;
444 /// Mask (1 bit: 1 << 9)
445 pub const mask: u32 = 1 << offset;
446 /// Read-only values (empty)
447 pub mod R {}
448 /// Write-only values (empty)
449 pub mod W {}
450 /// Read-write values (empty)
451 pub mod RW {}
452 }
453
454 /// DC
455 pub mod DC {
456 /// Offset (16 bits)
457 pub const offset: u32 = 16;
458 /// Mask (1 bit: 1 << 16)
459 pub const mask: u32 = 1 << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467
468 /// IC
469 pub mod IC {
470 /// Offset (17 bits)
471 pub const offset: u32 = 17;
472 /// Mask (1 bit: 1 << 17)
473 pub const mask: u32 = 1 << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481
482 /// BP
483 pub mod BP {
484 /// Offset (18 bits)
485 pub const offset: u32 = 18;
486 /// Mask (1 bit: 1 << 18)
487 pub const mask: u32 = 1 << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495}
496
497/// System handler priority registers
498pub mod SHPR1 {
499
500 /// Priority of system handler 4
501 pub mod PRI_4 {
502 /// Offset (0 bits)
503 pub const offset: u32 = 0;
504 /// Mask (8 bits: 0xff << 0)
505 pub const mask: u32 = 0xff << offset;
506 /// Read-only values (empty)
507 pub mod R {}
508 /// Write-only values (empty)
509 pub mod W {}
510 /// Read-write values (empty)
511 pub mod RW {}
512 }
513
514 /// Priority of system handler 5
515 pub mod PRI_5 {
516 /// Offset (8 bits)
517 pub const offset: u32 = 8;
518 /// Mask (8 bits: 0xff << 8)
519 pub const mask: u32 = 0xff << offset;
520 /// Read-only values (empty)
521 pub mod R {}
522 /// Write-only values (empty)
523 pub mod W {}
524 /// Read-write values (empty)
525 pub mod RW {}
526 }
527
528 /// Priority of system handler 6
529 pub mod PRI_6 {
530 /// Offset (16 bits)
531 pub const offset: u32 = 16;
532 /// Mask (8 bits: 0xff << 16)
533 pub const mask: u32 = 0xff << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values (empty)
539 pub mod RW {}
540 }
541}
542
543/// System handler priority registers
544pub mod SHPR2 {
545
546 /// Priority of system handler 11
547 pub mod PRI_11 {
548 /// Offset (24 bits)
549 pub const offset: u32 = 24;
550 /// Mask (8 bits: 0xff << 24)
551 pub const mask: u32 = 0xff << offset;
552 /// Read-only values (empty)
553 pub mod R {}
554 /// Write-only values (empty)
555 pub mod W {}
556 /// Read-write values (empty)
557 pub mod RW {}
558 }
559}
560
561/// System handler priority registers
562pub mod SHPR3 {
563
564 /// Priority of system handler 14
565 pub mod PRI_14 {
566 /// Offset (16 bits)
567 pub const offset: u32 = 16;
568 /// Mask (8 bits: 0xff << 16)
569 pub const mask: u32 = 0xff << offset;
570 /// Read-only values (empty)
571 pub mod R {}
572 /// Write-only values (empty)
573 pub mod W {}
574 /// Read-write values (empty)
575 pub mod RW {}
576 }
577
578 /// Priority of system handler 15
579 pub mod PRI_15 {
580 /// Offset (24 bits)
581 pub const offset: u32 = 24;
582 /// Mask (8 bits: 0xff << 24)
583 pub const mask: u32 = 0xff << offset;
584 /// Read-only values (empty)
585 pub mod R {}
586 /// Write-only values (empty)
587 pub mod W {}
588 /// Read-write values (empty)
589 pub mod RW {}
590 }
591}
592
593/// System handler control and state register
594pub mod SHCRS {
595
596 /// Memory management fault exception active bit
597 pub mod MEMFAULTACT {
598 /// Offset (0 bits)
599 pub const offset: u32 = 0;
600 /// Mask (1 bit: 1 << 0)
601 pub const mask: u32 = 1 << offset;
602 /// Read-only values (empty)
603 pub mod R {}
604 /// Write-only values (empty)
605 pub mod W {}
606 /// Read-write values (empty)
607 pub mod RW {}
608 }
609
610 /// Bus fault exception active bit
611 pub mod BUSFAULTACT {
612 /// Offset (1 bits)
613 pub const offset: u32 = 1;
614 /// Mask (1 bit: 1 << 1)
615 pub const mask: u32 = 1 << offset;
616 /// Read-only values (empty)
617 pub mod R {}
618 /// Write-only values (empty)
619 pub mod W {}
620 /// Read-write values (empty)
621 pub mod RW {}
622 }
623
624 /// Usage fault exception active bit
625 pub mod USGFAULTACT {
626 /// Offset (3 bits)
627 pub const offset: u32 = 3;
628 /// Mask (1 bit: 1 << 3)
629 pub const mask: u32 = 1 << offset;
630 /// Read-only values (empty)
631 pub mod R {}
632 /// Write-only values (empty)
633 pub mod W {}
634 /// Read-write values (empty)
635 pub mod RW {}
636 }
637
638 /// SVC call active bit
639 pub mod SVCALLACT {
640 /// Offset (7 bits)
641 pub const offset: u32 = 7;
642 /// Mask (1 bit: 1 << 7)
643 pub const mask: u32 = 1 << offset;
644 /// Read-only values (empty)
645 pub mod R {}
646 /// Write-only values (empty)
647 pub mod W {}
648 /// Read-write values (empty)
649 pub mod RW {}
650 }
651
652 /// Debug monitor active bit
653 pub mod MONITORACT {
654 /// Offset (8 bits)
655 pub const offset: u32 = 8;
656 /// Mask (1 bit: 1 << 8)
657 pub const mask: u32 = 1 << offset;
658 /// Read-only values (empty)
659 pub mod R {}
660 /// Write-only values (empty)
661 pub mod W {}
662 /// Read-write values (empty)
663 pub mod RW {}
664 }
665
666 /// PendSV exception active bit
667 pub mod PENDSVACT {
668 /// Offset (10 bits)
669 pub const offset: u32 = 10;
670 /// Mask (1 bit: 1 << 10)
671 pub const mask: u32 = 1 << offset;
672 /// Read-only values (empty)
673 pub mod R {}
674 /// Write-only values (empty)
675 pub mod W {}
676 /// Read-write values (empty)
677 pub mod RW {}
678 }
679
680 /// SysTick exception active bit
681 pub mod SYSTICKACT {
682 /// Offset (11 bits)
683 pub const offset: u32 = 11;
684 /// Mask (1 bit: 1 << 11)
685 pub const mask: u32 = 1 << offset;
686 /// Read-only values (empty)
687 pub mod R {}
688 /// Write-only values (empty)
689 pub mod W {}
690 /// Read-write values (empty)
691 pub mod RW {}
692 }
693
694 /// Usage fault exception pending bit
695 pub mod USGFAULTPENDED {
696 /// Offset (12 bits)
697 pub const offset: u32 = 12;
698 /// Mask (1 bit: 1 << 12)
699 pub const mask: u32 = 1 << offset;
700 /// Read-only values (empty)
701 pub mod R {}
702 /// Write-only values (empty)
703 pub mod W {}
704 /// Read-write values (empty)
705 pub mod RW {}
706 }
707
708 /// Memory management fault exception pending bit
709 pub mod MEMFAULTPENDED {
710 /// Offset (13 bits)
711 pub const offset: u32 = 13;
712 /// Mask (1 bit: 1 << 13)
713 pub const mask: u32 = 1 << offset;
714 /// Read-only values (empty)
715 pub mod R {}
716 /// Write-only values (empty)
717 pub mod W {}
718 /// Read-write values (empty)
719 pub mod RW {}
720 }
721
722 /// Bus fault exception pending bit
723 pub mod BUSFAULTPENDED {
724 /// Offset (14 bits)
725 pub const offset: u32 = 14;
726 /// Mask (1 bit: 1 << 14)
727 pub const mask: u32 = 1 << offset;
728 /// Read-only values (empty)
729 pub mod R {}
730 /// Write-only values (empty)
731 pub mod W {}
732 /// Read-write values (empty)
733 pub mod RW {}
734 }
735
736 /// SVC call pending bit
737 pub mod SVCALLPENDED {
738 /// Offset (15 bits)
739 pub const offset: u32 = 15;
740 /// Mask (1 bit: 1 << 15)
741 pub const mask: u32 = 1 << offset;
742 /// Read-only values (empty)
743 pub mod R {}
744 /// Write-only values (empty)
745 pub mod W {}
746 /// Read-write values (empty)
747 pub mod RW {}
748 }
749
750 /// Memory management fault enable bit
751 pub mod MEMFAULTENA {
752 /// Offset (16 bits)
753 pub const offset: u32 = 16;
754 /// Mask (1 bit: 1 << 16)
755 pub const mask: u32 = 1 << offset;
756 /// Read-only values (empty)
757 pub mod R {}
758 /// Write-only values (empty)
759 pub mod W {}
760 /// Read-write values (empty)
761 pub mod RW {}
762 }
763
764 /// Bus fault enable bit
765 pub mod BUSFAULTENA {
766 /// Offset (17 bits)
767 pub const offset: u32 = 17;
768 /// Mask (1 bit: 1 << 17)
769 pub const mask: u32 = 1 << offset;
770 /// Read-only values (empty)
771 pub mod R {}
772 /// Write-only values (empty)
773 pub mod W {}
774 /// Read-write values (empty)
775 pub mod RW {}
776 }
777
778 /// Usage fault enable bit
779 pub mod USGFAULTENA {
780 /// Offset (18 bits)
781 pub const offset: u32 = 18;
782 /// Mask (1 bit: 1 << 18)
783 pub const mask: u32 = 1 << offset;
784 /// Read-only values (empty)
785 pub mod R {}
786 /// Write-only values (empty)
787 pub mod W {}
788 /// Read-write values (empty)
789 pub mod RW {}
790 }
791}
792
793/// Configurable fault status register
794pub mod CFSR_UFSR_BFSR_MMFSR {
795
796 /// IACCVIOL
797 pub mod IACCVIOL {
798 /// Offset (0 bits)
799 pub const offset: u32 = 0;
800 /// Mask (1 bit: 1 << 0)
801 pub const mask: u32 = 1 << offset;
802 /// Read-only values (empty)
803 pub mod R {}
804 /// Write-only values (empty)
805 pub mod W {}
806 /// Read-write values (empty)
807 pub mod RW {}
808 }
809
810 /// DACCVIOL
811 pub mod DACCVIOL {
812 /// Offset (1 bits)
813 pub const offset: u32 = 1;
814 /// Mask (1 bit: 1 << 1)
815 pub const mask: u32 = 1 << offset;
816 /// Read-only values (empty)
817 pub mod R {}
818 /// Write-only values (empty)
819 pub mod W {}
820 /// Read-write values (empty)
821 pub mod RW {}
822 }
823
824 /// MUNSTKERR
825 pub mod MUNSTKERR {
826 /// Offset (3 bits)
827 pub const offset: u32 = 3;
828 /// Mask (1 bit: 1 << 3)
829 pub const mask: u32 = 1 << offset;
830 /// Read-only values (empty)
831 pub mod R {}
832 /// Write-only values (empty)
833 pub mod W {}
834 /// Read-write values (empty)
835 pub mod RW {}
836 }
837
838 /// MSTKERR
839 pub mod MSTKERR {
840 /// Offset (4 bits)
841 pub const offset: u32 = 4;
842 /// Mask (1 bit: 1 << 4)
843 pub const mask: u32 = 1 << offset;
844 /// Read-only values (empty)
845 pub mod R {}
846 /// Write-only values (empty)
847 pub mod W {}
848 /// Read-write values (empty)
849 pub mod RW {}
850 }
851
852 /// MLSPERR
853 pub mod MLSPERR {
854 /// Offset (5 bits)
855 pub const offset: u32 = 5;
856 /// Mask (1 bit: 1 << 5)
857 pub const mask: u32 = 1 << offset;
858 /// Read-only values (empty)
859 pub mod R {}
860 /// Write-only values (empty)
861 pub mod W {}
862 /// Read-write values (empty)
863 pub mod RW {}
864 }
865
866 /// MMARVALID
867 pub mod MMARVALID {
868 /// Offset (7 bits)
869 pub const offset: u32 = 7;
870 /// Mask (1 bit: 1 << 7)
871 pub const mask: u32 = 1 << offset;
872 /// Read-only values (empty)
873 pub mod R {}
874 /// Write-only values (empty)
875 pub mod W {}
876 /// Read-write values (empty)
877 pub mod RW {}
878 }
879
880 /// Instruction bus error
881 pub mod IBUSERR {
882 /// Offset (8 bits)
883 pub const offset: u32 = 8;
884 /// Mask (1 bit: 1 << 8)
885 pub const mask: u32 = 1 << offset;
886 /// Read-only values (empty)
887 pub mod R {}
888 /// Write-only values (empty)
889 pub mod W {}
890 /// Read-write values (empty)
891 pub mod RW {}
892 }
893
894 /// Precise data bus error
895 pub mod PRECISERR {
896 /// Offset (9 bits)
897 pub const offset: u32 = 9;
898 /// Mask (1 bit: 1 << 9)
899 pub const mask: u32 = 1 << offset;
900 /// Read-only values (empty)
901 pub mod R {}
902 /// Write-only values (empty)
903 pub mod W {}
904 /// Read-write values (empty)
905 pub mod RW {}
906 }
907
908 /// Imprecise data bus error
909 pub mod IMPRECISERR {
910 /// Offset (10 bits)
911 pub const offset: u32 = 10;
912 /// Mask (1 bit: 1 << 10)
913 pub const mask: u32 = 1 << offset;
914 /// Read-only values (empty)
915 pub mod R {}
916 /// Write-only values (empty)
917 pub mod W {}
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// Bus fault on unstacking for a return from exception
923 pub mod UNSTKERR {
924 /// Offset (11 bits)
925 pub const offset: u32 = 11;
926 /// Mask (1 bit: 1 << 11)
927 pub const mask: u32 = 1 << offset;
928 /// Read-only values (empty)
929 pub mod R {}
930 /// Write-only values (empty)
931 pub mod W {}
932 /// Read-write values (empty)
933 pub mod RW {}
934 }
935
936 /// Bus fault on stacking for exception entry
937 pub mod STKERR {
938 /// Offset (12 bits)
939 pub const offset: u32 = 12;
940 /// Mask (1 bit: 1 << 12)
941 pub const mask: u32 = 1 << offset;
942 /// Read-only values (empty)
943 pub mod R {}
944 /// Write-only values (empty)
945 pub mod W {}
946 /// Read-write values (empty)
947 pub mod RW {}
948 }
949
950 /// Bus fault on floating-point lazy state preservation
951 pub mod LSPERR {
952 /// Offset (13 bits)
953 pub const offset: u32 = 13;
954 /// Mask (1 bit: 1 << 13)
955 pub const mask: u32 = 1 << offset;
956 /// Read-only values (empty)
957 pub mod R {}
958 /// Write-only values (empty)
959 pub mod W {}
960 /// Read-write values (empty)
961 pub mod RW {}
962 }
963
964 /// Bus Fault Address Register (BFAR) valid flag
965 pub mod BFARVALID {
966 /// Offset (15 bits)
967 pub const offset: u32 = 15;
968 /// Mask (1 bit: 1 << 15)
969 pub const mask: u32 = 1 << offset;
970 /// Read-only values (empty)
971 pub mod R {}
972 /// Write-only values (empty)
973 pub mod W {}
974 /// Read-write values (empty)
975 pub mod RW {}
976 }
977
978 /// Undefined instruction usage fault
979 pub mod UNDEFINSTR {
980 /// Offset (16 bits)
981 pub const offset: u32 = 16;
982 /// Mask (1 bit: 1 << 16)
983 pub const mask: u32 = 1 << offset;
984 /// Read-only values (empty)
985 pub mod R {}
986 /// Write-only values (empty)
987 pub mod W {}
988 /// Read-write values (empty)
989 pub mod RW {}
990 }
991
992 /// Invalid state usage fault
993 pub mod INVSTATE {
994 /// Offset (17 bits)
995 pub const offset: u32 = 17;
996 /// Mask (1 bit: 1 << 17)
997 pub const mask: u32 = 1 << offset;
998 /// Read-only values (empty)
999 pub mod R {}
1000 /// Write-only values (empty)
1001 pub mod W {}
1002 /// Read-write values (empty)
1003 pub mod RW {}
1004 }
1005
1006 /// Invalid PC load usage fault
1007 pub mod INVPC {
1008 /// Offset (18 bits)
1009 pub const offset: u32 = 18;
1010 /// Mask (1 bit: 1 << 18)
1011 pub const mask: u32 = 1 << offset;
1012 /// Read-only values (empty)
1013 pub mod R {}
1014 /// Write-only values (empty)
1015 pub mod W {}
1016 /// Read-write values (empty)
1017 pub mod RW {}
1018 }
1019
1020 /// No coprocessor usage fault.
1021 pub mod NOCP {
1022 /// Offset (19 bits)
1023 pub const offset: u32 = 19;
1024 /// Mask (1 bit: 1 << 19)
1025 pub const mask: u32 = 1 << offset;
1026 /// Read-only values (empty)
1027 pub mod R {}
1028 /// Write-only values (empty)
1029 pub mod W {}
1030 /// Read-write values (empty)
1031 pub mod RW {}
1032 }
1033
1034 /// Unaligned access usage fault
1035 pub mod UNALIGNED {
1036 /// Offset (24 bits)
1037 pub const offset: u32 = 24;
1038 /// Mask (1 bit: 1 << 24)
1039 pub const mask: u32 = 1 << offset;
1040 /// Read-only values (empty)
1041 pub mod R {}
1042 /// Write-only values (empty)
1043 pub mod W {}
1044 /// Read-write values (empty)
1045 pub mod RW {}
1046 }
1047
1048 /// Divide by zero usage fault
1049 pub mod DIVBYZERO {
1050 /// Offset (25 bits)
1051 pub const offset: u32 = 25;
1052 /// Mask (1 bit: 1 << 25)
1053 pub const mask: u32 = 1 << offset;
1054 /// Read-only values (empty)
1055 pub mod R {}
1056 /// Write-only values (empty)
1057 pub mod W {}
1058 /// Read-write values (empty)
1059 pub mod RW {}
1060 }
1061}
1062
1063/// Hard fault status register
1064pub mod HFSR {
1065
1066 /// Vector table hard fault
1067 pub mod VECTTBL {
1068 /// Offset (1 bits)
1069 pub const offset: u32 = 1;
1070 /// Mask (1 bit: 1 << 1)
1071 pub const mask: u32 = 1 << offset;
1072 /// Read-only values (empty)
1073 pub mod R {}
1074 /// Write-only values (empty)
1075 pub mod W {}
1076 /// Read-write values (empty)
1077 pub mod RW {}
1078 }
1079
1080 /// Forced hard fault
1081 pub mod FORCED {
1082 /// Offset (30 bits)
1083 pub const offset: u32 = 30;
1084 /// Mask (1 bit: 1 << 30)
1085 pub const mask: u32 = 1 << offset;
1086 /// Read-only values (empty)
1087 pub mod R {}
1088 /// Write-only values (empty)
1089 pub mod W {}
1090 /// Read-write values (empty)
1091 pub mod RW {}
1092 }
1093
1094 /// Reserved for Debug use
1095 pub mod DEBUG_VT {
1096 /// Offset (31 bits)
1097 pub const offset: u32 = 31;
1098 /// Mask (1 bit: 1 << 31)
1099 pub const mask: u32 = 1 << offset;
1100 /// Read-only values (empty)
1101 pub mod R {}
1102 /// Write-only values (empty)
1103 pub mod W {}
1104 /// Read-write values (empty)
1105 pub mod RW {}
1106 }
1107}
1108
1109/// Memory management fault address register
1110pub mod MMFAR {
1111
1112 /// Memory management fault address
1113 pub mod ADDRESS {
1114 /// Offset (0 bits)
1115 pub const offset: u32 = 0;
1116 /// Mask (32 bits: 0xffffffff << 0)
1117 pub const mask: u32 = 0xffffffff << offset;
1118 /// Read-only values (empty)
1119 pub mod R {}
1120 /// Write-only values (empty)
1121 pub mod W {}
1122 /// Read-write values (empty)
1123 pub mod RW {}
1124 }
1125}
1126
1127/// Bus fault address register
1128pub mod BFAR {
1129 pub use super::MMFAR::ADDRESS;
1130}
1131#[repr(C)]
1132pub struct RegisterBlock {
1133 /// CPUID base register
1134 pub CPUID: RORegister<u32>,
1135
1136 /// Interrupt control and state register
1137 pub ICSR: RWRegister<u32>,
1138
1139 /// Vector table offset register
1140 pub VTOR: RWRegister<u32>,
1141
1142 /// Application interrupt and reset control register
1143 pub AIRCR: RWRegister<u32>,
1144
1145 /// System control register
1146 pub SCR: RWRegister<u32>,
1147
1148 /// Configuration and control register
1149 pub CCR: RWRegister<u32>,
1150
1151 /// System handler priority registers
1152 pub SHPR1: RWRegister<u32>,
1153
1154 /// System handler priority registers
1155 pub SHPR2: RWRegister<u32>,
1156
1157 /// System handler priority registers
1158 pub SHPR3: RWRegister<u32>,
1159
1160 /// System handler control and state register
1161 pub SHCRS: RWRegister<u32>,
1162
1163 /// Configurable fault status register
1164 pub CFSR_UFSR_BFSR_MMFSR: RWRegister<u32>,
1165
1166 /// Hard fault status register
1167 pub HFSR: RWRegister<u32>,
1168
1169 _reserved1: [u8; 4],
1170
1171 /// Memory management fault address register
1172 pub MMFAR: RWRegister<u32>,
1173
1174 /// Bus fault address register
1175 pub BFAR: RWRegister<u32>,
1176}
1177pub struct ResetValues {
1178 pub CPUID: u32,
1179 pub ICSR: u32,
1180 pub VTOR: u32,
1181 pub AIRCR: u32,
1182 pub SCR: u32,
1183 pub CCR: u32,
1184 pub SHPR1: u32,
1185 pub SHPR2: u32,
1186 pub SHPR3: u32,
1187 pub SHCRS: u32,
1188 pub CFSR_UFSR_BFSR_MMFSR: u32,
1189 pub HFSR: u32,
1190 pub MMFAR: u32,
1191 pub BFAR: u32,
1192}
1193#[cfg(not(feature = "nosync"))]
1194pub struct Instance {
1195 pub(crate) addr: u32,
1196 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1197}
1198#[cfg(not(feature = "nosync"))]
1199impl ::core::ops::Deref for Instance {
1200 type Target = RegisterBlock;
1201 #[inline(always)]
1202 fn deref(&self) -> &RegisterBlock {
1203 unsafe { &*(self.addr as *const _) }
1204 }
1205}
1206#[cfg(feature = "rtic")]
1207unsafe impl Send for Instance {}