stm32ral 0.8.0

#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! Operational amplifiers
//!
//! Used by: stm32l4x1, stm32l4x2, stm32l4x3, stm32l4x5, stm32l4x6

use crate::RWRegister;
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;

/// OPAMP1 control/status register
pub mod OPAMP1_CSR {

    /// Operational amplifier Enable
    pub mod OPAEN {
        /// Offset (0 bits)
        pub const offset: u32 = 0;
        /// Mask (1 bit: 1 << 0)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: OpAmp disabled
            pub const Disabled: u32 = 0b0;

            /// 0b1: OpAmp enabled
            pub const Enabled: u32 = 0b1;
        }
    }

    /// Operational amplifier Low Power Mode
    pub mod OPALPM {
        /// Offset (1 bits)
        pub const offset: u32 = 1;
        /// Mask (1 bit: 1 << 1)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: OpAmp in normal mode
            pub const NORMAL: u32 = 0b0;

            /// 0b1: OpAmp in low power mode
            pub const LOW: u32 = 0b1;
        }
    }

    /// Operational amplifier PGA mode
    pub mod OPAMODE {
        /// Offset (2 bits)
        pub const offset: u32 = 2;
        /// Mask (2 bits: 0b11 << 2)
        pub const mask: u32 = 0b11 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b00: internal PGA diabled
            pub const PGA_DISABLED: u32 = 0b00;

            /// 0b10: internal PGA enabled, gain programmed in PGA_GAIN
            pub const PGA_ENABLED: u32 = 0b10;

            /// 0b11: internal follower
            pub const FOLLOWER: u32 = 0b11;
        }
    }

    /// Operational amplifier Programmable amplifier gain value
    pub mod PGA_GAIN {
        /// Offset (4 bits)
        pub const offset: u32 = 4;
        /// Mask (2 bits: 0b11 << 4)
        pub const mask: u32 = 0b11 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b00: Gain 2
            pub const Gain2: u32 = 0b00;

            /// 0b01: Gain 4
            pub const Gain4: u32 = 0b01;

            /// 0b10: Gain 8
            pub const Gain8: u32 = 0b10;

            /// 0b11: Gain 16
            pub const Gain16: u32 = 0b11;
        }
    }

    /// Inverting input selection
    pub mod VM_SEL {
        /// Offset (8 bits)
        pub const offset: u32 = 8;
        /// Mask (2 bits: 0b11 << 8)
        pub const mask: u32 = 0b11 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b00: GPIO connectet to VINM
            pub const GPIO: u32 = 0b00;

            /// 0b01: Low leakage inputs connecte (only available in certen BGA cases
            pub const LOW_LEAKAGE: u32 = 0b01;

            /// 0b10: OPAMP in PGA mode
            pub const PGA_MODE: u32 = 0b10;
        }
    }

    /// Non inverted input selection
    pub mod VP_SEL {
        /// Offset (10 bits)
        pub const offset: u32 = 10;
        /// Mask (1 bit: 1 << 10)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: GPIO connectet to VINP
            pub const GPIO: u32 = 0b0;

            /// 0b1: DAC connected to VPINP
            pub const DAC: u32 = 0b1;
        }
    }

    /// Calibration mode enabled
    pub mod CALON {
        /// Offset (12 bits)
        pub const offset: u32 = 12;
        /// Mask (1 bit: 1 << 12)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: Normal mode
            pub const Disabled: u32 = 0b0;

            /// 0b1: Calibration mode
            pub const Enabled: u32 = 0b1;
        }
    }

    /// Calibration selection
    pub mod CALSEL {
        /// Offset (13 bits)
        pub const offset: u32 = 13;
        /// Mask (1 bit: 1 << 13)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: 0.2V applied to OPAMP inputs during calibration
            pub const NMOS: u32 = 0b0;

            /// 0b1: VDDA-0.2V applied to OPAMP inputs during calibration"
            pub const PMOS: u32 = 0b1;
        }
    }

    /// allows to switch from AOP offset trimmed values to AOP offset
    pub mod USERTRIM {
        /// Offset (14 bits)
        pub const offset: u32 = 14;
        /// Mask (1 bit: 1 << 14)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: Factory trim used
            pub const Factory: u32 = 0b0;

            /// 0b1: User trim used
            pub const User: u32 = 0b1;
        }
    }

    /// Operational amplifier calibration output
    pub mod CALOUT {
        /// Offset (15 bits)
        pub const offset: u32 = 15;
        /// Mask (1 bit: 1 << 15)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Operational amplifier power supply range for stability
    pub mod OPA_RANGE {
        /// Offset (31 bits)
        pub const offset: u32 = 31;
        /// Mask (1 bit: 1 << 31)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: low range (VDDA < 2.4V
            pub const LOW: u32 = 0b0;

            /// 0b1: low range (VDDA >2.4V
            pub const HIGH: u32 = 0b1;
        }
    }
}

/// OPAMP1 offset trimming register in normal mode
pub mod OPAMP1_OTR {

    /// Trim for NMOS differential pairs
    pub mod TRIMOFFSETN {
        /// Offset (0 bits)
        pub const offset: u32 = 0;
        /// Mask (5 bits: 0b11111 << 0)
        pub const mask: u32 = 0b11111 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Trim for PMOS differential pairs
    pub mod TRIMOFFSETP {
        /// Offset (8 bits)
        pub const offset: u32 = 8;
        /// Mask (5 bits: 0b11111 << 8)
        pub const mask: u32 = 0b11111 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// OPAMP1 offset trimming register in low-power mode
pub mod OPAMP1_LPOTR {

    /// Trim for NMOS differential pairs
    pub mod TRIMLPOFFSETN {
        /// Offset (0 bits)
        pub const offset: u32 = 0;
        /// Mask (5 bits: 0b11111 << 0)
        pub const mask: u32 = 0b11111 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Trim for PMOS differential pairs
    pub mod TRIMLPOFFSETP {
        /// Offset (8 bits)
        pub const offset: u32 = 8;
        /// Mask (5 bits: 0b11111 << 8)
        pub const mask: u32 = 0b11111 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// OPAMP2 control/status register
pub mod OPAMP2_CSR {

    /// Operational amplifier Enable
    pub mod OPAEN {
        /// Offset (0 bits)
        pub const offset: u32 = 0;
        /// Mask (1 bit: 1 << 0)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: OpAmp disabled
            pub const Disabled: u32 = 0b0;

            /// 0b1: OpAmp enabled
            pub const Enabled: u32 = 0b1;
        }
    }

    /// Operational amplifier Low Power Mode
    pub mod OPALPM {
        /// Offset (1 bits)
        pub const offset: u32 = 1;
        /// Mask (1 bit: 1 << 1)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: OpAmp in normal mode
            pub const NORMAL: u32 = 0b0;

            /// 0b1: OpAmp in low power mode
            pub const LOW: u32 = 0b1;
        }
    }

    /// Operational amplifier PGA mode
    pub mod OPAMODE {
        /// Offset (2 bits)
        pub const offset: u32 = 2;
        /// Mask (2 bits: 0b11 << 2)
        pub const mask: u32 = 0b11 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b00: internal PGA diabled
            pub const PGA_DISABLED: u32 = 0b00;

            /// 0b10: internal PGA enabled, gain programmed in PGA_GAIN
            pub const PGA_ENABLED: u32 = 0b10;

            /// 0b11: internal follower
            pub const FOLLOWER: u32 = 0b11;
        }
    }

    /// Operational amplifier Programmable amplifier gain value
    pub mod PGA_GAIN {
        /// Offset (4 bits)
        pub const offset: u32 = 4;
        /// Mask (2 bits: 0b11 << 4)
        pub const mask: u32 = 0b11 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b00: Gain 2
            pub const Gain2: u32 = 0b00;

            /// 0b01: Gain 4
            pub const Gain4: u32 = 0b01;

            /// 0b10: Gain 8
            pub const Gain8: u32 = 0b10;

            /// 0b11: Gain 16
            pub const Gain16: u32 = 0b11;
        }
    }

    /// Inverting input selection
    pub mod VM_SEL {
        /// Offset (8 bits)
        pub const offset: u32 = 8;
        /// Mask (2 bits: 0b11 << 8)
        pub const mask: u32 = 0b11 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b00: GPIO connectet to VINM
            pub const GPIO: u32 = 0b00;

            /// 0b01: Low leakage inputs connecte (only available in certen BGA cases
            pub const LOW_LEAKAGE: u32 = 0b01;

            /// 0b10: OPAMP in PGA mode
            pub const PGA_MODE: u32 = 0b10;
        }
    }

    /// Non inverted input selection
    pub mod VP_SEL {
        /// Offset (10 bits)
        pub const offset: u32 = 10;
        /// Mask (1 bit: 1 << 10)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: GPIO connectet to VINP
            pub const GPIO: u32 = 0b0;

            /// 0b1: DAC connected to VPINP
            pub const DAC: u32 = 0b1;
        }
    }

    /// Calibration mode enabled
    pub mod CALON {
        /// Offset (12 bits)
        pub const offset: u32 = 12;
        /// Mask (1 bit: 1 << 12)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: Normal mode
            pub const Disabled: u32 = 0b0;

            /// 0b1: Calibration mode
            pub const Enabled: u32 = 0b1;
        }
    }

    /// Calibration selection
    pub mod CALSEL {
        /// Offset (13 bits)
        pub const offset: u32 = 13;
        /// Mask (1 bit: 1 << 13)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: 0.2V applied to OPAMP inputs during calibration
            pub const NMOS: u32 = 0b0;

            /// 0b1: VDDA-0.2V applied to OPAMP inputs during calibration"
            pub const PMOS: u32 = 0b1;
        }
    }

    /// allows to switch from AOP offset trimmed values to AOP offset
    pub mod USERTRIM {
        /// Offset (14 bits)
        pub const offset: u32 = 14;
        /// Mask (1 bit: 1 << 14)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values
        pub mod RW {

            /// 0b0: Factory trim used
            pub const Factory: u32 = 0b0;

            /// 0b1: User trim used
            pub const User: u32 = 0b1;
        }
    }

    /// Operational amplifier calibration output
    pub mod CALOUT {
        /// Offset (15 bits)
        pub const offset: u32 = 15;
        /// Mask (1 bit: 1 << 15)
        pub const mask: u32 = 1 << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// OPAMP2 offset trimming register in normal mode
pub mod OPAMP2_OTR {
    pub use super::OPAMP1_OTR::TRIMOFFSETN;
    pub use super::OPAMP1_OTR::TRIMOFFSETP;
}

/// OPAMP2 offset trimming register in low-power mode
pub mod OPAMP2_LPOTR {
    pub use super::OPAMP1_LPOTR::TRIMLPOFFSETN;
    pub use super::OPAMP1_LPOTR::TRIMLPOFFSETP;
}
#[repr(C)]
pub struct RegisterBlock {
    /// OPAMP1 control/status register
    pub OPAMP1_CSR: RWRegister<u32>,

    /// OPAMP1 offset trimming register in normal mode
    pub OPAMP1_OTR: RWRegister<u32>,

    /// OPAMP1 offset trimming register in low-power mode
    pub OPAMP1_LPOTR: RWRegister<u32>,

    _reserved1: [u8; 4],

    /// OPAMP2 control/status register
    pub OPAMP2_CSR: RWRegister<u32>,

    /// OPAMP2 offset trimming register in normal mode
    pub OPAMP2_OTR: RWRegister<u32>,

    /// OPAMP2 offset trimming register in low-power mode
    pub OPAMP2_LPOTR: RWRegister<u32>,
}
pub struct ResetValues {
    pub OPAMP1_CSR: u32,
    pub OPAMP1_OTR: u32,
    pub OPAMP1_LPOTR: u32,
    pub OPAMP2_CSR: u32,
    pub OPAMP2_OTR: u32,
    pub OPAMP2_LPOTR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
    pub(crate) addr: u32,
    pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
    type Target = RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &RegisterBlock {
        unsafe { &*(self.addr as *const _) }
    }
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}