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#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! System configuration controller
//!
//! Used by: stm32f401, stm32f411
use crate::{RORegister, RWRegister};
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// memory remap register
pub mod MEMRM {
/// MEM_MODE
pub mod MEM_MODE {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (2 bits: 0b11 << 0)
pub const mask: u32 = 0b11 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// peripheral mode configuration register
pub mod PMC {
/// ADC1DC2
pub mod ADC1DC2 {
/// Offset (16 bits)
pub const offset: u32 = 16;
/// Mask (1 bit: 1 << 16)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// external interrupt configuration register 1
pub mod EXTICR1 {
/// EXTI x configuration (x = 0 to 3)
pub mod EXTI3 {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (4 bits: 0b1111 << 12)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 0 to 3)
pub mod EXTI2 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 0 to 3)
pub mod EXTI1 {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 0 to 3)
pub mod EXTI0 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// external interrupt configuration register 2
pub mod EXTICR2 {
/// EXTI x configuration (x = 4 to 7)
pub mod EXTI7 {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (4 bits: 0b1111 << 12)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 4 to 7)
pub mod EXTI6 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 4 to 7)
pub mod EXTI5 {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 4 to 7)
pub mod EXTI4 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// external interrupt configuration register 3
pub mod EXTICR3 {
/// EXTI x configuration (x = 8 to 11)
pub mod EXTI11 {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (4 bits: 0b1111 << 12)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI10
pub mod EXTI10 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 8 to 11)
pub mod EXTI9 {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 8 to 11)
pub mod EXTI8 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// external interrupt configuration register 4
pub mod EXTICR4 {
/// EXTI x configuration (x = 12 to 15)
pub mod EXTI15 {
/// Offset (12 bits)
pub const offset: u32 = 12;
/// Mask (4 bits: 0b1111 << 12)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 12 to 15)
pub mod EXTI14 {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (4 bits: 0b1111 << 8)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 12 to 15)
pub mod EXTI13 {
/// Offset (4 bits)
pub const offset: u32 = 4;
/// Mask (4 bits: 0b1111 << 4)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// EXTI x configuration (x = 12 to 15)
pub mod EXTI12 {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (4 bits: 0b1111 << 0)
pub const mask: u32 = 0b1111 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// Compensation cell control register
pub mod CMPCR {
/// READY
pub mod READY {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (1 bit: 1 << 8)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// Compensation cell power-down
pub mod CMP_PD {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
#[repr(C)]
pub struct RegisterBlock {
/// memory remap register
pub MEMRM: RWRegister<u32>,
/// peripheral mode configuration register
pub PMC: RWRegister<u32>,
/// external interrupt configuration register 1
pub EXTICR1: RWRegister<u32>,
/// external interrupt configuration register 2
pub EXTICR2: RWRegister<u32>,
/// external interrupt configuration register 3
pub EXTICR3: RWRegister<u32>,
/// external interrupt configuration register 4
pub EXTICR4: RWRegister<u32>,
_reserved1: [u32; 2],
/// Compensation cell control register
pub CMPCR: RORegister<u32>,
}
pub struct ResetValues {
pub MEMRM: u32,
pub PMC: u32,
pub EXTICR1: u32,
pub EXTICR2: u32,
pub EXTICR3: u32,
pub EXTICR4: u32,
pub CMPCR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtic")]
unsafe impl Send for Instance {}