Module stm32mp1::stm32mp157::otg::otg_hs_diepeachmsk1

Expand description

This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

Structs

OTG_HS_DIEPEACHMSK1_SPEC

This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

R

Register OTG_HS_DIEPEACHMSK1 reader

W

Register OTG_HS_DIEPEACHMSK1 writer