stm32mp1 0.16.0

/*!Peripheral access API for STM32MP157 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))

You can find an overview of the generated API [here].

API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.

[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
    fn WWDG1_IT();
    fn PVD_AVD();
    fn TAMP();
    fn RTC_WKUP_ALARM();
    fn TZC_IT();
    fn RCC();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2();
    fn EXTI3();
    fn EXTI4();
    fn DMA1_STR0();
    fn DMA1_STR1();
    fn DMA1_STR2();
    fn DMA1_STR3();
    fn DMA1_STR4();
    fn DMA1_STR5();
    fn DMA1_STR6();
    fn ADC1();
    fn FDCAN1_IT0();
    fn FDCAN2_IT0();
    fn FDCAN1_IT1();
    fn FDCAN2_IT1();
    fn EXTI5();
    fn TIM1_BRK();
    fn TIM1_UP();
    fn TIM1_TRG_COM();
    fn TIM1_CC();
    fn TIM2();
    fn TIM3();
    fn TIM4();
    fn I2C1_EVT();
    fn I2C1_ERR();
    fn I2C2_EVT();
    fn I2C2_ERR();
    fn SPI1();
    fn SPI2();
    fn USART1();
    fn USART2();
    fn USART3();
    fn EXTI10();
    fn RTC_TS();
    fn EXTI11();
    fn TIM8_BRK();
    fn TIM8_UP();
    fn TIM8_TRG_COM();
    fn TIM8_CC();
    fn DMA1_STR7();
    fn FMC();
    fn SDMMC1();
    fn TIM5();
    fn SPI3();
    fn USART4();
    fn USART5();
    fn TIM6();
    fn TIM7();
    fn DMA2_STR0();
    fn DMA2_STR1();
    fn DMA2_STR2();
    fn DMA2_STR3();
    fn DMA2_STR4();
    fn ETH1();
    fn ETH1_WKUP();
    fn EXTI6();
    fn EXTI7();
    fn EXTI8();
    fn EXTI9();
    fn DMA2_STR5();
    fn DMA2_STR6();
    fn DMA2_STR7();
    fn USART6();
    fn I2C3_EVT();
    fn I2C3_ERR();
    fn EXTI12();
    fn EXTI13();
    fn DCMI();
    fn CRYP1();
    fn HASH1();
    fn USART7();
    fn USART8();
    fn SPI4();
    fn SPI5();
    fn SPI6();
    fn SAI1();
    fn LTDC();
    fn LTDC_ER();
    fn ADC2();
    fn SAI2();
    fn QUADSPI();
    fn LPTIM1();
    fn CEC();
    fn I2C4_EVT();
    fn I2C4_ERR();
    fn SPDIFRX();
    fn OTG();
    fn IPCC_RX0();
    fn IPCC_TX0();
    fn DMAMUX1_OVR_REQ();
    fn IPCC_RX1();
    fn IPCC_TX1();
    fn CRYP2();
    fn HASH2();
    fn I2C5_EVT();
    fn I2C5_ERR();
    fn DFSDM1_FLT0();
    fn DFSDM1_FLT1();
    fn DFSDM1_FLT2();
    fn DFSDM1_FLT3();
    fn SAI3();
    fn DFSDM1_FLT4();
    fn TIM15();
    fn TIM16();
    fn TIM17();
    fn TIM12();
    fn MDIOS();
    fn EXTI14();
    fn MDMA();
    fn DSI();
    fn SDMMC2();
    fn HSEM_IT2();
    fn DFSDM1_FLT5();
    fn EXTI15();
    fn TIM13();
    fn TIM14();
    fn DAC();
    fn RNG1();
    fn RNG2();
    fn I2C6_EVT();
    fn I2C6_ERR();
    fn SDMMC3();
    fn LPTIM2();
    fn LPTIM3();
    fn LPTIM4();
    fn LPTIM5();
    fn ETH1_LPI();
    fn RCC_WAKEUP();
    fn SAI4();
    fn DTS();
    fn IWDG1_IT();
    fn IWDG2_IT();
    fn TAMP_S();
    fn RTC_WKUP_ALARM_S();
    fn RTC_TS_S();
    fn DDRPERFM();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 214] = [
    Vector { _handler: WWDG1_IT },
    Vector { _handler: PVD_AVD },
    Vector { _handler: TAMP },
    Vector {
        _handler: RTC_WKUP_ALARM,
    },
    Vector { _handler: TZC_IT },
    Vector { _handler: RCC },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector { _handler: EXTI2 },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector {
        _handler: DMA1_STR0,
    },
    Vector {
        _handler: DMA1_STR1,
    },
    Vector {
        _handler: DMA1_STR2,
    },
    Vector {
        _handler: DMA1_STR3,
    },
    Vector {
        _handler: DMA1_STR4,
    },
    Vector {
        _handler: DMA1_STR5,
    },
    Vector {
        _handler: DMA1_STR6,
    },
    Vector { _handler: ADC1 },
    Vector {
        _handler: FDCAN1_IT0,
    },
    Vector {
        _handler: FDCAN2_IT0,
    },
    Vector {
        _handler: FDCAN1_IT1,
    },
    Vector {
        _handler: FDCAN2_IT1,
    },
    Vector { _handler: EXTI5 },
    Vector { _handler: TIM1_BRK },
    Vector { _handler: TIM1_UP },
    Vector {
        _handler: TIM1_TRG_COM,
    },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _handler: TIM3 },
    Vector { _handler: TIM4 },
    Vector { _handler: I2C1_EVT },
    Vector { _handler: I2C1_ERR },
    Vector { _handler: I2C2_EVT },
    Vector { _handler: I2C2_ERR },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: USART1 },
    Vector { _handler: USART2 },
    Vector { _handler: USART3 },
    Vector { _handler: EXTI10 },
    Vector { _handler: RTC_TS },
    Vector { _handler: EXTI11 },
    Vector { _handler: TIM8_BRK },
    Vector { _handler: TIM8_UP },
    Vector {
        _handler: TIM8_TRG_COM,
    },
    Vector { _handler: TIM8_CC },
    Vector {
        _handler: DMA1_STR7,
    },
    Vector { _handler: FMC },
    Vector { _handler: SDMMC1 },
    Vector { _handler: TIM5 },
    Vector { _handler: SPI3 },
    Vector { _handler: USART4 },
    Vector { _handler: USART5 },
    Vector { _handler: TIM6 },
    Vector { _handler: TIM7 },
    Vector {
        _handler: DMA2_STR0,
    },
    Vector {
        _handler: DMA2_STR1,
    },
    Vector {
        _handler: DMA2_STR2,
    },
    Vector {
        _handler: DMA2_STR3,
    },
    Vector {
        _handler: DMA2_STR4,
    },
    Vector { _handler: ETH1 },
    Vector {
        _handler: ETH1_WKUP,
    },
    Vector { _reserved: 0 },
    Vector { _handler: EXTI6 },
    Vector { _handler: EXTI7 },
    Vector { _handler: EXTI8 },
    Vector { _handler: EXTI9 },
    Vector {
        _handler: DMA2_STR5,
    },
    Vector {
        _handler: DMA2_STR6,
    },
    Vector {
        _handler: DMA2_STR7,
    },
    Vector { _handler: USART6 },
    Vector { _handler: I2C3_EVT },
    Vector { _handler: I2C3_ERR },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: EXTI12 },
    Vector { _handler: EXTI13 },
    Vector { _handler: DCMI },
    Vector { _handler: CRYP1 },
    Vector { _handler: HASH1 },
    Vector { _reserved: 0 },
    Vector { _handler: USART7 },
    Vector { _handler: USART8 },
    Vector { _handler: SPI4 },
    Vector { _handler: SPI5 },
    Vector { _handler: SPI6 },
    Vector { _handler: SAI1 },
    Vector { _handler: LTDC },
    Vector { _handler: LTDC_ER },
    Vector { _handler: ADC2 },
    Vector { _handler: SAI2 },
    Vector { _handler: QUADSPI },
    Vector { _handler: LPTIM1 },
    Vector { _handler: CEC },
    Vector { _handler: I2C4_EVT },
    Vector { _handler: I2C4_ERR },
    Vector { _handler: SPDIFRX },
    Vector { _handler: OTG },
    Vector { _reserved: 0 },
    Vector { _handler: IPCC_RX0 },
    Vector { _handler: IPCC_TX0 },
    Vector {
        _handler: DMAMUX1_OVR_REQ,
    },
    Vector { _handler: IPCC_RX1 },
    Vector { _handler: IPCC_TX1 },
    Vector { _handler: CRYP2 },
    Vector { _handler: HASH2 },
    Vector { _handler: I2C5_EVT },
    Vector { _handler: I2C5_ERR },
    Vector { _reserved: 0 },
    Vector {
        _handler: DFSDM1_FLT0,
    },
    Vector {
        _handler: DFSDM1_FLT1,
    },
    Vector {
        _handler: DFSDM1_FLT2,
    },
    Vector {
        _handler: DFSDM1_FLT3,
    },
    Vector { _handler: SAI3 },
    Vector {
        _handler: DFSDM1_FLT4,
    },
    Vector { _handler: TIM15 },
    Vector { _handler: TIM16 },
    Vector { _handler: TIM17 },
    Vector { _handler: TIM12 },
    Vector { _handler: MDIOS },
    Vector { _handler: EXTI14 },
    Vector { _handler: MDMA },
    Vector { _handler: DSI },
    Vector { _handler: SDMMC2 },
    Vector { _handler: HSEM_IT2 },
    Vector {
        _handler: DFSDM1_FLT5,
    },
    Vector { _handler: EXTI15 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: TIM13 },
    Vector { _handler: TIM14 },
    Vector { _handler: DAC },
    Vector { _handler: RNG1 },
    Vector { _handler: RNG2 },
    Vector { _handler: I2C6_EVT },
    Vector { _handler: I2C6_ERR },
    Vector { _handler: SDMMC3 },
    Vector { _handler: LPTIM2 },
    Vector { _handler: LPTIM3 },
    Vector { _handler: LPTIM4 },
    Vector { _handler: LPTIM5 },
    Vector { _handler: ETH1_LPI },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector {
        _handler: RCC_WAKEUP,
    },
    Vector { _handler: SAI4 },
    Vector { _handler: DTS },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: IWDG1_IT },
    Vector { _handler: IWDG2_IT },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: TAMP_S },
    Vector {
        _handler: RTC_WKUP_ALARM_S,
    },
    Vector { _handler: RTC_TS_S },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: DDRPERFM },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///0 - Window Watchdog interrupt
    WWDG1_IT = 0,
    ///1 - PVD AND AVD detector through EXTI
    PVD_AVD = 1,
    ///2 - Tamper interrupt (include LSECSS interrupts)
    TAMP = 2,
    ///3 - RTC Tamper or TimeStamp
    RTC_WKUP_ALARM = 3,
    ///4 - TrustZone DDR address space controller
    TZC_IT = 4,
    ///5 - RCC global interrupt
    RCC = 5,
    ///6 - EXTI Line 0 interrupt
    EXTI0 = 6,
    ///7 - EXTI Line 1 interrupt
    EXTI1 = 7,
    ///8 - EXTI Line 2 interrupt
    EXTI2 = 8,
    ///9 - EXTI Line 3 interrupt
    EXTI3 = 9,
    ///10 - EXTI Line 4 interrupt
    EXTI4 = 10,
    ///11 - DMA1 stream0 global interrupt
    DMA1_STR0 = 11,
    ///12 - DMA1 stream1 global interrupt
    DMA1_STR1 = 12,
    ///13 - DMA1 stream2 global interrupt
    DMA1_STR2 = 13,
    ///14 - DMA1 stream3 global interrupt
    DMA1_STR3 = 14,
    ///15 - DMA1 stream4 global interrupt
    DMA1_STR4 = 15,
    ///16 - DMA1 stream5 global interrupt
    DMA1_STR5 = 16,
    ///17 - DMA1 stream6 global interrupt
    DMA1_STR6 = 17,
    ///18 - ADC1 global interrupt
    ADC1 = 18,
    ///19 - FDCAN1 interrupt 0
    FDCAN1_IT0 = 19,
    ///20 - FDCAN2 interrupt 0
    FDCAN2_IT0 = 20,
    ///21 - FDCAN1 interrupt 1
    FDCAN1_IT1 = 21,
    ///22 - FDCAN2 interrupt 1
    FDCAN2_IT1 = 22,
    ///23 - EXTI line 5 interrupt
    EXTI5 = 23,
    ///24 - TIM1 break interrupt
    TIM1_BRK = 24,
    ///25 - TIM1 update interrupt
    TIM1_UP = 25,
    ///26 - TIM1 trigger and commutation interrupt
    TIM1_TRG_COM = 26,
    ///27 - TIM1 capture compare interrupt
    TIM1_CC = 27,
    ///28 - TIM2 global interrupt
    TIM2 = 28,
    ///29 - TIM3 global interrupt
    TIM3 = 29,
    ///30 - TIM4 global interrupt
    TIM4 = 30,
    ///31 - I2C1 event interrupt
    I2C1_EVT = 31,
    ///32 - I2C1 global error interrupt
    I2C1_ERR = 32,
    ///33 - I2C2 event interrupt
    I2C2_EVT = 33,
    ///34 - I2C2 global error interrupt
    I2C2_ERR = 34,
    ///35 - SPI1 global interrupt
    SPI1 = 35,
    ///36 - SPI2 global interrupt
    SPI2 = 36,
    ///37 - USART1 global interrupt
    USART1 = 37,
    ///38 - USART2 global interrupt
    USART2 = 38,
    ///39 - USART3 global interrupt
    USART3 = 39,
    ///40 - EXTI line 10 interrupt
    EXTI10 = 40,
    ///41 - RTC timestamp interrupt
    RTC_TS = 41,
    ///42 - EXTI line 11 interrupt
    EXTI11 = 42,
    ///43 - TIM8 break interrupt
    TIM8_BRK = 43,
    ///44 - TIM8 update interrupt
    TIM8_UP = 44,
    ///45 - TIM8 trigger and commutation interrupt
    TIM8_TRG_COM = 45,
    ///46 - TIM8 capture compare interrupt
    TIM8_CC = 46,
    ///47 - DMA1 stream7 global interrupt
    DMA1_STR7 = 47,
    ///48 - FMC global interrupt
    FMC = 48,
    ///49 - SDMMC1 global interrupt
    SDMMC1 = 49,
    ///50 - TIM5 global interrupt
    TIM5 = 50,
    ///51 - SPI3 global interrupt
    SPI3 = 51,
    ///52 - USART4 global interrupt
    USART4 = 52,
    ///53 - USART5 global interrupt
    USART5 = 53,
    ///54 - TIM6 global interrupt
    TIM6 = 54,
    ///55 - TIM7 global interrupt
    TIM7 = 55,
    ///56 - DMA2 stream0 global interrupt
    DMA2_STR0 = 56,
    ///57 - DMA2 stream1 global interrupt
    DMA2_STR1 = 57,
    ///58 - DMA2 stream2 global interrupt
    DMA2_STR2 = 58,
    ///59 - DMA2 stream3 global interrupt
    DMA2_STR3 = 59,
    ///60 - DMA2 stream4 global interrupt
    DMA2_STR4 = 60,
    ///61 - ETH1 global interrupt
    ETH1 = 61,
    ///62 - ETH1 wakeup interrupt
    ETH1_WKUP = 62,
    ///64 - EXTI line 6 interrupt
    EXTI6 = 64,
    ///65 - EXTI line 7 interrupt
    EXTI7 = 65,
    ///66 - EXTI line 8 interrupt
    EXTI8 = 66,
    ///67 - EXTI line 9 interrupt
    EXTI9 = 67,
    ///68 - DMA2 stream5 global interrupt
    DMA2_STR5 = 68,
    ///69 - DMA2 stream6 global interrupt
    DMA2_STR6 = 69,
    ///70 - DMA2 stream7 global interrupt
    DMA2_STR7 = 70,
    ///71 - USART6 global interrupt
    USART6 = 71,
    ///72 - I2C3 event interrupt
    I2C3_EVT = 72,
    ///73 - I2C3 global error interrupt
    I2C3_ERR = 73,
    ///76 - EXTI line 12 interrupt
    EXTI12 = 76,
    ///77 - EXTI line 13 interrupt
    EXTI13 = 77,
    ///78 - DCMI global interrupt
    DCMI = 78,
    ///79 - CRYP1 global interrupt
    CRYP1 = 79,
    ///80 - HASH1 interrupt
    HASH1 = 80,
    ///82 - USART7 global interrupt
    USART7 = 82,
    ///83 - USART8 global interrupt
    USART8 = 83,
    ///84 - SPI4 global interrupt
    SPI4 = 84,
    ///85 - SPI5 global interrupt
    SPI5 = 85,
    ///86 - SPI6 global interrupt
    SPI6 = 86,
    ///87 - SAI1 global interrupt
    SAI1 = 87,
    ///88 - LTCD global interrupt
    LTDC = 88,
    ///89 - LTCD global error interrupt
    LTDC_ER = 89,
    ///90 - ADC2 global interrupt
    ADC2 = 90,
    ///91 - SAI2 global interrupt
    SAI2 = 91,
    ///92 - QUADSPI global interrupt
    QUADSPI = 92,
    ///93 - LPTIMER1 global interrupt
    LPTIM1 = 93,
    ///94 - HDMI-CEC global interrupt
    CEC = 94,
    ///95 - I2C4 event interrupt
    I2C4_EVT = 95,
    ///96 - I2C4 global error interrupt
    I2C4_ERR = 96,
    ///97 - SPDIFRX global interrupt
    SPDIFRX = 97,
    ///98 - USB On-The-Go global interrupt
    OTG = 98,
    ///100 - IPCC RX0 occupied interrupt
    IPCC_RX0 = 100,
    ///101 - IPCC TX0 free interrupt
    IPCC_TX0 = 101,
    ///102 - DMAMUX1 overrun interrupt
    DMAMUX1_OVR_REQ = 102,
    ///103 - IPCC RX1 occupied interrupt
    IPCC_RX1 = 103,
    ///104 - IPCC TX1 free interrupt
    IPCC_TX1 = 104,
    ///105 - CRYP2 global interrupt
    CRYP2 = 105,
    ///106 - HASH2 interrupt
    HASH2 = 106,
    ///107 - I2C5 event interrupt
    I2C5_EVT = 107,
    ///108 - I2C5 global error interrupt
    I2C5_ERR = 108,
    ///110 - DFSDM1 filter0 Interrupt
    DFSDM1_FLT0 = 110,
    ///111 - DFSDM1 filter1 Interrupt
    DFSDM1_FLT1 = 111,
    ///112 - DFSDM1 filter2 Interrupt
    DFSDM1_FLT2 = 112,
    ///113 - DFSDM1 filter3 Interrupt
    DFSDM1_FLT3 = 113,
    ///114 - SAI3 global interrupt
    SAI3 = 114,
    ///115 - DFSDM1 filter4 Interrupt
    DFSDM1_FLT4 = 115,
    ///116 - TIM15 global interrupt
    TIM15 = 116,
    ///117 - TIM16 global interrupt
    TIM16 = 117,
    ///118 - TIM17 global interrupt
    TIM17 = 118,
    ///119 - TIM12 gloabl interrupt
    TIM12 = 119,
    ///120 - MDIOS global interrupt
    MDIOS = 120,
    ///121 - EXTI line 14 interrupt
    EXTI14 = 121,
    ///122 - MDMA global interrupt
    MDMA = 122,
    ///123 - DSI Host controller global interrupt
    DSI = 123,
    ///124 - SDMMC2 global interrupt
    SDMMC2 = 124,
    ///125 - HSEM semaphore interrupt 2
    HSEM_IT2 = 125,
    ///126 - DFSDM1 filter5 Interrupt
    DFSDM1_FLT5 = 126,
    ///127 - EXTI line 15 interrupt
    EXTI15 = 127,
    ///130 - TIM13 global interrupt
    TIM13 = 130,
    ///131 - TIM14 global interrupt
    TIM14 = 131,
    ///132 - DAC1 and DAC2 underrun error interrupts
    DAC = 132,
    ///133 - RNG1 interrupt
    RNG1 = 133,
    ///134 - RNG2 interrupt
    RNG2 = 134,
    ///135 - I2C6 event interrupt
    I2C6_EVT = 135,
    ///136 - I2C6 global error interrupt
    I2C6_ERR = 136,
    ///137 - SDMMC3 global interrupt
    SDMMC3 = 137,
    ///138 - LPTIMER2 global interrupt
    LPTIM2 = 138,
    ///139 - LPTIMER3 global interrupt
    LPTIM3 = 139,
    ///140 - LPTIMER4 global interrupt
    LPTIM4 = 140,
    ///141 - LPTIMER5 global interrupt
    LPTIM5 = 141,
    ///142 - ETH1 LPI interrupt
    ETH1_LPI = 142,
    ///145 - RCC MPU wakeup interrupt
    RCC_WAKEUP = 145,
    ///146 - SAI4 global interrupt
    SAI4 = 146,
    ///147 - Digital temperature sensor interrupt
    DTS = 147,
    ///150 - IWDG1 early wake
    IWDG1_IT = 150,
    ///151 - IWDG2 early wake
    IWDG2_IT = 151,
    ///197 - TAMP tamper secure interrupt
    TAMP_S = 197,
    ///198 - RTC wakeup timer and alarms (A and B) secure interrupt
    RTC_WKUP_ALARM_S = 198,
    ///199 - RTC timestamp secure interrupt
    RTC_TS_S = 199,
    ///213 - DDR performance monitor interrupt
    DDRPERFM = 213,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///ADC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ADC)
pub type ADC = crate::Periph<adc::RegisterBlock, 0x4800_3000>;
impl core::fmt::Debug for ADC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC").finish()
    }
}
///ADC
pub mod adc;
///ADC2
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ADC2)
pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4800_3100>;
impl core::fmt::Debug for ADC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC2").finish()
    }
}
///ADC2
pub mod adc2;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ADC_common)
pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4800_3300>;
impl core::fmt::Debug for ADC_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC_COMMON").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc_common;
///AXIMC_Mx
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#AXIMC_Mx)
pub type AXIMC_MX = crate::Periph<aximc_mx::RegisterBlock, 0x5704_2024>;
impl core::fmt::Debug for AXIMC_MX {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AXIMC_MX").finish()
    }
}
///AXIMC_Mx
pub mod aximc_mx;
///BSEC2
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#BSEC)
pub type BSEC = crate::Periph<bsec::RegisterBlock, 0x5c00_5000>;
impl core::fmt::Debug for BSEC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("BSEC").finish()
    }
}
///BSEC2
pub mod bsec;
///CCU
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#CCU)
pub type CCU = crate::Periph<ccu::RegisterBlock, 0x4401_0000>;
impl core::fmt::Debug for CCU {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CCU").finish()
    }
}
///CCU
pub mod ccu;
///CRC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#CRC1)
pub type CRC1 = crate::Periph<crc1::RegisterBlock, 0x5800_9000>;
impl core::fmt::Debug for CRC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC1").finish()
    }
}
///CRC1
pub mod crc1;
///CRC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#CRC1)
pub type CRC2 = crate::Periph<crc1::RegisterBlock, 0x4c00_4000>;
impl core::fmt::Debug for CRC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC2").finish()
    }
}
///CRC1
pub use self::crc1 as crc2;
///CRYP1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#CRYP1)
pub type CRYP1 = crate::Periph<cryp1::RegisterBlock, 0x5400_1000>;
impl core::fmt::Debug for CRYP1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRYP1").finish()
    }
}
///CRYP1
pub mod cryp1;
///CRYP1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#CRYP1)
pub type CRYP2 = crate::Periph<cryp1::RegisterBlock, 0x4c00_5000>;
impl core::fmt::Debug for CRYP2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRYP2").finish()
    }
}
///CRYP1
pub use self::cryp1 as cryp2;
///DAC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DAC1)
pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x4001_7000>;
impl core::fmt::Debug for DAC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC1").finish()
    }
}
///DAC1
pub mod dac1;
///DCMI
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DCMI)
pub type DCMI = crate::Periph<dcmi::RegisterBlock, 0x4c00_6000>;
impl core::fmt::Debug for DCMI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DCMI").finish()
    }
}
///DCMI
pub mod dcmi;
///DDRCTRL
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRCTRL)
pub type DDRCTRL = crate::Periph<ddrctrl::RegisterBlock, 0x5a00_3000>;
impl core::fmt::Debug for DDRCTRL {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DDRCTRL").finish()
    }
}
///DDRCTRL
pub mod ddrctrl;
///DDRPERFM
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRPERFM)
pub type DDRPERFM = crate::Periph<ddrperfm::RegisterBlock, 0x5a00_7000>;
impl core::fmt::Debug for DDRPERFM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DDRPERFM").finish()
    }
}
///DDRPERFM
pub mod ddrperfm;
///DDRPHYC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DDRPHYC)
pub type DDRPHYC = crate::Periph<ddrphyc::RegisterBlock, 0x5a00_4000>;
impl core::fmt::Debug for DDRPHYC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DDRPHYC").finish()
    }
}
///DDRPHYC
pub mod ddrphyc;
///DFSDM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DFSDM1)
pub type DFSDM1 = crate::Periph<dfsdm1::RegisterBlock, 0x4400_d000>;
impl core::fmt::Debug for DFSDM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DFSDM1").finish()
    }
}
///DFSDM1
pub mod dfsdm1;
///DLYBQS
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DLYBQS)
pub type DLYBQS = crate::Periph<dlybqs::RegisterBlock, 0x5800_4000>;
impl core::fmt::Debug for DLYBQS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DLYBQS").finish()
    }
}
///DLYBQS
pub mod dlybqs;
///DLYBSD1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DLYBSD1)
pub type DLYBSD1 = crate::Periph<dlybsd1::RegisterBlock, 0x5800_6000>;
impl core::fmt::Debug for DLYBSD1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DLYBSD1").finish()
    }
}
///DLYBSD1
pub mod dlybsd1;
///DLYBSD1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DLYBSD1)
pub type DLYBSD2 = crate::Periph<dlybsd1::RegisterBlock, 0x5800_8000>;
impl core::fmt::Debug for DLYBSD2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DLYBSD2").finish()
    }
}
///DLYBSD1
pub use self::dlybsd1 as dlybsd2;
///DLYBSD1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DLYBSD1)
pub type DLYBSD3 = crate::Periph<dlybsd1::RegisterBlock, 0x4800_5000>;
impl core::fmt::Debug for DLYBSD3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DLYBSD3").finish()
    }
}
///DLYBSD1
pub use self::dlybsd1 as dlybsd3;
///DMA1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DMA1)
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA1").finish()
    }
}
///DMA1
pub mod dma1;
///DMA1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DMA1)
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4800_1000>;
impl core::fmt::Debug for DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA2").finish()
    }
}
///DMA1
pub use self::dma1 as dma2;
///DMAMUX1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DMAMUX1)
pub type DMAMUX1 = crate::Periph<dmamux1::RegisterBlock, 0x4800_2000>;
impl core::fmt::Debug for DMAMUX1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMAMUX1").finish()
    }
}
///DMAMUX1
pub mod dmamux1;
///DSIHOST1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DSI)
pub type DSI = crate::Periph<dsi::RegisterBlock, 0x5a00_0000>;
impl core::fmt::Debug for DSI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DSI").finish()
    }
}
///DSIHOST1
pub mod dsi;
///DTS register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#DTS)
pub type DTS = crate::Periph<dts::RegisterBlock, 0x5002_8000>;
impl core::fmt::Debug for DTS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DTS").finish()
    }
}
///DTS register block
pub mod dts;
///ETH_MAC_MMC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ETH_MAC_MMC)
pub type ETH_MAC_MMC = crate::Periph<eth_mac_mmc::RegisterBlock, 0x5800_a000>;
impl core::fmt::Debug for ETH_MAC_MMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ETH_MAC_MMC").finish()
    }
}
///ETH_MAC_MMC
pub mod eth_mac_mmc;
///ETH_MTL
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ETH_MTL)
pub type ETH_MTL = crate::Periph<eth_mtl::RegisterBlock, 0x5800_ac00>;
impl core::fmt::Debug for ETH_MTL {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ETH_MTL").finish()
    }
}
///ETH_MTL
pub mod eth_mtl;
///ETH_DMA
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ETH_DMA)
pub type ETH_DMA = crate::Periph<eth_dma::RegisterBlock, 0x5800_b000>;
impl core::fmt::Debug for ETH_DMA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ETH_DMA").finish()
    }
}
///ETH_DMA
pub mod eth_dma;
///ETZPC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#ETZPC)
pub type ETZPC = crate::Periph<etzpc::RegisterBlock, 0x5c00_7000>;
impl core::fmt::Debug for ETZPC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ETZPC").finish()
    }
}
///ETZPC
pub mod etzpc;
///EXTI
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#EXTI)
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x5000_d000>;
impl core::fmt::Debug for EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTI").finish()
    }
}
///EXTI
pub mod exti;
///FDCAN1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#FDCAN1)
pub type FDCAN1 = crate::Periph<fdcan1::RegisterBlock, 0x4400_e000>;
impl core::fmt::Debug for FDCAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN1").finish()
    }
}
///FDCAN1
pub mod fdcan1;
///FDCAN1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#FDCAN1)
pub type FDCAN2 = crate::Periph<fdcan1::RegisterBlock, 0x4400_f000>;
impl core::fmt::Debug for FDCAN2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN2").finish()
    }
}
///FDCAN1
pub use self::fdcan1 as fdcan2;
///FMC register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#FMC)
pub type FMC = crate::Periph<fmc::RegisterBlock, 0x5800_2000>;
impl core::fmt::Debug for FMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FMC").finish()
    }
}
///FMC register block
pub mod fmc;
///GICC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GICC)
pub type GICC = crate::Periph<gicc::RegisterBlock, 0xa002_2000>;
impl core::fmt::Debug for GICC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GICC").finish()
    }
}
///GICC
pub mod gicc;
///GICD
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GICD)
pub type GICD = crate::Periph<gicd::RegisterBlock, 0xa002_1000>;
impl core::fmt::Debug for GICD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GICD").finish()
    }
}
///GICD
pub mod gicd;
///GICH
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GICH)
pub type GICH = crate::Periph<gich::RegisterBlock, 0xa002_4000>;
impl core::fmt::Debug for GICH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GICH").finish()
    }
}
///GICH
pub mod gich;
///GICV
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GICV)
pub type GICV = crate::Periph<gicv::RegisterBlock, 0xa002_6000>;
impl core::fmt::Debug for GICV {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GICV").finish()
    }
}
///GICV
pub mod gicv;
///GPIOA
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOA)
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x5000_2000>;
impl core::fmt::Debug for GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOA").finish()
    }
}
///GPIOA
pub mod gpioa;
///GPIOB
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOB)
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x5000_3000>;
impl core::fmt::Debug for GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOB").finish()
    }
}
///GPIOB
pub mod gpiob;
///GPIOC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOC)
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x5000_4000>;
impl core::fmt::Debug for GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOC").finish()
    }
}
///GPIOC
pub mod gpioc;
///GPIOD
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOD)
pub type GPIOD = crate::Periph<gpiod::RegisterBlock, 0x5000_5000>;
impl core::fmt::Debug for GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOD").finish()
    }
}
///GPIOD
pub mod gpiod;
///GPIOE
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOE)
pub type GPIOE = crate::Periph<gpioe::RegisterBlock, 0x5000_6000>;
impl core::fmt::Debug for GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOE").finish()
    }
}
///GPIOE
pub mod gpioe;
///GPIOF
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOF)
pub type GPIOF = crate::Periph<gpiof::RegisterBlock, 0x5000_7000>;
impl core::fmt::Debug for GPIOF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOF").finish()
    }
}
///GPIOF
pub mod gpiof;
///GPIOG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOG)
pub type GPIOG = crate::Periph<gpiog::RegisterBlock, 0x5000_8000>;
impl core::fmt::Debug for GPIOG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOG").finish()
    }
}
///GPIOG
pub mod gpiog;
///GPIOH
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOH)
pub type GPIOH = crate::Periph<gpioh::RegisterBlock, 0x5000_9000>;
impl core::fmt::Debug for GPIOH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOH").finish()
    }
}
///GPIOH
pub mod gpioh;
///GPIOI
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOI)
pub type GPIOI = crate::Periph<gpioi::RegisterBlock, 0x5000_a000>;
impl core::fmt::Debug for GPIOI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOI").finish()
    }
}
///GPIOI
pub mod gpioi;
///GPIOJ
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOJ)
pub type GPIOJ = crate::Periph<gpioj::RegisterBlock, 0x5000_b000>;
impl core::fmt::Debug for GPIOJ {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOJ").finish()
    }
}
///GPIOJ
pub mod gpioj;
///GPIOK
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOK)
pub type GPIOK = crate::Periph<gpiok::RegisterBlock, 0x5000_c000>;
impl core::fmt::Debug for GPIOK {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOK").finish()
    }
}
///GPIOK
pub mod gpiok;
///GPIOZ
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#GPIOZ)
pub type GPIOZ = crate::Periph<gpioz::RegisterBlock, 0x5400_4000>;
impl core::fmt::Debug for GPIOZ {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOZ").finish()
    }
}
///GPIOZ
pub mod gpioz;
///HASH register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#HASH1)
pub type HASH1 = crate::Periph<hash1::RegisterBlock, 0x5400_2000>;
impl core::fmt::Debug for HASH1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HASH1").finish()
    }
}
///HASH register block
pub mod hash1;
///HASH register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#HASH2)
pub type HASH2 = crate::Periph<hash2::RegisterBlock, 0x4c00_2000>;
impl core::fmt::Debug for HASH2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HASH2").finish()
    }
}
///HASH register block
pub mod hash2;
///HDMI_CEC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#HDMI_CEC)
pub type HDMI_CEC = crate::Periph<hdmi_cec::RegisterBlock, 0x4001_6000>;
impl core::fmt::Debug for HDMI_CEC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HDMI_CEC").finish()
    }
}
///HDMI_CEC
pub mod hdmi_cec;
///HDP
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#HDP)
pub type HDP = crate::Periph<hdp::RegisterBlock, 0x5002_a000>;
impl core::fmt::Debug for HDP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HDP").finish()
    }
}
///HDP
pub mod hdp;
///HSEM
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#HSEM)
pub type HSEM = crate::Periph<hsem::RegisterBlock, 0x4c00_0000>;
impl core::fmt::Debug for HSEM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HSEM").finish()
    }
}
///HSEM
pub mod hsem;
///I2C1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#I2C1)
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
///I2C1
pub mod i2c1;
///I2C1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#I2C1)
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
///I2C1
pub use self::i2c1 as i2c2;
///I2C1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#I2C1)
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
///I2C1
pub use self::i2c1 as i2c3;
///I2C1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#I2C1)
pub type I2C4 = crate::Periph<i2c1::RegisterBlock, 0x5c00_2000>;
impl core::fmt::Debug for I2C4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C4").finish()
    }
}
///I2C1
pub use self::i2c1 as i2c4;
///I2C1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#I2C1)
pub type I2C5 = crate::Periph<i2c1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for I2C5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C5").finish()
    }
}
///I2C1
pub use self::i2c1 as i2c5;
///I2C1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#I2C1)
pub type I2C6 = crate::Periph<i2c1::RegisterBlock, 0x5c00_9000>;
impl core::fmt::Debug for I2C6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C6").finish()
    }
}
///I2C1
pub use self::i2c1 as i2c6;
///IPCC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#IPCC)
pub type IPCC = crate::Periph<ipcc::RegisterBlock, 0x4c00_1000>;
impl core::fmt::Debug for IPCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IPCC").finish()
    }
}
///IPCC
pub mod ipcc;
///IWDG1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#IWDG1)
pub type IWDG1 = crate::Periph<iwdg1::RegisterBlock, 0x5c00_3000>;
impl core::fmt::Debug for IWDG1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG1").finish()
    }
}
///IWDG1
pub mod iwdg1;
///IWDG1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#IWDG1)
pub type IWDG2 = crate::Periph<iwdg1::RegisterBlock, 0x5a00_2000>;
impl core::fmt::Debug for IWDG2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG2").finish()
    }
}
///IWDG1
pub use self::iwdg1 as iwdg2;
///LPTIM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#LPTIM1)
pub type LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x4000_9000>;
impl core::fmt::Debug for LPTIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM1").finish()
    }
}
///LPTIM1
pub mod lptim1;
///LPTIM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#LPTIM1)
pub type LPTIM2 = crate::Periph<lptim1::RegisterBlock, 0x5002_1000>;
impl core::fmt::Debug for LPTIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM2").finish()
    }
}
///LPTIM1
pub use self::lptim1 as lptim2;
///LPTIM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#LPTIM1)
pub type LPTIM3 = crate::Periph<lptim1::RegisterBlock, 0x5002_2000>;
impl core::fmt::Debug for LPTIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM3").finish()
    }
}
///LPTIM1
pub use self::lptim1 as lptim3;
///LPTIM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#LPTIM1)
pub type LPTIM4 = crate::Periph<lptim1::RegisterBlock, 0x5002_3000>;
impl core::fmt::Debug for LPTIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM4").finish()
    }
}
///LPTIM1
pub use self::lptim1 as lptim4;
///LPTIM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#LPTIM1)
pub type LPTIM5 = crate::Periph<lptim1::RegisterBlock, 0x5002_4000>;
impl core::fmt::Debug for LPTIM5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM5").finish()
    }
}
///LPTIM1
pub use self::lptim1 as lptim5;
///LTDC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#LTDC)
pub type LTDC = crate::Periph<ltdc::RegisterBlock, 0x5a00_1000>;
impl core::fmt::Debug for LTDC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LTDC").finish()
    }
}
///LTDC
pub mod ltdc;
///MDIOS
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#MDIOS)
pub type MDIOS = crate::Periph<mdios::RegisterBlock, 0x4001_c000>;
impl core::fmt::Debug for MDIOS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MDIOS").finish()
    }
}
///MDIOS
pub mod mdios;
///MDMA1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#MDMA)
pub type MDMA = crate::Periph<mdma::RegisterBlock, 0x5800_0000>;
impl core::fmt::Debug for MDMA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MDMA").finish()
    }
}
///MDMA1
pub mod mdma;
///OTG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#OTG)
pub type OTG = crate::Periph<otg::RegisterBlock, 0x4900_0000>;
impl core::fmt::Debug for OTG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OTG").finish()
    }
}
///OTG
pub mod otg;
///PWR
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#PWR)
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x5000_1000>;
impl core::fmt::Debug for PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWR").finish()
    }
}
///PWR
pub mod pwr;
///QUADSPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#QUADSPI)
pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0x5800_3000>;
impl core::fmt::Debug for QUADSPI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QUADSPI").finish()
    }
}
///QUADSPI1
pub mod quadspi;
///RCC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#RCC)
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RCC").finish()
    }
}
///RCC
pub mod rcc;
///RNG1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#RNG1)
pub type RNG1 = crate::Periph<rng1::RegisterBlock, 0x5400_3000>;
impl core::fmt::Debug for RNG1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG1").finish()
    }
}
///RNG1
pub mod rng1;
///RNG1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#RNG1)
pub type RNG2 = crate::Periph<rng1::RegisterBlock, 0x4c00_3000>;
impl core::fmt::Debug for RNG2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG2").finish()
    }
}
///RNG1
pub use self::rng1 as rng2;
///RTC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#RTC)
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x5c00_4000>;
impl core::fmt::Debug for RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC").finish()
    }
}
///RTC
pub mod rtc;
///SAI1 register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SAI1)
pub type SAI1 = crate::Periph<sai1::RegisterBlock, 0x4400_a000>;
impl core::fmt::Debug for SAI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI1").finish()
    }
}
///SAI1 register block
pub mod sai1;
///SAI1 register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SAI1)
pub type SAI2 = crate::Periph<sai1::RegisterBlock, 0x4400_b000>;
impl core::fmt::Debug for SAI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI2").finish()
    }
}
///SAI1 register block
pub use self::sai1 as sai2;
///SAI1 register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SAI1)
pub type SAI3 = crate::Periph<sai1::RegisterBlock, 0x4400_c000>;
impl core::fmt::Debug for SAI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI3").finish()
    }
}
///SAI1 register block
pub use self::sai1 as sai3;
///SAI1 register block
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SAI1)
pub type SAI4 = crate::Periph<sai1::RegisterBlock, 0x5002_7000>;
impl core::fmt::Debug for SAI4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI4").finish()
    }
}
///SAI1 register block
pub use self::sai1 as sai4;
///SDMMC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SDMMC1)
pub type SDMMC1 = crate::Periph<sdmmc1::RegisterBlock, 0x5800_5000>;
impl core::fmt::Debug for SDMMC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDMMC1").finish()
    }
}
///SDMMC1
pub mod sdmmc1;
///SDMMC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SDMMC1)
pub type SDMMC2 = crate::Periph<sdmmc1::RegisterBlock, 0x5800_7000>;
impl core::fmt::Debug for SDMMC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDMMC2").finish()
    }
}
///SDMMC1
pub use self::sdmmc1 as sdmmc2;
///SDMMC1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SDMMC1)
pub type SDMMC3 = crate::Periph<sdmmc1::RegisterBlock, 0x4800_4000>;
impl core::fmt::Debug for SDMMC3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDMMC3").finish()
    }
}
///SDMMC1
pub use self::sdmmc1 as sdmmc3;
///SPDIFRX
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPDIFRX)
pub type SPDIFRX = crate::Periph<spdifrx::RegisterBlock, 0x4000_d000>;
impl core::fmt::Debug for SPDIFRX {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPDIFRX").finish()
    }
}
///SPDIFRX
pub mod spdifrx;
///SPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPI1)
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4400_4000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
///SPI1
pub mod spi1;
///SPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPI1)
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_b000>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
///SPI1
pub use self::spi1 as spi2;
///SPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPI1)
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_c000>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
///SPI1
pub use self::spi1 as spi3;
///SPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPI1)
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4400_5000>;
impl core::fmt::Debug for SPI4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI4").finish()
    }
}
///SPI1
pub use self::spi1 as spi4;
///SPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPI1)
pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4400_9000>;
impl core::fmt::Debug for SPI5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI5").finish()
    }
}
///SPI1
pub use self::spi1 as spi5;
///SPI1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SPI1)
pub type SPI6 = crate::Periph<spi1::RegisterBlock, 0x5c00_1000>;
impl core::fmt::Debug for SPI6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI6").finish()
    }
}
///SPI1
pub use self::spi1 as spi6;
///STGENC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#STGENC)
pub type STGENC = crate::Periph<stgenc::RegisterBlock, 0x5c00_8000>;
impl core::fmt::Debug for STGENC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("STGENC").finish()
    }
}
///STGENC
pub mod stgenc;
///STGENR
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#STGENR)
pub type STGENR = crate::Periph<stgenr::RegisterBlock, 0x5a00_5000>;
impl core::fmt::Debug for STGENR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("STGENR").finish()
    }
}
///STGENR
pub mod stgenr;
///SYSCFG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#SYSCFG)
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x5002_0000>;
impl core::fmt::Debug for SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCFG").finish()
    }
}
///SYSCFG
pub mod syscfg;
///TAMP
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TAMP)
pub type TAMP = crate::Periph<tamp::RegisterBlock, 0x5c00_a000>;
impl core::fmt::Debug for TAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TAMP").finish()
    }
}
///TAMP
pub mod tamp;
///TIM1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM1)
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4400_0000>;
impl core::fmt::Debug for TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM1").finish()
    }
}
///TIM1
pub mod tim1;
///TIM2
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM2)
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM2").finish()
    }
}
///TIM2
pub mod tim2;
///TIM3
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM3)
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM3").finish()
    }
}
///TIM3
pub mod tim3;
///TIM4
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM4)
pub type TIM4 = crate::Periph<tim4::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for TIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM4").finish()
    }
}
///TIM4
pub mod tim4;
///TIM5
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM5)
pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for TIM5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM5").finish()
    }
}
///TIM5
pub mod tim5;
///TIM6
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM6)
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM6").finish()
    }
}
///TIM6
pub mod tim6;
///TIM7
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM7)
pub type TIM7 = crate::Periph<tim7::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM7").finish()
    }
}
///TIM7
pub mod tim7;
///TIM8
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM8)
pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4400_1000>;
impl core::fmt::Debug for TIM8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM8").finish()
    }
}
///TIM8
pub mod tim8;
///TIM12
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM12)
pub type TIM12 = crate::Periph<tim12::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for TIM12 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM12").finish()
    }
}
///TIM12
pub mod tim12;
///TIM13
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM13)
pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for TIM13 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM13").finish()
    }
}
///TIM13
pub mod tim13;
///TIM14
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM14)
pub type TIM14 = crate::Periph<tim14::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for TIM14 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM14").finish()
    }
}
///TIM14
pub mod tim14;
///TIM15
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM15)
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4400_6000>;
impl core::fmt::Debug for TIM15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM15").finish()
    }
}
///TIM15
pub mod tim15;
///TIM16
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM16)
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4400_7000>;
impl core::fmt::Debug for TIM16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM16").finish()
    }
}
///TIM16
pub mod tim16;
///TIM16
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TIM16)
pub type TIM17 = crate::Periph<tim16::RegisterBlock, 0x4400_8000>;
impl core::fmt::Debug for TIM17 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM17").finish()
    }
}
///TIM16
pub use self::tim16 as tim17;
///TZC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#TZC)
pub type TZC = crate::Periph<tzc::RegisterBlock, 0x5c00_6000>;
impl core::fmt::Debug for TZC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TZC").finish()
    }
}
///TZC
pub mod tzc;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x5c00_0000>;
impl core::fmt::Debug for USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_e000>;
impl core::fmt::Debug for USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_f000>;
impl core::fmt::Debug for USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART4 = crate::Periph<usart1::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for USART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART4").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart4;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART5 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for USART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART5").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart5;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4400_3000>;
impl core::fmt::Debug for USART6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART6").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart6;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART7 = crate::Periph<usart1::RegisterBlock, 0x4001_8000>;
impl core::fmt::Debug for USART7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART7").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart7;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USART1)
pub type USART8 = crate::Periph<usart1::RegisterBlock, 0x4001_9000>;
impl core::fmt::Debug for USART8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART8").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart8;
///USBPHYC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#USBPHYC)
pub type USBPHYC = crate::Periph<usbphyc::RegisterBlock, 0x5a00_6000>;
impl core::fmt::Debug for USBPHYC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USBPHYC").finish()
    }
}
///USBPHYC
pub mod usbphyc;
///VREFBUF
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#VREFBUF)
pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x5002_5000>;
impl core::fmt::Debug for VREFBUF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("VREFBUF").finish()
    }
}
///VREFBUF
pub mod vrefbuf;
///WWDG1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32MP157.html#WWDG1)
pub type WWDG1 = crate::Periph<wwdg1::RegisterBlock, 0x4000_a000>;
impl core::fmt::Debug for WWDG1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WWDG1").finish()
    }
}
///WWDG1
pub mod wwdg1;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///ADC
    pub ADC: ADC,
    ///ADC2
    pub ADC2: ADC2,
    ///ADC_common
    pub ADC_COMMON: ADC_COMMON,
    ///AXIMC_Mx
    pub AXIMC_MX: AXIMC_MX,
    ///BSEC
    pub BSEC: BSEC,
    ///CCU
    pub CCU: CCU,
    ///CRC1
    pub CRC1: CRC1,
    ///CRC2
    pub CRC2: CRC2,
    ///CRYP1
    pub CRYP1: CRYP1,
    ///CRYP2
    pub CRYP2: CRYP2,
    ///DAC1
    pub DAC1: DAC1,
    ///DCMI
    pub DCMI: DCMI,
    ///DDRCTRL
    pub DDRCTRL: DDRCTRL,
    ///DDRPERFM
    pub DDRPERFM: DDRPERFM,
    ///DDRPHYC
    pub DDRPHYC: DDRPHYC,
    ///DFSDM1
    pub DFSDM1: DFSDM1,
    ///DLYBQS
    pub DLYBQS: DLYBQS,
    ///DLYBSD1
    pub DLYBSD1: DLYBSD1,
    ///DLYBSD2
    pub DLYBSD2: DLYBSD2,
    ///DLYBSD3
    pub DLYBSD3: DLYBSD3,
    ///DMA1
    pub DMA1: DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///DMAMUX1
    pub DMAMUX1: DMAMUX1,
    ///DSI
    pub DSI: DSI,
    ///DTS
    pub DTS: DTS,
    ///ETH_MAC_MMC
    pub ETH_MAC_MMC: ETH_MAC_MMC,
    ///ETH_MTL
    pub ETH_MTL: ETH_MTL,
    ///ETH_DMA
    pub ETH_DMA: ETH_DMA,
    ///ETZPC
    pub ETZPC: ETZPC,
    ///EXTI
    pub EXTI: EXTI,
    ///FDCAN1
    pub FDCAN1: FDCAN1,
    ///FDCAN2
    pub FDCAN2: FDCAN2,
    ///FMC
    pub FMC: FMC,
    ///GICC
    pub GICC: GICC,
    ///GICD
    pub GICD: GICD,
    ///GICH
    pub GICH: GICH,
    ///GICV
    pub GICV: GICV,
    ///GPIOA
    pub GPIOA: GPIOA,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOF
    pub GPIOF: GPIOF,
    ///GPIOG
    pub GPIOG: GPIOG,
    ///GPIOH
    pub GPIOH: GPIOH,
    ///GPIOI
    pub GPIOI: GPIOI,
    ///GPIOJ
    pub GPIOJ: GPIOJ,
    ///GPIOK
    pub GPIOK: GPIOK,
    ///GPIOZ
    pub GPIOZ: GPIOZ,
    ///HASH1
    pub HASH1: HASH1,
    ///HASH2
    pub HASH2: HASH2,
    ///HDMI_CEC
    pub HDMI_CEC: HDMI_CEC,
    ///HDP
    pub HDP: HDP,
    ///HSEM
    pub HSEM: HSEM,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C2
    pub I2C2: I2C2,
    ///I2C3
    pub I2C3: I2C3,
    ///I2C4
    pub I2C4: I2C4,
    ///I2C5
    pub I2C5: I2C5,
    ///I2C6
    pub I2C6: I2C6,
    ///IPCC
    pub IPCC: IPCC,
    ///IWDG1
    pub IWDG1: IWDG1,
    ///IWDG2
    pub IWDG2: IWDG2,
    ///LPTIM1
    pub LPTIM1: LPTIM1,
    ///LPTIM2
    pub LPTIM2: LPTIM2,
    ///LPTIM3
    pub LPTIM3: LPTIM3,
    ///LPTIM4
    pub LPTIM4: LPTIM4,
    ///LPTIM5
    pub LPTIM5: LPTIM5,
    ///LTDC
    pub LTDC: LTDC,
    ///MDIOS
    pub MDIOS: MDIOS,
    ///MDMA
    pub MDMA: MDMA,
    ///OTG
    pub OTG: OTG,
    ///PWR
    pub PWR: PWR,
    ///QUADSPI
    pub QUADSPI: QUADSPI,
    ///RCC
    pub RCC: RCC,
    ///RNG1
    pub RNG1: RNG1,
    ///RNG2
    pub RNG2: RNG2,
    ///RTC
    pub RTC: RTC,
    ///SAI1
    pub SAI1: SAI1,
    ///SAI2
    pub SAI2: SAI2,
    ///SAI3
    pub SAI3: SAI3,
    ///SAI4
    pub SAI4: SAI4,
    ///SDMMC1
    pub SDMMC1: SDMMC1,
    ///SDMMC2
    pub SDMMC2: SDMMC2,
    ///SDMMC3
    pub SDMMC3: SDMMC3,
    ///SPDIFRX
    pub SPDIFRX: SPDIFRX,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI2
    pub SPI2: SPI2,
    ///SPI3
    pub SPI3: SPI3,
    ///SPI4
    pub SPI4: SPI4,
    ///SPI5
    pub SPI5: SPI5,
    ///SPI6
    pub SPI6: SPI6,
    ///STGENC
    pub STGENC: STGENC,
    ///STGENR
    pub STGENR: STGENR,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///TAMP
    pub TAMP: TAMP,
    ///TIM1
    pub TIM1: TIM1,
    ///TIM2
    pub TIM2: TIM2,
    ///TIM3
    pub TIM3: TIM3,
    ///TIM4
    pub TIM4: TIM4,
    ///TIM5
    pub TIM5: TIM5,
    ///TIM6
    pub TIM6: TIM6,
    ///TIM7
    pub TIM7: TIM7,
    ///TIM8
    pub TIM8: TIM8,
    ///TIM12
    pub TIM12: TIM12,
    ///TIM13
    pub TIM13: TIM13,
    ///TIM14
    pub TIM14: TIM14,
    ///TIM15
    pub TIM15: TIM15,
    ///TIM16
    pub TIM16: TIM16,
    ///TIM17
    pub TIM17: TIM17,
    ///TZC
    pub TZC: TZC,
    ///USART1
    pub USART1: USART1,
    ///USART2
    pub USART2: USART2,
    ///USART3
    pub USART3: USART3,
    ///USART4
    pub USART4: USART4,
    ///USART5
    pub USART5: USART5,
    ///USART6
    pub USART6: USART6,
    ///USART7
    pub USART7: USART7,
    ///USART8
    pub USART8: USART8,
    ///USBPHYC
    pub USBPHYC: USBPHYC,
    ///VREFBUF
    pub VREFBUF: VREFBUF,
    ///WWDG1
    pub WWDG1: WWDG1,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            ADC: ADC::steal(),
            ADC2: ADC2::steal(),
            ADC_COMMON: ADC_COMMON::steal(),
            AXIMC_MX: AXIMC_MX::steal(),
            BSEC: BSEC::steal(),
            CCU: CCU::steal(),
            CRC1: CRC1::steal(),
            CRC2: CRC2::steal(),
            CRYP1: CRYP1::steal(),
            CRYP2: CRYP2::steal(),
            DAC1: DAC1::steal(),
            DCMI: DCMI::steal(),
            DDRCTRL: DDRCTRL::steal(),
            DDRPERFM: DDRPERFM::steal(),
            DDRPHYC: DDRPHYC::steal(),
            DFSDM1: DFSDM1::steal(),
            DLYBQS: DLYBQS::steal(),
            DLYBSD1: DLYBSD1::steal(),
            DLYBSD2: DLYBSD2::steal(),
            DLYBSD3: DLYBSD3::steal(),
            DMA1: DMA1::steal(),
            DMA2: DMA2::steal(),
            DMAMUX1: DMAMUX1::steal(),
            DSI: DSI::steal(),
            DTS: DTS::steal(),
            ETH_MAC_MMC: ETH_MAC_MMC::steal(),
            ETH_MTL: ETH_MTL::steal(),
            ETH_DMA: ETH_DMA::steal(),
            ETZPC: ETZPC::steal(),
            EXTI: EXTI::steal(),
            FDCAN1: FDCAN1::steal(),
            FDCAN2: FDCAN2::steal(),
            FMC: FMC::steal(),
            GICC: GICC::steal(),
            GICD: GICD::steal(),
            GICH: GICH::steal(),
            GICV: GICV::steal(),
            GPIOA: GPIOA::steal(),
            GPIOB: GPIOB::steal(),
            GPIOC: GPIOC::steal(),
            GPIOD: GPIOD::steal(),
            GPIOE: GPIOE::steal(),
            GPIOF: GPIOF::steal(),
            GPIOG: GPIOG::steal(),
            GPIOH: GPIOH::steal(),
            GPIOI: GPIOI::steal(),
            GPIOJ: GPIOJ::steal(),
            GPIOK: GPIOK::steal(),
            GPIOZ: GPIOZ::steal(),
            HASH1: HASH1::steal(),
            HASH2: HASH2::steal(),
            HDMI_CEC: HDMI_CEC::steal(),
            HDP: HDP::steal(),
            HSEM: HSEM::steal(),
            I2C1: I2C1::steal(),
            I2C2: I2C2::steal(),
            I2C3: I2C3::steal(),
            I2C4: I2C4::steal(),
            I2C5: I2C5::steal(),
            I2C6: I2C6::steal(),
            IPCC: IPCC::steal(),
            IWDG1: IWDG1::steal(),
            IWDG2: IWDG2::steal(),
            LPTIM1: LPTIM1::steal(),
            LPTIM2: LPTIM2::steal(),
            LPTIM3: LPTIM3::steal(),
            LPTIM4: LPTIM4::steal(),
            LPTIM5: LPTIM5::steal(),
            LTDC: LTDC::steal(),
            MDIOS: MDIOS::steal(),
            MDMA: MDMA::steal(),
            OTG: OTG::steal(),
            PWR: PWR::steal(),
            QUADSPI: QUADSPI::steal(),
            RCC: RCC::steal(),
            RNG1: RNG1::steal(),
            RNG2: RNG2::steal(),
            RTC: RTC::steal(),
            SAI1: SAI1::steal(),
            SAI2: SAI2::steal(),
            SAI3: SAI3::steal(),
            SAI4: SAI4::steal(),
            SDMMC1: SDMMC1::steal(),
            SDMMC2: SDMMC2::steal(),
            SDMMC3: SDMMC3::steal(),
            SPDIFRX: SPDIFRX::steal(),
            SPI1: SPI1::steal(),
            SPI2: SPI2::steal(),
            SPI3: SPI3::steal(),
            SPI4: SPI4::steal(),
            SPI5: SPI5::steal(),
            SPI6: SPI6::steal(),
            STGENC: STGENC::steal(),
            STGENR: STGENR::steal(),
            SYSCFG: SYSCFG::steal(),
            TAMP: TAMP::steal(),
            TIM1: TIM1::steal(),
            TIM2: TIM2::steal(),
            TIM3: TIM3::steal(),
            TIM4: TIM4::steal(),
            TIM5: TIM5::steal(),
            TIM6: TIM6::steal(),
            TIM7: TIM7::steal(),
            TIM8: TIM8::steal(),
            TIM12: TIM12::steal(),
            TIM13: TIM13::steal(),
            TIM14: TIM14::steal(),
            TIM15: TIM15::steal(),
            TIM16: TIM16::steal(),
            TIM17: TIM17::steal(),
            TZC: TZC::steal(),
            USART1: USART1::steal(),
            USART2: USART2::steal(),
            USART3: USART3::steal(),
            USART4: USART4::steal(),
            USART5: USART5::steal(),
            USART6: USART6::steal(),
            USART7: USART7::steal(),
            USART8: USART8::steal(),
            USBPHYC: USBPHYC::steal(),
            VREFBUF: VREFBUF::steal(),
            WWDG1: WWDG1::steal(),
        }
    }
}