pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
fn WWDG1_IT();
fn PVD_AVD();
fn TAMP();
fn RTC_WKUP_ALARM();
fn TZC_IT();
fn RCC();
fn EXTI0();
fn EXTI1();
fn EXTI2();
fn EXTI3();
fn EXTI4();
fn DMA1_STR0();
fn DMA1_STR1();
fn DMA1_STR2();
fn DMA1_STR3();
fn DMA1_STR4();
fn DMA1_STR5();
fn DMA1_STR6();
fn ADC1();
fn FDCAN1_IT0();
fn FDCAN2_IT0();
fn FDCAN1_IT1();
fn FDCAN2_IT1();
fn EXTI5();
fn TIM1_BRK();
fn TIM1_UP();
fn TIM1_TRG_COM();
fn TIM1_CC();
fn TIM2();
fn TIM3();
fn TIM4();
fn I2C1_EVT();
fn I2C1_ERR();
fn I2C2_EVT();
fn I2C2_ERR();
fn SPI1();
fn SPI2();
fn USART1();
fn USART2();
fn USART3();
fn EXTI10();
fn RTC_TS();
fn EXTI11();
fn TIM8_BRK();
fn TIM8_UP();
fn TIM8_TRG_COM();
fn TIM8_CC();
fn DMA1_STR7();
fn FMC();
fn SDMMC1();
fn TIM5();
fn SPI3();
fn USART4();
fn USART5();
fn TIM6();
fn TIM7();
fn DMA2_STR0();
fn DMA2_STR1();
fn DMA2_STR2();
fn DMA2_STR3();
fn DMA2_STR4();
fn ETH1();
fn ETH1_WKUP();
fn EXTI6();
fn EXTI7();
fn EXTI8();
fn EXTI9();
fn DMA2_STR5();
fn DMA2_STR6();
fn DMA2_STR7();
fn USART6();
fn I2C3_EVT();
fn I2C3_ERR();
fn EXTI12();
fn EXTI13();
fn DCMI();
fn CRYP1();
fn HASH1();
fn USART7();
fn USART8();
fn SPI4();
fn SPI5();
fn SPI6();
fn SAI1();
fn LTDC();
fn LTDC_ER();
fn ADC2();
fn SAI2();
fn QUADSPI();
fn LPTIM1();
fn CEC();
fn I2C4_EVT();
fn I2C4_ERR();
fn SPDIFRX();
fn OTG();
fn IPCC_RX0();
fn IPCC_TX0();
fn DMAMUX1_OVR_REQ();
fn IPCC_RX1();
fn IPCC_TX1();
fn CRYP2();
fn HASH2();
fn I2C5_EVT();
fn I2C5_ERR();
fn DFSDM1_FLT0();
fn DFSDM1_FLT1();
fn DFSDM1_FLT2();
fn DFSDM1_FLT3();
fn SAI3();
fn DFSDM1_FLT4();
fn TIM15();
fn TIM16();
fn TIM17();
fn TIM12();
fn MDIOS();
fn EXTI14();
fn MDMA();
fn DSI();
fn SDMMC2();
fn HSEM_IT2();
fn DFSDM1_FLT5();
fn EXTI15();
fn TIM13();
fn TIM14();
fn DAC();
fn RNG1();
fn RNG2();
fn I2C6_EVT();
fn I2C6_ERR();
fn SDMMC3();
fn LPTIM2();
fn LPTIM3();
fn LPTIM4();
fn LPTIM5();
fn ETH1_LPI();
fn RCC_WAKEUP();
fn SAI4();
fn DTS();
fn IWDG1_IT();
fn IWDG2_IT();
fn TAMP_S();
fn RTC_WKUP_ALARM_S();
fn RTC_TS_S();
fn DDRPERFM();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 214] = [
Vector { _handler: WWDG1_IT },
Vector { _handler: PVD_AVD },
Vector { _handler: TAMP },
Vector {
_handler: RTC_WKUP_ALARM,
},
Vector { _handler: TZC_IT },
Vector { _handler: RCC },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector { _handler: EXTI2 },
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector {
_handler: DMA1_STR0,
},
Vector {
_handler: DMA1_STR1,
},
Vector {
_handler: DMA1_STR2,
},
Vector {
_handler: DMA1_STR3,
},
Vector {
_handler: DMA1_STR4,
},
Vector {
_handler: DMA1_STR5,
},
Vector {
_handler: DMA1_STR6,
},
Vector { _handler: ADC1 },
Vector {
_handler: FDCAN1_IT0,
},
Vector {
_handler: FDCAN2_IT0,
},
Vector {
_handler: FDCAN1_IT1,
},
Vector {
_handler: FDCAN2_IT1,
},
Vector { _handler: EXTI5 },
Vector { _handler: TIM1_BRK },
Vector { _handler: TIM1_UP },
Vector {
_handler: TIM1_TRG_COM,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _handler: TIM3 },
Vector { _handler: TIM4 },
Vector { _handler: I2C1_EVT },
Vector { _handler: I2C1_ERR },
Vector { _handler: I2C2_EVT },
Vector { _handler: I2C2_ERR },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: USART1 },
Vector { _handler: USART2 },
Vector { _handler: USART3 },
Vector { _handler: EXTI10 },
Vector { _handler: RTC_TS },
Vector { _handler: EXTI11 },
Vector { _handler: TIM8_BRK },
Vector { _handler: TIM8_UP },
Vector {
_handler: TIM8_TRG_COM,
},
Vector { _handler: TIM8_CC },
Vector {
_handler: DMA1_STR7,
},
Vector { _handler: FMC },
Vector { _handler: SDMMC1 },
Vector { _handler: TIM5 },
Vector { _handler: SPI3 },
Vector { _handler: USART4 },
Vector { _handler: USART5 },
Vector { _handler: TIM6 },
Vector { _handler: TIM7 },
Vector {
_handler: DMA2_STR0,
},
Vector {
_handler: DMA2_STR1,
},
Vector {
_handler: DMA2_STR2,
},
Vector {
_handler: DMA2_STR3,
},
Vector {
_handler: DMA2_STR4,
},
Vector { _handler: ETH1 },
Vector {
_handler: ETH1_WKUP,
},
Vector { _reserved: 0 },
Vector { _handler: EXTI6 },
Vector { _handler: EXTI7 },
Vector { _handler: EXTI8 },
Vector { _handler: EXTI9 },
Vector {
_handler: DMA2_STR5,
},
Vector {
_handler: DMA2_STR6,
},
Vector {
_handler: DMA2_STR7,
},
Vector { _handler: USART6 },
Vector { _handler: I2C3_EVT },
Vector { _handler: I2C3_ERR },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: EXTI12 },
Vector { _handler: EXTI13 },
Vector { _handler: DCMI },
Vector { _handler: CRYP1 },
Vector { _handler: HASH1 },
Vector { _reserved: 0 },
Vector { _handler: USART7 },
Vector { _handler: USART8 },
Vector { _handler: SPI4 },
Vector { _handler: SPI5 },
Vector { _handler: SPI6 },
Vector { _handler: SAI1 },
Vector { _handler: LTDC },
Vector { _handler: LTDC_ER },
Vector { _handler: ADC2 },
Vector { _handler: SAI2 },
Vector { _handler: QUADSPI },
Vector { _handler: LPTIM1 },
Vector { _handler: CEC },
Vector { _handler: I2C4_EVT },
Vector { _handler: I2C4_ERR },
Vector { _handler: SPDIFRX },
Vector { _handler: OTG },
Vector { _reserved: 0 },
Vector { _handler: IPCC_RX0 },
Vector { _handler: IPCC_TX0 },
Vector {
_handler: DMAMUX1_OVR_REQ,
},
Vector { _handler: IPCC_RX1 },
Vector { _handler: IPCC_TX1 },
Vector { _handler: CRYP2 },
Vector { _handler: HASH2 },
Vector { _handler: I2C5_EVT },
Vector { _handler: I2C5_ERR },
Vector { _reserved: 0 },
Vector {
_handler: DFSDM1_FLT0,
},
Vector {
_handler: DFSDM1_FLT1,
},
Vector {
_handler: DFSDM1_FLT2,
},
Vector {
_handler: DFSDM1_FLT3,
},
Vector { _handler: SAI3 },
Vector {
_handler: DFSDM1_FLT4,
},
Vector { _handler: TIM15 },
Vector { _handler: TIM16 },
Vector { _handler: TIM17 },
Vector { _handler: TIM12 },
Vector { _handler: MDIOS },
Vector { _handler: EXTI14 },
Vector { _handler: MDMA },
Vector { _handler: DSI },
Vector { _handler: SDMMC2 },
Vector { _handler: HSEM_IT2 },
Vector {
_handler: DFSDM1_FLT5,
},
Vector { _handler: EXTI15 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: TIM13 },
Vector { _handler: TIM14 },
Vector { _handler: DAC },
Vector { _handler: RNG1 },
Vector { _handler: RNG2 },
Vector { _handler: I2C6_EVT },
Vector { _handler: I2C6_ERR },
Vector { _handler: SDMMC3 },
Vector { _handler: LPTIM2 },
Vector { _handler: LPTIM3 },
Vector { _handler: LPTIM4 },
Vector { _handler: LPTIM5 },
Vector { _handler: ETH1_LPI },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector {
_handler: RCC_WAKEUP,
},
Vector { _handler: SAI4 },
Vector { _handler: DTS },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: IWDG1_IT },
Vector { _handler: IWDG2_IT },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: TAMP_S },
Vector {
_handler: RTC_WKUP_ALARM_S,
},
Vector { _handler: RTC_TS_S },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: DDRPERFM },
];
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
WWDG1_IT = 0,
PVD_AVD = 1,
TAMP = 2,
RTC_WKUP_ALARM = 3,
TZC_IT = 4,
RCC = 5,
EXTI0 = 6,
EXTI1 = 7,
EXTI2 = 8,
EXTI3 = 9,
EXTI4 = 10,
DMA1_STR0 = 11,
DMA1_STR1 = 12,
DMA1_STR2 = 13,
DMA1_STR3 = 14,
DMA1_STR4 = 15,
DMA1_STR5 = 16,
DMA1_STR6 = 17,
ADC1 = 18,
FDCAN1_IT0 = 19,
FDCAN2_IT0 = 20,
FDCAN1_IT1 = 21,
FDCAN2_IT1 = 22,
EXTI5 = 23,
TIM1_BRK = 24,
TIM1_UP = 25,
TIM1_TRG_COM = 26,
TIM1_CC = 27,
TIM2 = 28,
TIM3 = 29,
TIM4 = 30,
I2C1_EVT = 31,
I2C1_ERR = 32,
I2C2_EVT = 33,
I2C2_ERR = 34,
SPI1 = 35,
SPI2 = 36,
USART1 = 37,
USART2 = 38,
USART3 = 39,
EXTI10 = 40,
RTC_TS = 41,
EXTI11 = 42,
TIM8_BRK = 43,
TIM8_UP = 44,
TIM8_TRG_COM = 45,
TIM8_CC = 46,
DMA1_STR7 = 47,
FMC = 48,
SDMMC1 = 49,
TIM5 = 50,
SPI3 = 51,
USART4 = 52,
USART5 = 53,
TIM6 = 54,
TIM7 = 55,
DMA2_STR0 = 56,
DMA2_STR1 = 57,
DMA2_STR2 = 58,
DMA2_STR3 = 59,
DMA2_STR4 = 60,
ETH1 = 61,
ETH1_WKUP = 62,
EXTI6 = 64,
EXTI7 = 65,
EXTI8 = 66,
EXTI9 = 67,
DMA2_STR5 = 68,
DMA2_STR6 = 69,
DMA2_STR7 = 70,
USART6 = 71,
I2C3_EVT = 72,
I2C3_ERR = 73,
EXTI12 = 76,
EXTI13 = 77,
DCMI = 78,
CRYP1 = 79,
HASH1 = 80,
USART7 = 82,
USART8 = 83,
SPI4 = 84,
SPI5 = 85,
SPI6 = 86,
SAI1 = 87,
LTDC = 88,
LTDC_ER = 89,
ADC2 = 90,
SAI2 = 91,
QUADSPI = 92,
LPTIM1 = 93,
CEC = 94,
I2C4_EVT = 95,
I2C4_ERR = 96,
SPDIFRX = 97,
OTG = 98,
IPCC_RX0 = 100,
IPCC_TX0 = 101,
DMAMUX1_OVR_REQ = 102,
IPCC_RX1 = 103,
IPCC_TX1 = 104,
CRYP2 = 105,
HASH2 = 106,
I2C5_EVT = 107,
I2C5_ERR = 108,
DFSDM1_FLT0 = 110,
DFSDM1_FLT1 = 111,
DFSDM1_FLT2 = 112,
DFSDM1_FLT3 = 113,
SAI3 = 114,
DFSDM1_FLT4 = 115,
TIM15 = 116,
TIM16 = 117,
TIM17 = 118,
TIM12 = 119,
MDIOS = 120,
EXTI14 = 121,
MDMA = 122,
DSI = 123,
SDMMC2 = 124,
HSEM_IT2 = 125,
DFSDM1_FLT5 = 126,
EXTI15 = 127,
TIM13 = 130,
TIM14 = 131,
DAC = 132,
RNG1 = 133,
RNG2 = 134,
I2C6_EVT = 135,
I2C6_ERR = 136,
SDMMC3 = 137,
LPTIM2 = 138,
LPTIM3 = 139,
LPTIM4 = 140,
LPTIM5 = 141,
ETH1_LPI = 142,
RCC_WAKEUP = 145,
SAI4 = 146,
DTS = 147,
IWDG1_IT = 150,
IWDG2_IT = 151,
TAMP_S = 197,
RTC_WKUP_ALARM_S = 198,
RTC_TS_S = 199,
DDRPERFM = 213,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
pub type ADC = crate::Periph<adc::RegisterBlock, 0x4800_3000>;
impl core::fmt::Debug for ADC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC").finish()
}
}
pub mod adc;
pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4800_3100>;
impl core::fmt::Debug for ADC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC2").finish()
}
}
pub mod adc2;
pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4800_3300>;
impl core::fmt::Debug for ADC_COMMON {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC_COMMON").finish()
}
}
pub mod adc_common;
pub type AXIMC_MX = crate::Periph<aximc_mx::RegisterBlock, 0x5704_2024>;
impl core::fmt::Debug for AXIMC_MX {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AXIMC_MX").finish()
}
}
pub mod aximc_mx;
pub type BSEC = crate::Periph<bsec::RegisterBlock, 0x5c00_5000>;
impl core::fmt::Debug for BSEC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BSEC").finish()
}
}
pub mod bsec;
pub type CCU = crate::Periph<ccu::RegisterBlock, 0x4401_0000>;
impl core::fmt::Debug for CCU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU").finish()
}
}
pub mod ccu;
pub type CRC1 = crate::Periph<crc1::RegisterBlock, 0x5800_9000>;
impl core::fmt::Debug for CRC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC1").finish()
}
}
pub mod crc1;
pub type CRC2 = crate::Periph<crc1::RegisterBlock, 0x4c00_4000>;
impl core::fmt::Debug for CRC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC2").finish()
}
}
pub use self::crc1 as crc2;
pub type CRYP1 = crate::Periph<cryp1::RegisterBlock, 0x5400_1000>;
impl core::fmt::Debug for CRYP1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRYP1").finish()
}
}
pub mod cryp1;
pub type CRYP2 = crate::Periph<cryp1::RegisterBlock, 0x4c00_5000>;
impl core::fmt::Debug for CRYP2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRYP2").finish()
}
}
pub use self::cryp1 as cryp2;
pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x4001_7000>;
impl core::fmt::Debug for DAC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DAC1").finish()
}
}
pub mod dac1;
pub type DCMI = crate::Periph<dcmi::RegisterBlock, 0x4c00_6000>;
impl core::fmt::Debug for DCMI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DCMI").finish()
}
}
pub mod dcmi;
pub type DDRCTRL = crate::Periph<ddrctrl::RegisterBlock, 0x5a00_3000>;
impl core::fmt::Debug for DDRCTRL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DDRCTRL").finish()
}
}
pub mod ddrctrl;
pub type DDRPERFM = crate::Periph<ddrperfm::RegisterBlock, 0x5a00_7000>;
impl core::fmt::Debug for DDRPERFM {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DDRPERFM").finish()
}
}
pub mod ddrperfm;
pub type DDRPHYC = crate::Periph<ddrphyc::RegisterBlock, 0x5a00_4000>;
impl core::fmt::Debug for DDRPHYC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DDRPHYC").finish()
}
}
pub mod ddrphyc;
pub type DFSDM1 = crate::Periph<dfsdm1::RegisterBlock, 0x4400_d000>;
impl core::fmt::Debug for DFSDM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DFSDM1").finish()
}
}
pub mod dfsdm1;
pub type DLYBQS = crate::Periph<dlybqs::RegisterBlock, 0x5800_4000>;
impl core::fmt::Debug for DLYBQS {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DLYBQS").finish()
}
}
pub mod dlybqs;
pub type DLYBSD1 = crate::Periph<dlybsd1::RegisterBlock, 0x5800_6000>;
impl core::fmt::Debug for DLYBSD1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DLYBSD1").finish()
}
}
pub mod dlybsd1;
pub type DLYBSD2 = crate::Periph<dlybsd1::RegisterBlock, 0x5800_8000>;
impl core::fmt::Debug for DLYBSD2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DLYBSD2").finish()
}
}
pub use self::dlybsd1 as dlybsd2;
pub type DLYBSD3 = crate::Periph<dlybsd1::RegisterBlock, 0x4800_5000>;
impl core::fmt::Debug for DLYBSD3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DLYBSD3").finish()
}
}
pub use self::dlybsd1 as dlybsd3;
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for DMA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA1").finish()
}
}
pub mod dma1;
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4800_1000>;
impl core::fmt::Debug for DMA2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA2").finish()
}
}
pub use self::dma1 as dma2;
pub type DMAMUX1 = crate::Periph<dmamux1::RegisterBlock, 0x4800_2000>;
impl core::fmt::Debug for DMAMUX1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMAMUX1").finish()
}
}
pub mod dmamux1;
pub type DSI = crate::Periph<dsi::RegisterBlock, 0x5a00_0000>;
impl core::fmt::Debug for DSI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DSI").finish()
}
}
pub mod dsi;
pub type DTS = crate::Periph<dts::RegisterBlock, 0x5002_8000>;
impl core::fmt::Debug for DTS {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTS").finish()
}
}
pub mod dts;
pub type ETH_MAC_MMC = crate::Periph<eth_mac_mmc::RegisterBlock, 0x5800_a000>;
impl core::fmt::Debug for ETH_MAC_MMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETH_MAC_MMC").finish()
}
}
pub mod eth_mac_mmc;
pub type ETH_MTL = crate::Periph<eth_mtl::RegisterBlock, 0x5800_ac00>;
impl core::fmt::Debug for ETH_MTL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETH_MTL").finish()
}
}
pub mod eth_mtl;
pub type ETH_DMA = crate::Periph<eth_dma::RegisterBlock, 0x5800_b000>;
impl core::fmt::Debug for ETH_DMA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETH_DMA").finish()
}
}
pub mod eth_dma;
pub type ETZPC = crate::Periph<etzpc::RegisterBlock, 0x5c00_7000>;
impl core::fmt::Debug for ETZPC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETZPC").finish()
}
}
pub mod etzpc;
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x5000_d000>;
impl core::fmt::Debug for EXTI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXTI").finish()
}
}
pub mod exti;
pub type FDCAN1 = crate::Periph<fdcan1::RegisterBlock, 0x4400_e000>;
impl core::fmt::Debug for FDCAN1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FDCAN1").finish()
}
}
pub mod fdcan1;
pub type FDCAN2 = crate::Periph<fdcan1::RegisterBlock, 0x4400_f000>;
impl core::fmt::Debug for FDCAN2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FDCAN2").finish()
}
}
pub use self::fdcan1 as fdcan2;
pub type FMC = crate::Periph<fmc::RegisterBlock, 0x5800_2000>;
impl core::fmt::Debug for FMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FMC").finish()
}
}
pub mod fmc;
pub type GICC = crate::Periph<gicc::RegisterBlock, 0xa002_2000>;
impl core::fmt::Debug for GICC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GICC").finish()
}
}
pub mod gicc;
pub type GICD = crate::Periph<gicd::RegisterBlock, 0xa002_1000>;
impl core::fmt::Debug for GICD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GICD").finish()
}
}
pub mod gicd;
pub type GICH = crate::Periph<gich::RegisterBlock, 0xa002_4000>;
impl core::fmt::Debug for GICH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GICH").finish()
}
}
pub mod gich;
pub type GICV = crate::Periph<gicv::RegisterBlock, 0xa002_6000>;
impl core::fmt::Debug for GICV {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GICV").finish()
}
}
pub mod gicv;
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x5000_2000>;
impl core::fmt::Debug for GPIOA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOA").finish()
}
}
pub mod gpioa;
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x5000_3000>;
impl core::fmt::Debug for GPIOB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOB").finish()
}
}
pub mod gpiob;
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x5000_4000>;
impl core::fmt::Debug for GPIOC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOC").finish()
}
}
pub mod gpioc;
pub type GPIOD = crate::Periph<gpiod::RegisterBlock, 0x5000_5000>;
impl core::fmt::Debug for GPIOD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOD").finish()
}
}
pub mod gpiod;
pub type GPIOE = crate::Periph<gpioe::RegisterBlock, 0x5000_6000>;
impl core::fmt::Debug for GPIOE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOE").finish()
}
}
pub mod gpioe;
pub type GPIOF = crate::Periph<gpiof::RegisterBlock, 0x5000_7000>;
impl core::fmt::Debug for GPIOF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOF").finish()
}
}
pub mod gpiof;
pub type GPIOG = crate::Periph<gpiog::RegisterBlock, 0x5000_8000>;
impl core::fmt::Debug for GPIOG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOG").finish()
}
}
pub mod gpiog;
pub type GPIOH = crate::Periph<gpioh::RegisterBlock, 0x5000_9000>;
impl core::fmt::Debug for GPIOH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOH").finish()
}
}
pub mod gpioh;
pub type GPIOI = crate::Periph<gpioi::RegisterBlock, 0x5000_a000>;
impl core::fmt::Debug for GPIOI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOI").finish()
}
}
pub mod gpioi;
pub type GPIOJ = crate::Periph<gpioj::RegisterBlock, 0x5000_b000>;
impl core::fmt::Debug for GPIOJ {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOJ").finish()
}
}
pub mod gpioj;
pub type GPIOK = crate::Periph<gpiok::RegisterBlock, 0x5000_c000>;
impl core::fmt::Debug for GPIOK {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOK").finish()
}
}
pub mod gpiok;
pub type GPIOZ = crate::Periph<gpioz::RegisterBlock, 0x5400_4000>;
impl core::fmt::Debug for GPIOZ {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOZ").finish()
}
}
pub mod gpioz;
pub type HASH1 = crate::Periph<hash1::RegisterBlock, 0x5400_2000>;
impl core::fmt::Debug for HASH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HASH1").finish()
}
}
pub mod hash1;
pub type HASH2 = crate::Periph<hash2::RegisterBlock, 0x4c00_2000>;
impl core::fmt::Debug for HASH2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HASH2").finish()
}
}
pub mod hash2;
pub type HDMI_CEC = crate::Periph<hdmi_cec::RegisterBlock, 0x4001_6000>;
impl core::fmt::Debug for HDMI_CEC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HDMI_CEC").finish()
}
}
pub mod hdmi_cec;
pub type HDP = crate::Periph<hdp::RegisterBlock, 0x5002_a000>;
impl core::fmt::Debug for HDP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HDP").finish()
}
}
pub mod hdp;
pub type HSEM = crate::Periph<hsem::RegisterBlock, 0x4c00_0000>;
impl core::fmt::Debug for HSEM {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HSEM").finish()
}
}
pub mod hsem;
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for I2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C1").finish()
}
}
pub mod i2c1;
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for I2C2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C2").finish()
}
}
pub use self::i2c1 as i2c2;
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for I2C3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C3").finish()
}
}
pub use self::i2c1 as i2c3;
pub type I2C4 = crate::Periph<i2c1::RegisterBlock, 0x5c00_2000>;
impl core::fmt::Debug for I2C4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C4").finish()
}
}
pub use self::i2c1 as i2c4;
pub type I2C5 = crate::Periph<i2c1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for I2C5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C5").finish()
}
}
pub use self::i2c1 as i2c5;
pub type I2C6 = crate::Periph<i2c1::RegisterBlock, 0x5c00_9000>;
impl core::fmt::Debug for I2C6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C6").finish()
}
}
pub use self::i2c1 as i2c6;
pub type IPCC = crate::Periph<ipcc::RegisterBlock, 0x4c00_1000>;
impl core::fmt::Debug for IPCC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IPCC").finish()
}
}
pub mod ipcc;
pub type IWDG1 = crate::Periph<iwdg1::RegisterBlock, 0x5c00_3000>;
impl core::fmt::Debug for IWDG1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IWDG1").finish()
}
}
pub mod iwdg1;
pub type IWDG2 = crate::Periph<iwdg1::RegisterBlock, 0x5a00_2000>;
impl core::fmt::Debug for IWDG2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IWDG2").finish()
}
}
pub use self::iwdg1 as iwdg2;
pub type LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x4000_9000>;
impl core::fmt::Debug for LPTIM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPTIM1").finish()
}
}
pub mod lptim1;
pub type LPTIM2 = crate::Periph<lptim1::RegisterBlock, 0x5002_1000>;
impl core::fmt::Debug for LPTIM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPTIM2").finish()
}
}
pub use self::lptim1 as lptim2;
pub type LPTIM3 = crate::Periph<lptim1::RegisterBlock, 0x5002_2000>;
impl core::fmt::Debug for LPTIM3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPTIM3").finish()
}
}
pub use self::lptim1 as lptim3;
pub type LPTIM4 = crate::Periph<lptim1::RegisterBlock, 0x5002_3000>;
impl core::fmt::Debug for LPTIM4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPTIM4").finish()
}
}
pub use self::lptim1 as lptim4;
pub type LPTIM5 = crate::Periph<lptim1::RegisterBlock, 0x5002_4000>;
impl core::fmt::Debug for LPTIM5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPTIM5").finish()
}
}
pub use self::lptim1 as lptim5;
pub type LTDC = crate::Periph<ltdc::RegisterBlock, 0x5a00_1000>;
impl core::fmt::Debug for LTDC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LTDC").finish()
}
}
pub mod ltdc;
pub type MDIOS = crate::Periph<mdios::RegisterBlock, 0x4001_c000>;
impl core::fmt::Debug for MDIOS {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MDIOS").finish()
}
}
pub mod mdios;
pub type MDMA = crate::Periph<mdma::RegisterBlock, 0x5800_0000>;
impl core::fmt::Debug for MDMA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MDMA").finish()
}
}
pub mod mdma;
pub type OTG = crate::Periph<otg::RegisterBlock, 0x4900_0000>;
impl core::fmt::Debug for OTG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG").finish()
}
}
pub mod otg;
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x5000_1000>;
impl core::fmt::Debug for PWR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PWR").finish()
}
}
pub mod pwr;
pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0x5800_3000>;
impl core::fmt::Debug for QUADSPI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("QUADSPI").finish()
}
}
pub mod quadspi;
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for RCC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RCC").finish()
}
}
pub mod rcc;
pub type RNG1 = crate::Periph<rng1::RegisterBlock, 0x5400_3000>;
impl core::fmt::Debug for RNG1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RNG1").finish()
}
}
pub mod rng1;
pub type RNG2 = crate::Periph<rng1::RegisterBlock, 0x4c00_3000>;
impl core::fmt::Debug for RNG2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RNG2").finish()
}
}
pub use self::rng1 as rng2;
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x5c00_4000>;
impl core::fmt::Debug for RTC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC").finish()
}
}
pub mod rtc;
pub type SAI1 = crate::Periph<sai1::RegisterBlock, 0x4400_a000>;
impl core::fmt::Debug for SAI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAI1").finish()
}
}
pub mod sai1;
pub type SAI2 = crate::Periph<sai1::RegisterBlock, 0x4400_b000>;
impl core::fmt::Debug for SAI2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAI2").finish()
}
}
pub use self::sai1 as sai2;
pub type SAI3 = crate::Periph<sai1::RegisterBlock, 0x4400_c000>;
impl core::fmt::Debug for SAI3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAI3").finish()
}
}
pub use self::sai1 as sai3;
pub type SAI4 = crate::Periph<sai1::RegisterBlock, 0x5002_7000>;
impl core::fmt::Debug for SAI4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAI4").finish()
}
}
pub use self::sai1 as sai4;
pub type SDMMC1 = crate::Periph<sdmmc1::RegisterBlock, 0x5800_5000>;
impl core::fmt::Debug for SDMMC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDMMC1").finish()
}
}
pub mod sdmmc1;
pub type SDMMC2 = crate::Periph<sdmmc1::RegisterBlock, 0x5800_7000>;
impl core::fmt::Debug for SDMMC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDMMC2").finish()
}
}
pub use self::sdmmc1 as sdmmc2;
pub type SDMMC3 = crate::Periph<sdmmc1::RegisterBlock, 0x4800_4000>;
impl core::fmt::Debug for SDMMC3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDMMC3").finish()
}
}
pub use self::sdmmc1 as sdmmc3;
pub type SPDIFRX = crate::Periph<spdifrx::RegisterBlock, 0x4000_d000>;
impl core::fmt::Debug for SPDIFRX {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPDIFRX").finish()
}
}
pub mod spdifrx;
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4400_4000>;
impl core::fmt::Debug for SPI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI1").finish()
}
}
pub mod spi1;
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_b000>;
impl core::fmt::Debug for SPI2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI2").finish()
}
}
pub use self::spi1 as spi2;
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_c000>;
impl core::fmt::Debug for SPI3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI3").finish()
}
}
pub use self::spi1 as spi3;
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4400_5000>;
impl core::fmt::Debug for SPI4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI4").finish()
}
}
pub use self::spi1 as spi4;
pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4400_9000>;
impl core::fmt::Debug for SPI5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI5").finish()
}
}
pub use self::spi1 as spi5;
pub type SPI6 = crate::Periph<spi1::RegisterBlock, 0x5c00_1000>;
impl core::fmt::Debug for SPI6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI6").finish()
}
}
pub use self::spi1 as spi6;
pub type STGENC = crate::Periph<stgenc::RegisterBlock, 0x5c00_8000>;
impl core::fmt::Debug for STGENC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("STGENC").finish()
}
}
pub mod stgenc;
pub type STGENR = crate::Periph<stgenr::RegisterBlock, 0x5a00_5000>;
impl core::fmt::Debug for STGENR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("STGENR").finish()
}
}
pub mod stgenr;
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x5002_0000>;
impl core::fmt::Debug for SYSCFG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCFG").finish()
}
}
pub mod syscfg;
pub type TAMP = crate::Periph<tamp::RegisterBlock, 0x5c00_a000>;
impl core::fmt::Debug for TAMP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TAMP").finish()
}
}
pub mod tamp;
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4400_0000>;
impl core::fmt::Debug for TIM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM1").finish()
}
}
pub mod tim1;
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM2").finish()
}
}
pub mod tim2;
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM3").finish()
}
}
pub mod tim3;
pub type TIM4 = crate::Periph<tim4::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for TIM4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM4").finish()
}
}
pub mod tim4;
pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for TIM5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM5").finish()
}
}
pub mod tim5;
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for TIM6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM6").finish()
}
}
pub mod tim6;
pub type TIM7 = crate::Periph<tim7::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for TIM7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM7").finish()
}
}
pub mod tim7;
pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4400_1000>;
impl core::fmt::Debug for TIM8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM8").finish()
}
}
pub mod tim8;
pub type TIM12 = crate::Periph<tim12::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for TIM12 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM12").finish()
}
}
pub mod tim12;
pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for TIM13 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM13").finish()
}
}
pub mod tim13;
pub type TIM14 = crate::Periph<tim14::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for TIM14 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM14").finish()
}
}
pub mod tim14;
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4400_6000>;
impl core::fmt::Debug for TIM15 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM15").finish()
}
}
pub mod tim15;
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4400_7000>;
impl core::fmt::Debug for TIM16 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM16").finish()
}
}
pub mod tim16;
pub type TIM17 = crate::Periph<tim16::RegisterBlock, 0x4400_8000>;
impl core::fmt::Debug for TIM17 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM17").finish()
}
}
pub use self::tim16 as tim17;
pub type TZC = crate::Periph<tzc::RegisterBlock, 0x5c00_6000>;
impl core::fmt::Debug for TZC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TZC").finish()
}
}
pub mod tzc;
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x5c00_0000>;
impl core::fmt::Debug for USART1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART1").finish()
}
}
pub mod usart1;
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_e000>;
impl core::fmt::Debug for USART2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART2").finish()
}
}
pub use self::usart1 as usart2;
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_f000>;
impl core::fmt::Debug for USART3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART3").finish()
}
}
pub use self::usart1 as usart3;
pub type USART4 = crate::Periph<usart1::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for USART4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART4").finish()
}
}
pub use self::usart1 as usart4;
pub type USART5 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for USART5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART5").finish()
}
}
pub use self::usart1 as usart5;
pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4400_3000>;
impl core::fmt::Debug for USART6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART6").finish()
}
}
pub use self::usart1 as usart6;
pub type USART7 = crate::Periph<usart1::RegisterBlock, 0x4001_8000>;
impl core::fmt::Debug for USART7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART7").finish()
}
}
pub use self::usart1 as usart7;
pub type USART8 = crate::Periph<usart1::RegisterBlock, 0x4001_9000>;
impl core::fmt::Debug for USART8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART8").finish()
}
}
pub use self::usart1 as usart8;
pub type USBPHYC = crate::Periph<usbphyc::RegisterBlock, 0x5a00_6000>;
impl core::fmt::Debug for USBPHYC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USBPHYC").finish()
}
}
pub mod usbphyc;
pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x5002_5000>;
impl core::fmt::Debug for VREFBUF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VREFBUF").finish()
}
}
pub mod vrefbuf;
pub type WWDG1 = crate::Periph<wwdg1::RegisterBlock, 0x4000_a000>;
impl core::fmt::Debug for WWDG1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WWDG1").finish()
}
}
pub mod wwdg1;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[allow(non_snake_case)]
pub struct Peripherals {
pub ADC: ADC,
pub ADC2: ADC2,
pub ADC_COMMON: ADC_COMMON,
pub AXIMC_MX: AXIMC_MX,
pub BSEC: BSEC,
pub CCU: CCU,
pub CRC1: CRC1,
pub CRC2: CRC2,
pub CRYP1: CRYP1,
pub CRYP2: CRYP2,
pub DAC1: DAC1,
pub DCMI: DCMI,
pub DDRCTRL: DDRCTRL,
pub DDRPERFM: DDRPERFM,
pub DDRPHYC: DDRPHYC,
pub DFSDM1: DFSDM1,
pub DLYBQS: DLYBQS,
pub DLYBSD1: DLYBSD1,
pub DLYBSD2: DLYBSD2,
pub DLYBSD3: DLYBSD3,
pub DMA1: DMA1,
pub DMA2: DMA2,
pub DMAMUX1: DMAMUX1,
pub DSI: DSI,
pub DTS: DTS,
pub ETH_MAC_MMC: ETH_MAC_MMC,
pub ETH_MTL: ETH_MTL,
pub ETH_DMA: ETH_DMA,
pub ETZPC: ETZPC,
pub EXTI: EXTI,
pub FDCAN1: FDCAN1,
pub FDCAN2: FDCAN2,
pub FMC: FMC,
pub GICC: GICC,
pub GICD: GICD,
pub GICH: GICH,
pub GICV: GICV,
pub GPIOA: GPIOA,
pub GPIOB: GPIOB,
pub GPIOC: GPIOC,
pub GPIOD: GPIOD,
pub GPIOE: GPIOE,
pub GPIOF: GPIOF,
pub GPIOG: GPIOG,
pub GPIOH: GPIOH,
pub GPIOI: GPIOI,
pub GPIOJ: GPIOJ,
pub GPIOK: GPIOK,
pub GPIOZ: GPIOZ,
pub HASH1: HASH1,
pub HASH2: HASH2,
pub HDMI_CEC: HDMI_CEC,
pub HDP: HDP,
pub HSEM: HSEM,
pub I2C1: I2C1,
pub I2C2: I2C2,
pub I2C3: I2C3,
pub I2C4: I2C4,
pub I2C5: I2C5,
pub I2C6: I2C6,
pub IPCC: IPCC,
pub IWDG1: IWDG1,
pub IWDG2: IWDG2,
pub LPTIM1: LPTIM1,
pub LPTIM2: LPTIM2,
pub LPTIM3: LPTIM3,
pub LPTIM4: LPTIM4,
pub LPTIM5: LPTIM5,
pub LTDC: LTDC,
pub MDIOS: MDIOS,
pub MDMA: MDMA,
pub OTG: OTG,
pub PWR: PWR,
pub QUADSPI: QUADSPI,
pub RCC: RCC,
pub RNG1: RNG1,
pub RNG2: RNG2,
pub RTC: RTC,
pub SAI1: SAI1,
pub SAI2: SAI2,
pub SAI3: SAI3,
pub SAI4: SAI4,
pub SDMMC1: SDMMC1,
pub SDMMC2: SDMMC2,
pub SDMMC3: SDMMC3,
pub SPDIFRX: SPDIFRX,
pub SPI1: SPI1,
pub SPI2: SPI2,
pub SPI3: SPI3,
pub SPI4: SPI4,
pub SPI5: SPI5,
pub SPI6: SPI6,
pub STGENC: STGENC,
pub STGENR: STGENR,
pub SYSCFG: SYSCFG,
pub TAMP: TAMP,
pub TIM1: TIM1,
pub TIM2: TIM2,
pub TIM3: TIM3,
pub TIM4: TIM4,
pub TIM5: TIM5,
pub TIM6: TIM6,
pub TIM7: TIM7,
pub TIM8: TIM8,
pub TIM12: TIM12,
pub TIM13: TIM13,
pub TIM14: TIM14,
pub TIM15: TIM15,
pub TIM16: TIM16,
pub TIM17: TIM17,
pub TZC: TZC,
pub USART1: USART1,
pub USART2: USART2,
pub USART3: USART3,
pub USART4: USART4,
pub USART5: USART5,
pub USART6: USART6,
pub USART7: USART7,
pub USART8: USART8,
pub USBPHYC: USBPHYC,
pub VREFBUF: VREFBUF,
pub WWDG1: WWDG1,
}
impl Peripherals {
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
ADC: ADC::steal(),
ADC2: ADC2::steal(),
ADC_COMMON: ADC_COMMON::steal(),
AXIMC_MX: AXIMC_MX::steal(),
BSEC: BSEC::steal(),
CCU: CCU::steal(),
CRC1: CRC1::steal(),
CRC2: CRC2::steal(),
CRYP1: CRYP1::steal(),
CRYP2: CRYP2::steal(),
DAC1: DAC1::steal(),
DCMI: DCMI::steal(),
DDRCTRL: DDRCTRL::steal(),
DDRPERFM: DDRPERFM::steal(),
DDRPHYC: DDRPHYC::steal(),
DFSDM1: DFSDM1::steal(),
DLYBQS: DLYBQS::steal(),
DLYBSD1: DLYBSD1::steal(),
DLYBSD2: DLYBSD2::steal(),
DLYBSD3: DLYBSD3::steal(),
DMA1: DMA1::steal(),
DMA2: DMA2::steal(),
DMAMUX1: DMAMUX1::steal(),
DSI: DSI::steal(),
DTS: DTS::steal(),
ETH_MAC_MMC: ETH_MAC_MMC::steal(),
ETH_MTL: ETH_MTL::steal(),
ETH_DMA: ETH_DMA::steal(),
ETZPC: ETZPC::steal(),
EXTI: EXTI::steal(),
FDCAN1: FDCAN1::steal(),
FDCAN2: FDCAN2::steal(),
FMC: FMC::steal(),
GICC: GICC::steal(),
GICD: GICD::steal(),
GICH: GICH::steal(),
GICV: GICV::steal(),
GPIOA: GPIOA::steal(),
GPIOB: GPIOB::steal(),
GPIOC: GPIOC::steal(),
GPIOD: GPIOD::steal(),
GPIOE: GPIOE::steal(),
GPIOF: GPIOF::steal(),
GPIOG: GPIOG::steal(),
GPIOH: GPIOH::steal(),
GPIOI: GPIOI::steal(),
GPIOJ: GPIOJ::steal(),
GPIOK: GPIOK::steal(),
GPIOZ: GPIOZ::steal(),
HASH1: HASH1::steal(),
HASH2: HASH2::steal(),
HDMI_CEC: HDMI_CEC::steal(),
HDP: HDP::steal(),
HSEM: HSEM::steal(),
I2C1: I2C1::steal(),
I2C2: I2C2::steal(),
I2C3: I2C3::steal(),
I2C4: I2C4::steal(),
I2C5: I2C5::steal(),
I2C6: I2C6::steal(),
IPCC: IPCC::steal(),
IWDG1: IWDG1::steal(),
IWDG2: IWDG2::steal(),
LPTIM1: LPTIM1::steal(),
LPTIM2: LPTIM2::steal(),
LPTIM3: LPTIM3::steal(),
LPTIM4: LPTIM4::steal(),
LPTIM5: LPTIM5::steal(),
LTDC: LTDC::steal(),
MDIOS: MDIOS::steal(),
MDMA: MDMA::steal(),
OTG: OTG::steal(),
PWR: PWR::steal(),
QUADSPI: QUADSPI::steal(),
RCC: RCC::steal(),
RNG1: RNG1::steal(),
RNG2: RNG2::steal(),
RTC: RTC::steal(),
SAI1: SAI1::steal(),
SAI2: SAI2::steal(),
SAI3: SAI3::steal(),
SAI4: SAI4::steal(),
SDMMC1: SDMMC1::steal(),
SDMMC2: SDMMC2::steal(),
SDMMC3: SDMMC3::steal(),
SPDIFRX: SPDIFRX::steal(),
SPI1: SPI1::steal(),
SPI2: SPI2::steal(),
SPI3: SPI3::steal(),
SPI4: SPI4::steal(),
SPI5: SPI5::steal(),
SPI6: SPI6::steal(),
STGENC: STGENC::steal(),
STGENR: STGENR::steal(),
SYSCFG: SYSCFG::steal(),
TAMP: TAMP::steal(),
TIM1: TIM1::steal(),
TIM2: TIM2::steal(),
TIM3: TIM3::steal(),
TIM4: TIM4::steal(),
TIM5: TIM5::steal(),
TIM6: TIM6::steal(),
TIM7: TIM7::steal(),
TIM8: TIM8::steal(),
TIM12: TIM12::steal(),
TIM13: TIM13::steal(),
TIM14: TIM14::steal(),
TIM15: TIM15::steal(),
TIM16: TIM16::steal(),
TIM17: TIM17::steal(),
TZC: TZC::steal(),
USART1: USART1::steal(),
USART2: USART2::steal(),
USART3: USART3::steal(),
USART4: USART4::steal(),
USART5: USART5::steal(),
USART6: USART6::steal(),
USART7: USART7::steal(),
USART8: USART8::steal(),
USBPHYC: USBPHYC::steal(),
VREFBUF: VREFBUF::steal(),
WWDG1: WWDG1::steal(),
}
}
}