1#![allow(dead_code)]
4#![allow(non_camel_case_types)]
5
6use core::convert::TryFrom;
7use core::convert::TryInto;
8
9use crate::dma::{dma1, dma2};
10
11#[cfg(any(
12 feature = "stm32l4r9",
19 feature = "stm32l4s9"
20))]
21use crate::stm32::DMAMUX1 as DMAMUX;
22
23#[non_exhaustive]
24#[derive(Debug)]
25pub enum Error {
26 Invalid,
27}
28
29pub enum DmaInput {
31 Generator0,
32 Generator1,
33 Generator2,
34 Generator3,
35 Adc1,
36 Adc2,
37 Adc3,
38 Dac1Ch1,
39 Dac1Ch2,
40 Spi1Rx,
41 Spi1Tx,
42 Spi2Rx,
43 Spi2Tx,
44 Spi3Rx,
45 Spi3Tx,
46 I2c1Rx,
47 I2c1Tx,
48 I2c2Rx,
49 I2c2Tx,
50 I2c3Rx,
51 I2c3Tx,
52 I2c4Rx,
53 I2c4Tx,
54 Usart1Rx,
55 Usart1Tx,
56 Usart2Rx,
57 Usart2Tx,
58 Usart3Rx,
59 Usart3Tx,
60 Uart4Rx,
61 Uart4Tx,
62 Uart5Rx,
63 Uart5Tx,
64 LpUart1Rx,
65 LpUart1Tx,
66 Sai1A,
67 Sai1B,
68 Sai2A,
69 Sai2B,
70 QuadSpi,
71 OctoSpi1,
72 OctoSpi2,
73 Tim6Up,
74 Tim7Up,
75 Tim1Ch1,
76 Tim1Ch2,
77 Tim1Ch3,
78 Tim1Ch4,
79 Tim1Up,
80 Tim1Trig,
81 Tim1Com,
82 Tim8Ch1,
83 Tim8Ch2,
84 Tim8Ch3,
85 Tim8Ch4,
86 Tim8Up,
87 Tim8Trig,
88 Tim8Com,
89 Tim2Ch1,
90 Tim2Ch2,
91 Tim2Ch3,
92 Tim2Ch4,
93 Tim2Up,
94 Tim3Ch1,
95 Tim3Ch2,
96 Tim3Ch3,
97 Tim3Ch4,
98 Tim3Up,
99 Tim3Trig,
100 Tim4Ch1,
101 Tim4Ch2,
102 Tim4Ch3,
103 Tim4Ch4,
104 Tim4Up,
105 Tim5Ch1,
106 Tim5Ch2,
107 Tim5Ch3,
108 Tim5Ch4,
109 Tim5Up,
110 Tim5Trig,
111 Tim15Ch1,
112 Tim15Up,
113 Tim15Trig,
114 Tim15Com,
115 Tim16Ch1,
116 Tim16Up,
117 Tim17Ch1,
118 Tim17Up,
119 Dfsdm1Flt0,
120 Dfsdm1Flt1,
121 Dfsdm1Flt2,
122 Dfsdm1Flt3,
123 Dcmi,
124 AesIn,
125 AesOut,
126 HashIn,
127 Swpmi1Rx,
128 Swpmi1Tx,
129 SdMmc1,
130}
131
132#[cfg(any(
133 feature = "stm32l4r9",
140 feature = "stm32l4s9"
141))]
142#[derive(Clone, Copy, Debug, PartialEq)]
143#[repr(u8)]
144enum DMAREQ_ID_A {
145 NONE = 0,
146 GENERATOR0 = 1,
147 GENERATOR1 = 2,
148 GENERATOR2 = 3,
149 GENERATOR3 = 4,
150 ADC1 = 5,
151 DAC1_CH1 = 6,
152 DAC1_CH2 = 7,
153 TIM6_UP = 8,
154 TIM7_UP = 9,
155 SPI1_RX = 10,
156 SPI1_TX = 11,
157 SPI2_RX = 12,
158 SPI2_TX = 13,
159 SPI3_RX = 14,
160 SPI3_TX = 15,
161 I2C1_RX = 16,
162 I2C1_TX = 17,
163 I2C2_RX = 18,
164 I2C2_TX = 19,
165 I2C3_RX = 20,
166 I2C3_TX = 21,
167 I2C4_RX = 22,
168 I2C4_TX = 23,
169 USART1_RX = 24,
170 USART1_TX = 25,
171 USART2_RX = 26,
172 USART2_TX = 27,
173 USART3_RX = 28,
174 USART3_TX = 29,
175 UART4_RX = 30,
176 UART4_TX = 31,
177 UART5_RX = 32,
178 UART5_TX = 33,
179 LPUART1_RX = 34,
180 LPUART1_TX = 35,
181 SAI1_A = 36,
182 SAI1_B = 37,
183 SAI2_A = 38,
184 SAI2_B = 39,
185 OCTOSPI1 = 40,
186 OCTOSPI2 = 41,
187 TIM1_CH1 = 42,
188 TIM1_CH2 = 43,
189 TIM1_CH3 = 44,
190 TIM1_CH4 = 45,
191 TIM1_UP = 46,
192 TIM1_TRIG = 47,
193 TIM1_COM = 48,
194 TIM8_CH1 = 49,
195 TIM8_CH2 = 50,
196 TIM8_CH3 = 51,
197 TIM8_CH4 = 52,
198 TIM8_UP = 53,
199 TIM8_TRIG = 54,
200 TIM8_COM = 55,
201 TIM2_CH1 = 56,
202 TIM2_CH2 = 57,
203 TIM2_CH3 = 58,
204 TIM2_CH4 = 59,
205 TIM2_UP = 60,
206 TIM3_CH1 = 61,
207 TIM3_CH2 = 62,
208 TIM3_CH3 = 63,
209 TIM3_CH4 = 64,
210 TIM3_UP = 65,
211 TIM3_TRIG = 66,
212 TIM4_CH1 = 67,
213 TIM4_CH2 = 68,
214 TIM4_CH3 = 69,
215 TIM4_CH4 = 70,
216 TIM4_UP = 71,
217 TIM5_CH1 = 72,
218 TIM5_CH2 = 73,
219 TIM5_CH3 = 74,
220 TIM5_CH4 = 75,
221 TIM5_UP = 76,
222 TIM5_TRIG = 77,
223 TIM15_CH1 = 78,
224 TIM15_UP = 79,
225 TIM15_TRIG = 80,
226 TIM15_COM = 81,
227 TIM16_CH1 = 82,
228 TIM16_UP = 83,
229 TIM17_CH1 = 84,
230 TIM17_UP = 85,
231 DFSDM1_FLT0 = 86,
232 DFSDM1_FLT1 = 87,
233 DFSDM1_FLT2 = 88,
234 DFSDM1_FLT3 = 89,
235 DCMI = 90,
236 AES_IN = 91,
237 AES_OUT = 92,
238 HASH_IN = 93,
239}
240#[cfg(any(
241 feature = "stm32l4r9",
248 feature = "stm32l4s9"
249))]
250impl From<DMAREQ_ID_A> for u8 {
251 #[inline(always)]
252 fn from(variant: DMAREQ_ID_A) -> Self {
253 variant as _
254 }
255}
256#[cfg(any(
257 feature = "stm32l4r9",
264 feature = "stm32l4s9"
265))]
266impl TryFrom<DmaInput> for DMAREQ_ID_A {
267 type Error = Error;
268
269 #[inline(always)]
270 fn try_from(variant: DmaInput) -> Result<Self, Self::Error> {
271 let result = match variant {
272 DmaInput::Generator0 => Self::GENERATOR0,
273 DmaInput::Generator1 => Self::GENERATOR1,
274 DmaInput::Generator2 => Self::GENERATOR2,
275 DmaInput::Generator3 => Self::GENERATOR3,
276 DmaInput::Adc1 => Self::ADC1,
277 DmaInput::Dac1Ch1 => Self::DAC1_CH1,
278 DmaInput::Dac1Ch2 => Self::DAC1_CH2,
279 DmaInput::Tim6Up => Self::TIM6_UP,
280 DmaInput::Tim7Up => Self::TIM7_UP,
281 DmaInput::Spi1Rx => Self::SPI1_RX,
282 DmaInput::Spi1Tx => Self::SPI1_TX,
283 DmaInput::Spi2Rx => Self::SPI2_RX,
284 DmaInput::Spi2Tx => Self::SPI2_TX,
285 DmaInput::Spi3Rx => Self::SPI3_RX,
286 DmaInput::Spi3Tx => Self::SPI3_TX,
287 DmaInput::I2c1Rx => Self::I2C1_RX,
288 DmaInput::I2c1Tx => Self::I2C1_TX,
289 DmaInput::I2c2Rx => Self::I2C2_RX,
290 DmaInput::I2c2Tx => Self::I2C2_TX,
291 DmaInput::I2c3Rx => Self::I2C3_RX,
292 DmaInput::I2c3Tx => Self::I2C3_TX,
293 DmaInput::I2c4Rx => Self::I2C4_RX,
294 DmaInput::I2c4Tx => Self::I2C4_TX,
295 DmaInput::Usart1Rx => Self::USART1_RX,
296 DmaInput::Usart1Tx => Self::USART1_TX,
297 DmaInput::Usart2Rx => Self::USART2_RX,
298 DmaInput::Usart2Tx => Self::USART2_TX,
299 DmaInput::Usart3Rx => Self::USART3_RX,
300 DmaInput::Usart3Tx => Self::USART3_TX,
301 DmaInput::Uart4Rx => Self::UART4_RX,
302 DmaInput::Uart4Tx => Self::UART4_TX,
303 DmaInput::Uart5Rx => Self::UART5_RX,
304 DmaInput::Uart5Tx => Self::UART5_TX,
305 DmaInput::LpUart1Rx => Self::LPUART1_RX,
306 DmaInput::LpUart1Tx => Self::LPUART1_TX,
307 DmaInput::Sai1A => Self::SAI1_A,
308 DmaInput::Sai1B => Self::SAI1_B,
309 DmaInput::Sai2A => Self::SAI2_A,
310 DmaInput::Sai2B => Self::SAI2_B,
311 DmaInput::OctoSpi1 => Self::OCTOSPI1,
312 DmaInput::OctoSpi2 => Self::OCTOSPI2,
313 DmaInput::Tim1Ch1 => Self::TIM1_CH1,
314 DmaInput::Tim1Ch2 => Self::TIM1_CH2,
315 DmaInput::Tim1Ch3 => Self::TIM1_CH3,
316 DmaInput::Tim1Ch4 => Self::TIM1_CH4,
317 DmaInput::Tim1Up => Self::TIM1_UP,
318 DmaInput::Tim1Trig => Self::TIM1_TRIG,
319 DmaInput::Tim1Com => Self::TIM1_COM,
320 DmaInput::Tim8Ch1 => Self::TIM8_CH1,
321 DmaInput::Tim8Ch2 => Self::TIM8_CH2,
322 DmaInput::Tim8Ch3 => Self::TIM8_CH3,
323 DmaInput::Tim8Ch4 => Self::TIM8_CH4,
324 DmaInput::Tim8Up => Self::TIM8_UP,
325 DmaInput::Tim8Trig => Self::TIM8_TRIG,
326 DmaInput::Tim8Com => Self::TIM8_COM,
327 DmaInput::Tim2Ch1 => Self::TIM2_CH1,
328 DmaInput::Tim2Ch2 => Self::TIM2_CH2,
329 DmaInput::Tim2Ch3 => Self::TIM2_CH3,
330 DmaInput::Tim2Ch4 => Self::TIM2_CH4,
331 DmaInput::Tim2Up => Self::TIM2_UP,
332 DmaInput::Tim3Ch1 => Self::TIM3_CH1,
333 DmaInput::Tim3Ch2 => Self::TIM3_CH2,
334 DmaInput::Tim3Ch3 => Self::TIM3_CH3,
335 DmaInput::Tim3Ch4 => Self::TIM3_CH4,
336 DmaInput::Tim3Up => Self::TIM3_UP,
337 DmaInput::Tim3Trig => Self::TIM3_TRIG,
338 DmaInput::Tim4Ch1 => Self::TIM4_CH1,
339 DmaInput::Tim4Ch2 => Self::TIM4_CH2,
340 DmaInput::Tim4Ch3 => Self::TIM4_CH3,
341 DmaInput::Tim4Ch4 => Self::TIM4_CH4,
342 DmaInput::Tim4Up => Self::TIM4_UP,
343 DmaInput::Tim5Ch1 => Self::TIM5_CH1,
344 DmaInput::Tim5Ch2 => Self::TIM5_CH2,
345 DmaInput::Tim5Ch3 => Self::TIM5_CH3,
346 DmaInput::Tim5Ch4 => Self::TIM5_CH4,
347 DmaInput::Tim5Up => Self::TIM5_UP,
348 DmaInput::Tim5Trig => Self::TIM5_TRIG,
349 DmaInput::Tim15Ch1 => Self::TIM15_CH1,
350 DmaInput::Tim15Up => Self::TIM15_UP,
351 DmaInput::Tim15Trig => Self::TIM15_TRIG,
352 DmaInput::Tim15Com => Self::TIM15_COM,
353 DmaInput::Tim16Ch1 => Self::TIM16_CH1,
354 DmaInput::Tim16Up => Self::TIM16_UP,
355 DmaInput::Tim17Ch1 => Self::TIM17_CH1,
356 DmaInput::Tim17Up => Self::TIM17_UP,
357 DmaInput::Dfsdm1Flt0 => Self::DFSDM1_FLT0,
358 DmaInput::Dfsdm1Flt1 => Self::DFSDM1_FLT1,
359 DmaInput::Dfsdm1Flt2 => Self::DFSDM1_FLT2,
360 DmaInput::Dfsdm1Flt3 => Self::DFSDM1_FLT3,
361 DmaInput::Dcmi => Self::DCMI,
362 DmaInput::AesIn => Self::AES_IN,
363 DmaInput::AesOut => Self::AES_OUT,
364 DmaInput::HashIn => Self::HASH_IN,
365 _ => return Err(Error::Invalid),
366 };
367
368 Ok(result)
369 }
370}
371
372#[cfg(not(any(
373 feature = "stm32l4r9",
380 feature = "stm32l4s9"
381)))]
382macro_rules! cselr {
383 ($($DMAX_CY_SEL:ident: {
384 $( ($field:ident, $bits:literal, [ $( $input:path ),+ ]), )+
385 },)+) => {
386 $(
387 #[derive(Clone, Copy, Debug, PartialEq)]
388 #[repr(u8)]
389 enum $DMAX_CY_SEL {
390 $(
391 $field = $bits,
392 )+
393 }
394 impl From<$DMAX_CY_SEL> for u8 {
395 #[inline(always)]
396 fn from(variant: $DMAX_CY_SEL) -> Self {
397 variant as _
398 }
399 }
400 impl TryFrom<DmaInput> for $DMAX_CY_SEL {
401 type Error = Error;
402
403 #[inline(always)]
404 fn try_from(variant: DmaInput) -> Result<Self, Self::Error> {
405 match variant {
406 $(
407 $(
408 $input => Ok(Self::$field),
409 )+
410 )+
411 _ => Err(Error::Invalid),
412 }
413 }
414 }
415 )+
416 };
417}
418
419#[cfg(not(any(
420 feature = "stm32l4r9",
427 feature = "stm32l4s9"
428)))]
429cselr! {
430 DMA1_C1_SEL: {
431 (ADC1, 0b0000, [DmaInput::Adc1]),
432 (TIM2_CH3, 0b0100, [DmaInput::Tim2Ch3]),
433 (TIM17_CH1_TIM17_UP, 0b0101, [DmaInput::Tim17Ch1, DmaInput::Tim17Up]),
434 (TIM4_CH1, 0b0110, [DmaInput::Tim4Ch1]),
435 },
436 DMA1_C2_SEL: {
437 (ADC2, 0b0000, [DmaInput::Adc2]),
438 (SPI1_RX, 0b0001, [DmaInput::Spi1Rx]),
439 (USART3_TX, 0b0010, [DmaInput::Usart3Tx]),
440 (I2C3_TX, 0b0011, [DmaInput::I2c3Tx]),
441 (TIM2_UP, 0b0100, [DmaInput::Tim2Up]),
442 (TIM3_CH3, 0b0101, [DmaInput::Tim3Ch3]),
443 (TIM1_CH1, 0b0111, [DmaInput::Tim1Ch1]),
444 },
445 DMA1_C3_SEL: {
446 (ADC3, 0b0000, [DmaInput::Adc3]),
447 (SPI1_TX, 0b0001, [DmaInput::Spi1Tx]),
448 (USART3_RX, 0b0010, [DmaInput::Usart3Rx]),
449 (I2C3_RX, 0b0011, [DmaInput::I2c3Rx]),
450 (TIM16_CH1_TIM16_UP, 0b0100, [DmaInput::Tim16Ch1, DmaInput::Tim16Up]),
451 (TIM3_CH4_TIM3_UP, 0b0101, [DmaInput::Tim3Ch4, DmaInput::Tim3Up]),
452 (TIM6_UP_DAC_CH1, 0b0110, [DmaInput::Tim6Up, DmaInput::Dac1Ch1]),
453 (TIM1_CH2, 0b0111, [DmaInput::Tim1Ch2]),
454 },
455 DMA1_C4_SEL: {
456 (DFSDM1_FLT0, 0b0000, [DmaInput::Dfsdm1Flt0]),
457 (SPI2_RX, 0b0001, [DmaInput::Spi2Rx]),
458 (USART1_TX, 0b0010, [DmaInput::Usart1Tx]),
459 (I2C2_TX, 0b0011, [DmaInput::I2c2Tx]),
460 (TIM7_UP_DAC_CH2, 0b0101, [DmaInput::Tim7Up, DmaInput::Dac1Ch2]),
461 (TIM4_CH2, 0b0110, [DmaInput::Tim4Ch2]),
462 (TIM1_CH4_TIM1_TRIG_TIM1_COM, 0b0111, [DmaInput::Tim1Ch4, DmaInput::Tim1Trig, DmaInput::Tim1Com]),
463 },
464 DMA1_C5_SEL: {
465 (DFSDM1_FLT1, 0b0000, [DmaInput::Dfsdm1Flt1]),
466 (SPI2_TX, 0b0001, [DmaInput::Spi2Tx]),
467 (USART1_RX, 0b0010, [DmaInput::Usart1Rx]),
468 (I2C2_RX, 0b0011, [DmaInput::I2c2Rx]),
469 (TIM2_CH1, 0b0100, [DmaInput::Tim2Ch1]),
470 (QUADSPI, 0b0101, [DmaInput::QuadSpi]),
471 (TIM4_CH3, 0b0110, [DmaInput::Tim4Ch3]),
472 (TIM15_CH1_TIM15_UP_TIM15_TRIG_TIM15_COM, 0b0111, [DmaInput::Tim15Ch1, DmaInput::Tim15Up, DmaInput::Tim15Trig, DmaInput::Tim15Com]),
473 },
474 DMA1_C6_SEL: {
475 (DFSDM1_FLT2, 0b0000, [DmaInput::Dfsdm1Flt2]),
476 (SAI2_A, 0b0001, [DmaInput::Sai2A]),
477 (USART2_RX, 0b0010, [DmaInput::Usart2Rx]),
478 (I2C1_TX, 0b0011, [DmaInput::I2c1Tx]),
479 (TIM16_CH1_TIM16_UP, 0b0100, [DmaInput::Tim16Ch1, DmaInput::Tim16Up]),
480 (TIM3_CH1_TIM3_TRIG, 0b0101, [DmaInput::Tim3Ch1, DmaInput::Tim3Trig]),
481 (TIM1_UP, 0b0111, [DmaInput::Tim1Up]),
482 },
483 DMA1_C7_SEL: {
484 (DFSDM1_FLT3, 0b0000, [DmaInput::Dfsdm1Flt3]),
485 (SAI2_B, 0b0001, [DmaInput::Sai2B]),
486 (USART2_TX, 0b0010, [DmaInput::Usart2Tx]),
487 (I2C1_RX, 0b0011, [DmaInput::I2c1Rx]),
488 (TIM2_CH2_TIM2_CH4, 0b0100, [DmaInput::Tim2Ch2, DmaInput::Tim2Ch4]),
489 (TIM17_CH1_TIM17_UP, 0b0101, [DmaInput::Tim17Ch1, DmaInput::Tim17Up]),
490 (TIM4_UP, 0b0110, [DmaInput::Tim4Up]),
491 (TIM1_CH3, 0b0111, [DmaInput::Tim1Ch3]),
492 },
493 DMA2_C1_SEL: {
494 (I2C4_RX, 0b0000, [DmaInput::I2c4Rx]),
495 (SAI1_A, 0b0001, [DmaInput::Sai1A]),
496 (UART5_TX, 0b0010, [DmaInput::Uart5Tx]),
497 (SPI3_RX, 0b0011, [DmaInput::Spi3Rx]),
498 (SWPMI1_RX, 0b0100, [DmaInput::Swpmi1Rx]),
499 (TIM5_CH4_TIM5_TRIG, 0b0101, [DmaInput::Tim5Ch4, DmaInput::Tim5Trig]),
500 (AES_IN, 0b0110, [DmaInput::AesIn]),
501 (TIM8_CH3_TIM8_UP, 0b0111, [DmaInput::Tim8Ch3, DmaInput::Tim8Up]),
502 },
503 DMA2_C2_SEL: {
504 (I2C4_TX, 0b0000, [DmaInput::I2c4Tx]),
505 (SAI1_B, 0b0001, [DmaInput::Sai1B]),
506 (UART5_RX, 0b0010, [DmaInput::Uart5Rx]),
507 (SPI3_TX, 0b0011, [DmaInput::Spi3Tx]),
508 (SWPMI1_TX, 0b0100, [DmaInput::Swpmi1Tx]),
509 (TIM5_CH3_TIM5_UP, 0b0101, [DmaInput::Tim5Ch3, DmaInput::Tim5Up]),
510 (AES_OUT, 0b0110, [DmaInput::AesOut]),
511 (TIM8_CH4_TIM8_TRIG_TIM8_COM, 0b0111, [DmaInput::Tim8Ch4, DmaInput::Tim8Trig, DmaInput::Tim8Com]),
512 },
513 DMA2_C3_SEL: {
514 (ADC1, 0b0000, [DmaInput::Adc1]),
515 (SAI2_A, 0b0001, [DmaInput::Sai2A]),
516 (UART4_TX, 0b0010, [DmaInput::Uart4Tx]),
517 (SPI1_RX, 0b0100, [DmaInput::Spi1Rx]),
518 (AES_OUT, 0b0110, [DmaInput::AesOut]),
519 },
520 DMA2_C4_SEL: {
521 (ADC2, 0b0000, [DmaInput::Adc2]),
522 (SAI2_B, 0b0001, [DmaInput::Sai2B]),
523 (TIM6_UP_DAC_CH1, 0b0011, [DmaInput::Tim6Up, DmaInput::Dac1Ch1]),
524 (SPI1_TX, 0b0100, [DmaInput::Spi1Tx]),
525 (TIM5_CH2, 0b0101, [DmaInput::Tim5Ch2]),
526 (SDMMC1, 0b0111, [DmaInput::SdMmc1]),
527 },
528 DMA2_C5_SEL: {
529 (ADC3, 0b0000, [DmaInput::Adc3]),
530 (UART4_RX, 0b0010, [DmaInput::Uart4Rx]),
531 (TIM7_UP_DAC_CH2, 0b0011, [DmaInput::Tim7Up, DmaInput::Dac1Ch2]),
532 (DCMI, 0b0100, [DmaInput::Dcmi]),
533 (TIM5_CH1, 0b0101, [DmaInput::Tim5Ch1]),
534 (AES_IN, 0b0110, [DmaInput::AesIn]),
535 (SDMMC1, 0b0111, [DmaInput::SdMmc1]),
536 },
537 DMA2_C6_SEL: {
538 (DCMI, 0b0000, [DmaInput::Dcmi]),
539 (SAI1_A, 0b0001, [DmaInput::Sai1A]),
540 (USART1_TX, 0b0010, [DmaInput::Usart1Tx]),
541 (LPUART1_TX, 0b0100, [DmaInput::LpUart1Tx]),
542 (I2C1_RX, 0b0101, [DmaInput::I2c1Rx]),
543 (TIM8_CH1, 0b0111, [DmaInput::Tim8Ch1]),
544 },
545 DMA2_C7_SEL: {
546 (SAI1_B, 0b0001, [DmaInput::Sai1B]),
547 (USART1_RX, 0b0010, [DmaInput::Usart1Rx]),
548 (QUADSPI, 0b0011, [DmaInput::QuadSpi]),
549 (LPUART1_RX, 0b0100, [DmaInput::LpUart1Rx]),
550 (I2C1_TX, 0b0101, [DmaInput::I2c1Tx]),
551 (HASH_IN, 0b0110, [DmaInput::HashIn]),
552 (TIM8_CH2, 0b0111, [DmaInput::Tim8Ch2]),
553 },
554}
555
556pub trait DmaMux {
557 fn set_request_line(&mut self, request_line: DmaInput) -> Result<(), Error>;
558}
559
560macro_rules! dmamux {
561 ($($dmaX:ident: { $( $CY:ident: ($cYcr:ident, $cYs:ident, $DMAX_CY_SEL:ident), )+ },)+) => {
562 $(
563 $(
564 impl DmaMux for $dmaX::$CY {
565 #[cfg(any(
566 feature = "stm32l4r9",
573 feature = "stm32l4s9"
574 ))]
575 #[inline(always)]
576 fn set_request_line(&mut self, request_line: DmaInput) -> Result<(), Error> {
577 let dmareq_id_a: DMAREQ_ID_A = request_line.try_into()?;
578 let mux = unsafe { &(*DMAMUX::ptr()) };
579 unsafe {
580 mux.$cYcr.modify(|_, w| w.dmareq_id().bits(dmareq_id_a.into()));
581 }
582
583 Ok(())
584 }
585
586 #[cfg(not(any(
587 feature = "stm32l4r9",
594 feature = "stm32l4s9"
595 )))]
596 #[inline(always)]
597 fn set_request_line(&mut self, request_line: DmaInput) -> Result<(), Error> {
598 let csel_val: $DMAX_CY_SEL = request_line.try_into()?;
599 self.cselr().modify(|_, w| w.$cYs().bits(csel_val.into()));
600
601 Ok(())
602 }
603 }
604 )+
605 )+
606 };
607}
608
609dmamux! {
610 dma1: {
611 C1: (c0cr, c1s, DMA1_C1_SEL),
612 C2: (c1cr, c2s, DMA1_C2_SEL),
613 C3: (c2cr, c3s, DMA1_C3_SEL),
614 C4: (c3cr, c4s, DMA1_C4_SEL),
615 C5: (c4cr, c5s, DMA1_C5_SEL),
616 C6: (c5cr, c6s, DMA1_C6_SEL),
617 C7: (c6cr, c7s, DMA1_C7_SEL),
618 },
619 dma2: {
620 C1: (c7cr, c1s, DMA2_C1_SEL),
621 C2: (c8cr, c2s, DMA2_C2_SEL),
622 C3: (c9cr, c3s, DMA2_C3_SEL),
623 C4: (c10cr, c4s, DMA2_C4_SEL),
624 C5: (c11cr, c5s, DMA2_C5_SEL),
625 C6: (c12cr, c6s, DMA2_C6_SEL),
626 C7: (c13cr, c7s, DMA2_C7_SEL),
627 },
628}