stm32l4x2_pac/pwr/
cr1.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CR1 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct LPRR {
47    bits: bool,
48}
49impl LPRR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct VOSR {
68    bits: u8,
69}
70impl VOSR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bits(&self) -> u8 {
74        self.bits
75    }
76}
77#[doc = r" Value of the field"]
78pub struct DBPR {
79    bits: bool,
80}
81impl DBPR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bit(&self) -> bool {
85        self.bits
86    }
87    #[doc = r" Returns `true` if the bit is clear (0)"]
88    #[inline]
89    pub fn bit_is_clear(&self) -> bool {
90        !self.bit()
91    }
92    #[doc = r" Returns `true` if the bit is set (1)"]
93    #[inline]
94    pub fn bit_is_set(&self) -> bool {
95        self.bit()
96    }
97}
98#[doc = r" Value of the field"]
99pub struct LPMSR {
100    bits: u8,
101}
102impl LPMSR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bits(&self) -> u8 {
106        self.bits
107    }
108}
109#[doc = r" Proxy"]
110pub struct _LPRW<'a> {
111    w: &'a mut W,
112}
113impl<'a> _LPRW<'a> {
114    #[doc = r" Sets the field bit"]
115    pub fn set_bit(self) -> &'a mut W {
116        self.bit(true)
117    }
118    #[doc = r" Clears the field bit"]
119    pub fn clear_bit(self) -> &'a mut W {
120        self.bit(false)
121    }
122    #[doc = r" Writes raw bits to the field"]
123    #[inline]
124    pub fn bit(self, value: bool) -> &'a mut W {
125        const MASK: bool = true;
126        const OFFSET: u8 = 14;
127        self.w.bits &= !((MASK as u32) << OFFSET);
128        self.w.bits |= ((value & MASK) as u32) << OFFSET;
129        self.w
130    }
131}
132#[doc = r" Proxy"]
133pub struct _VOSW<'a> {
134    w: &'a mut W,
135}
136impl<'a> _VOSW<'a> {
137    #[doc = r" Writes raw bits to the field"]
138    #[inline]
139    pub unsafe fn bits(self, value: u8) -> &'a mut W {
140        const MASK: u8 = 3;
141        const OFFSET: u8 = 9;
142        self.w.bits &= !((MASK as u32) << OFFSET);
143        self.w.bits |= ((value & MASK) as u32) << OFFSET;
144        self.w
145    }
146}
147#[doc = r" Proxy"]
148pub struct _DBPW<'a> {
149    w: &'a mut W,
150}
151impl<'a> _DBPW<'a> {
152    #[doc = r" Sets the field bit"]
153    pub fn set_bit(self) -> &'a mut W {
154        self.bit(true)
155    }
156    #[doc = r" Clears the field bit"]
157    pub fn clear_bit(self) -> &'a mut W {
158        self.bit(false)
159    }
160    #[doc = r" Writes raw bits to the field"]
161    #[inline]
162    pub fn bit(self, value: bool) -> &'a mut W {
163        const MASK: bool = true;
164        const OFFSET: u8 = 8;
165        self.w.bits &= !((MASK as u32) << OFFSET);
166        self.w.bits |= ((value & MASK) as u32) << OFFSET;
167        self.w
168    }
169}
170#[doc = r" Proxy"]
171pub struct _LPMSW<'a> {
172    w: &'a mut W,
173}
174impl<'a> _LPMSW<'a> {
175    #[doc = r" Writes raw bits to the field"]
176    #[inline]
177    pub unsafe fn bits(self, value: u8) -> &'a mut W {
178        const MASK: u8 = 7;
179        const OFFSET: u8 = 0;
180        self.w.bits &= !((MASK as u32) << OFFSET);
181        self.w.bits |= ((value & MASK) as u32) << OFFSET;
182        self.w
183    }
184}
185impl R {
186    #[doc = r" Value of the register as raw bits"]
187    #[inline]
188    pub fn bits(&self) -> u32 {
189        self.bits
190    }
191    #[doc = "Bit 14 - Low-power run"]
192    #[inline]
193    pub fn lpr(&self) -> LPRR {
194        let bits = {
195            const MASK: bool = true;
196            const OFFSET: u8 = 14;
197            ((self.bits >> OFFSET) & MASK as u32) != 0
198        };
199        LPRR { bits }
200    }
201    #[doc = "Bits 9:10 - Voltage scaling range selection"]
202    #[inline]
203    pub fn vos(&self) -> VOSR {
204        let bits = {
205            const MASK: u8 = 3;
206            const OFFSET: u8 = 9;
207            ((self.bits >> OFFSET) & MASK as u32) as u8
208        };
209        VOSR { bits }
210    }
211    #[doc = "Bit 8 - Disable backup domain write protection"]
212    #[inline]
213    pub fn dbp(&self) -> DBPR {
214        let bits = {
215            const MASK: bool = true;
216            const OFFSET: u8 = 8;
217            ((self.bits >> OFFSET) & MASK as u32) != 0
218        };
219        DBPR { bits }
220    }
221    #[doc = "Bits 0:2 - Low-power mode selection"]
222    #[inline]
223    pub fn lpms(&self) -> LPMSR {
224        let bits = {
225            const MASK: u8 = 7;
226            const OFFSET: u8 = 0;
227            ((self.bits >> OFFSET) & MASK as u32) as u8
228        };
229        LPMSR { bits }
230    }
231}
232impl W {
233    #[doc = r" Reset value of the register"]
234    #[inline]
235    pub fn reset_value() -> W {
236        W { bits: 512 }
237    }
238    #[doc = r" Writes raw bits to the register"]
239    #[inline]
240    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
241        self.bits = bits;
242        self
243    }
244    #[doc = "Bit 14 - Low-power run"]
245    #[inline]
246    pub fn lpr(&mut self) -> _LPRW {
247        _LPRW { w: self }
248    }
249    #[doc = "Bits 9:10 - Voltage scaling range selection"]
250    #[inline]
251    pub fn vos(&mut self) -> _VOSW {
252        _VOSW { w: self }
253    }
254    #[doc = "Bit 8 - Disable backup domain write protection"]
255    #[inline]
256    pub fn dbp(&mut self) -> _DBPW {
257        _DBPW { w: self }
258    }
259    #[doc = "Bits 0:2 - Low-power mode selection"]
260    #[inline]
261    pub fn lpms(&mut self) -> _LPMSW {
262        _LPMSW { w: self }
263    }
264}
stm32l4x2_pac/pwr/cr1.rs

stm32l4x2_pac/pwr/
cr1.rs
