#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFGR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SYNCPOLR {
bits: bool,
}
impl SYNCPOLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct SYNCSRCR {
bits: u8,
}
impl SYNCSRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct SYNCDIVR {
bits: u8,
}
impl SYNCDIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FELIMR {
bits: u8,
}
impl FELIMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct RELOADR {
bits: u16,
}
impl RELOADR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SYNCPOLW<'a> {
w: &'a mut W,
}
impl<'a> _SYNCPOLW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SYNCSRCW<'a> {
w: &'a mut W,
}
impl<'a> _SYNCSRCW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 28;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _SYNCDIVW<'a> {
w: &'a mut W,
}
impl<'a> _SYNCDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FELIMW<'a> {
w: &'a mut W,
}
impl<'a> _FELIMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RELOADW<'a> {
w: &'a mut W,
}
impl<'a> _RELOADW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 31 - SYNC polarity selection"]
#[inline]
pub fn syncpol(&self) -> SYNCPOLR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
};
SYNCPOLR { bits }
}
#[doc = "Bits 28:29 - SYNC signal source selection"]
#[inline]
pub fn syncsrc(&self) -> SYNCSRCR {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 28;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SYNCSRCR { bits }
}
#[doc = "Bits 24:26 - SYNC divider"]
#[inline]
pub fn syncdiv(&self) -> SYNCDIVR {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SYNCDIVR { bits }
}
#[doc = "Bits 16:23 - Frequency error limit"]
#[inline]
pub fn felim(&self) -> FELIMR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FELIMR { bits }
}
#[doc = "Bits 0:15 - Counter reload value"]
#[inline]
pub fn reload(&self) -> RELOADR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
RELOADR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 539147135 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 31 - SYNC polarity selection"]
#[inline]
pub fn syncpol(&mut self) -> _SYNCPOLW {
_SYNCPOLW { w: self }
}
#[doc = "Bits 28:29 - SYNC signal source selection"]
#[inline]
pub fn syncsrc(&mut self) -> _SYNCSRCW {
_SYNCSRCW { w: self }
}
#[doc = "Bits 24:26 - SYNC divider"]
#[inline]
pub fn syncdiv(&mut self) -> _SYNCDIVW {
_SYNCDIVW { w: self }
}
#[doc = "Bits 16:23 - Frequency error limit"]
#[inline]
pub fn felim(&mut self) -> _FELIMW {
_FELIMW { w: self }
}
#[doc = "Bits 0:15 - Counter reload value"]
#[inline]
pub fn reload(&mut self) -> _RELOADW {
_RELOADW { w: self }
}
}