stm32l4x2_pac/rcc/
pllcfgr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::PLLCFGR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct PLLRR {
47    bits: u8,
48}
49impl PLLRR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct PLLRENR {
58    bits: bool,
59}
60impl PLLRENR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct PLLQR {
79    bits: u8,
80}
81impl PLLQR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bits(&self) -> u8 {
85        self.bits
86    }
87}
88#[doc = r" Value of the field"]
89pub struct PLLQENR {
90    bits: bool,
91}
92impl PLLQENR {
93    #[doc = r" Value of the field as raw bits"]
94    #[inline]
95    pub fn bit(&self) -> bool {
96        self.bits
97    }
98    #[doc = r" Returns `true` if the bit is clear (0)"]
99    #[inline]
100    pub fn bit_is_clear(&self) -> bool {
101        !self.bit()
102    }
103    #[doc = r" Returns `true` if the bit is set (1)"]
104    #[inline]
105    pub fn bit_is_set(&self) -> bool {
106        self.bit()
107    }
108}
109#[doc = r" Value of the field"]
110pub struct PLLPR {
111    bits: bool,
112}
113impl PLLPR {
114    #[doc = r" Value of the field as raw bits"]
115    #[inline]
116    pub fn bit(&self) -> bool {
117        self.bits
118    }
119    #[doc = r" Returns `true` if the bit is clear (0)"]
120    #[inline]
121    pub fn bit_is_clear(&self) -> bool {
122        !self.bit()
123    }
124    #[doc = r" Returns `true` if the bit is set (1)"]
125    #[inline]
126    pub fn bit_is_set(&self) -> bool {
127        self.bit()
128    }
129}
130#[doc = r" Value of the field"]
131pub struct PLLPENR {
132    bits: bool,
133}
134impl PLLPENR {
135    #[doc = r" Value of the field as raw bits"]
136    #[inline]
137    pub fn bit(&self) -> bool {
138        self.bits
139    }
140    #[doc = r" Returns `true` if the bit is clear (0)"]
141    #[inline]
142    pub fn bit_is_clear(&self) -> bool {
143        !self.bit()
144    }
145    #[doc = r" Returns `true` if the bit is set (1)"]
146    #[inline]
147    pub fn bit_is_set(&self) -> bool {
148        self.bit()
149    }
150}
151#[doc = r" Value of the field"]
152pub struct PLLNR {
153    bits: u8,
154}
155impl PLLNR {
156    #[doc = r" Value of the field as raw bits"]
157    #[inline]
158    pub fn bits(&self) -> u8 {
159        self.bits
160    }
161}
162#[doc = r" Value of the field"]
163pub struct PLLMR {
164    bits: u8,
165}
166impl PLLMR {
167    #[doc = r" Value of the field as raw bits"]
168    #[inline]
169    pub fn bits(&self) -> u8 {
170        self.bits
171    }
172}
173#[doc = r" Value of the field"]
174pub struct PLLSRCR {
175    bits: u8,
176}
177impl PLLSRCR {
178    #[doc = r" Value of the field as raw bits"]
179    #[inline]
180    pub fn bits(&self) -> u8 {
181        self.bits
182    }
183}
184#[doc = r" Value of the field"]
185pub struct PLLPDIVR {
186    bits: u8,
187}
188impl PLLPDIVR {
189    #[doc = r" Value of the field as raw bits"]
190    #[inline]
191    pub fn bits(&self) -> u8 {
192        self.bits
193    }
194}
195#[doc = r" Proxy"]
196pub struct _PLLRW<'a> {
197    w: &'a mut W,
198}
199impl<'a> _PLLRW<'a> {
200    #[doc = r" Writes raw bits to the field"]
201    #[inline]
202    pub unsafe fn bits(self, value: u8) -> &'a mut W {
203        const MASK: u8 = 3;
204        const OFFSET: u8 = 25;
205        self.w.bits &= !((MASK as u32) << OFFSET);
206        self.w.bits |= ((value & MASK) as u32) << OFFSET;
207        self.w
208    }
209}
210#[doc = r" Proxy"]
211pub struct _PLLRENW<'a> {
212    w: &'a mut W,
213}
214impl<'a> _PLLRENW<'a> {
215    #[doc = r" Sets the field bit"]
216    pub fn set_bit(self) -> &'a mut W {
217        self.bit(true)
218    }
219    #[doc = r" Clears the field bit"]
220    pub fn clear_bit(self) -> &'a mut W {
221        self.bit(false)
222    }
223    #[doc = r" Writes raw bits to the field"]
224    #[inline]
225    pub fn bit(self, value: bool) -> &'a mut W {
226        const MASK: bool = true;
227        const OFFSET: u8 = 24;
228        self.w.bits &= !((MASK as u32) << OFFSET);
229        self.w.bits |= ((value & MASK) as u32) << OFFSET;
230        self.w
231    }
232}
233#[doc = r" Proxy"]
234pub struct _PLLQW<'a> {
235    w: &'a mut W,
236}
237impl<'a> _PLLQW<'a> {
238    #[doc = r" Writes raw bits to the field"]
239    #[inline]
240    pub unsafe fn bits(self, value: u8) -> &'a mut W {
241        const MASK: u8 = 3;
242        const OFFSET: u8 = 21;
243        self.w.bits &= !((MASK as u32) << OFFSET);
244        self.w.bits |= ((value & MASK) as u32) << OFFSET;
245        self.w
246    }
247}
248#[doc = r" Proxy"]
249pub struct _PLLQENW<'a> {
250    w: &'a mut W,
251}
252impl<'a> _PLLQENW<'a> {
253    #[doc = r" Sets the field bit"]
254    pub fn set_bit(self) -> &'a mut W {
255        self.bit(true)
256    }
257    #[doc = r" Clears the field bit"]
258    pub fn clear_bit(self) -> &'a mut W {
259        self.bit(false)
260    }
261    #[doc = r" Writes raw bits to the field"]
262    #[inline]
263    pub fn bit(self, value: bool) -> &'a mut W {
264        const MASK: bool = true;
265        const OFFSET: u8 = 20;
266        self.w.bits &= !((MASK as u32) << OFFSET);
267        self.w.bits |= ((value & MASK) as u32) << OFFSET;
268        self.w
269    }
270}
271#[doc = r" Proxy"]
272pub struct _PLLPW<'a> {
273    w: &'a mut W,
274}
275impl<'a> _PLLPW<'a> {
276    #[doc = r" Sets the field bit"]
277    pub fn set_bit(self) -> &'a mut W {
278        self.bit(true)
279    }
280    #[doc = r" Clears the field bit"]
281    pub fn clear_bit(self) -> &'a mut W {
282        self.bit(false)
283    }
284    #[doc = r" Writes raw bits to the field"]
285    #[inline]
286    pub fn bit(self, value: bool) -> &'a mut W {
287        const MASK: bool = true;
288        const OFFSET: u8 = 17;
289        self.w.bits &= !((MASK as u32) << OFFSET);
290        self.w.bits |= ((value & MASK) as u32) << OFFSET;
291        self.w
292    }
293}
294#[doc = r" Proxy"]
295pub struct _PLLPENW<'a> {
296    w: &'a mut W,
297}
298impl<'a> _PLLPENW<'a> {
299    #[doc = r" Sets the field bit"]
300    pub fn set_bit(self) -> &'a mut W {
301        self.bit(true)
302    }
303    #[doc = r" Clears the field bit"]
304    pub fn clear_bit(self) -> &'a mut W {
305        self.bit(false)
306    }
307    #[doc = r" Writes raw bits to the field"]
308    #[inline]
309    pub fn bit(self, value: bool) -> &'a mut W {
310        const MASK: bool = true;
311        const OFFSET: u8 = 16;
312        self.w.bits &= !((MASK as u32) << OFFSET);
313        self.w.bits |= ((value & MASK) as u32) << OFFSET;
314        self.w
315    }
316}
317#[doc = r" Proxy"]
318pub struct _PLLNW<'a> {
319    w: &'a mut W,
320}
321impl<'a> _PLLNW<'a> {
322    #[doc = r" Writes raw bits to the field"]
323    #[inline]
324    pub unsafe fn bits(self, value: u8) -> &'a mut W {
325        const MASK: u8 = 127;
326        const OFFSET: u8 = 8;
327        self.w.bits &= !((MASK as u32) << OFFSET);
328        self.w.bits |= ((value & MASK) as u32) << OFFSET;
329        self.w
330    }
331}
332#[doc = r" Proxy"]
333pub struct _PLLMW<'a> {
334    w: &'a mut W,
335}
336impl<'a> _PLLMW<'a> {
337    #[doc = r" Writes raw bits to the field"]
338    #[inline]
339    pub unsafe fn bits(self, value: u8) -> &'a mut W {
340        const MASK: u8 = 7;
341        const OFFSET: u8 = 4;
342        self.w.bits &= !((MASK as u32) << OFFSET);
343        self.w.bits |= ((value & MASK) as u32) << OFFSET;
344        self.w
345    }
346}
347#[doc = r" Proxy"]
348pub struct _PLLSRCW<'a> {
349    w: &'a mut W,
350}
351impl<'a> _PLLSRCW<'a> {
352    #[doc = r" Writes raw bits to the field"]
353    #[inline]
354    pub unsafe fn bits(self, value: u8) -> &'a mut W {
355        const MASK: u8 = 3;
356        const OFFSET: u8 = 0;
357        self.w.bits &= !((MASK as u32) << OFFSET);
358        self.w.bits |= ((value & MASK) as u32) << OFFSET;
359        self.w
360    }
361}
362#[doc = r" Proxy"]
363pub struct _PLLPDIVW<'a> {
364    w: &'a mut W,
365}
366impl<'a> _PLLPDIVW<'a> {
367    #[doc = r" Writes raw bits to the field"]
368    #[inline]
369    pub unsafe fn bits(self, value: u8) -> &'a mut W {
370        const MASK: u8 = 31;
371        const OFFSET: u8 = 27;
372        self.w.bits &= !((MASK as u32) << OFFSET);
373        self.w.bits |= ((value & MASK) as u32) << OFFSET;
374        self.w
375    }
376}
377impl R {
378    #[doc = r" Value of the register as raw bits"]
379    #[inline]
380    pub fn bits(&self) -> u32 {
381        self.bits
382    }
383    #[doc = "Bits 25:26 - Main PLL division factor for PLLCLK (system clock)"]
384    #[inline]
385    pub fn pllr(&self) -> PLLRR {
386        let bits = {
387            const MASK: u8 = 3;
388            const OFFSET: u8 = 25;
389            ((self.bits >> OFFSET) & MASK as u32) as u8
390        };
391        PLLRR { bits }
392    }
393    #[doc = "Bit 24 - Main PLL PLLCLK output enable"]
394    #[inline]
395    pub fn pllren(&self) -> PLLRENR {
396        let bits = {
397            const MASK: bool = true;
398            const OFFSET: u8 = 24;
399            ((self.bits >> OFFSET) & MASK as u32) != 0
400        };
401        PLLRENR { bits }
402    }
403    #[doc = "Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"]
404    #[inline]
405    pub fn pllq(&self) -> PLLQR {
406        let bits = {
407            const MASK: u8 = 3;
408            const OFFSET: u8 = 21;
409            ((self.bits >> OFFSET) & MASK as u32) as u8
410        };
411        PLLQR { bits }
412    }
413    #[doc = "Bit 20 - Main PLL PLLUSB1CLK output enable"]
414    #[inline]
415    pub fn pllqen(&self) -> PLLQENR {
416        let bits = {
417            const MASK: bool = true;
418            const OFFSET: u8 = 20;
419            ((self.bits >> OFFSET) & MASK as u32) != 0
420        };
421        PLLQENR { bits }
422    }
423    #[doc = "Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"]
424    #[inline]
425    pub fn pllp(&self) -> PLLPR {
426        let bits = {
427            const MASK: bool = true;
428            const OFFSET: u8 = 17;
429            ((self.bits >> OFFSET) & MASK as u32) != 0
430        };
431        PLLPR { bits }
432    }
433    #[doc = "Bit 16 - Main PLL PLLSAI3CLK output enable"]
434    #[inline]
435    pub fn pllpen(&self) -> PLLPENR {
436        let bits = {
437            const MASK: bool = true;
438            const OFFSET: u8 = 16;
439            ((self.bits >> OFFSET) & MASK as u32) != 0
440        };
441        PLLPENR { bits }
442    }
443    #[doc = "Bits 8:14 - Main PLL multiplication factor for VCO"]
444    #[inline]
445    pub fn plln(&self) -> PLLNR {
446        let bits = {
447            const MASK: u8 = 127;
448            const OFFSET: u8 = 8;
449            ((self.bits >> OFFSET) & MASK as u32) as u8
450        };
451        PLLNR { bits }
452    }
453    #[doc = "Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
454    #[inline]
455    pub fn pllm(&self) -> PLLMR {
456        let bits = {
457            const MASK: u8 = 7;
458            const OFFSET: u8 = 4;
459            ((self.bits >> OFFSET) & MASK as u32) as u8
460        };
461        PLLMR { bits }
462    }
463    #[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
464    #[inline]
465    pub fn pllsrc(&self) -> PLLSRCR {
466        let bits = {
467            const MASK: u8 = 3;
468            const OFFSET: u8 = 0;
469            ((self.bits >> OFFSET) & MASK as u32) as u8
470        };
471        PLLSRCR { bits }
472    }
473    #[doc = "Bits 27:31 - Main PLL division factor for PLLSAI2CLK"]
474    #[inline]
475    pub fn pllpdiv(&self) -> PLLPDIVR {
476        let bits = {
477            const MASK: u8 = 31;
478            const OFFSET: u8 = 27;
479            ((self.bits >> OFFSET) & MASK as u32) as u8
480        };
481        PLLPDIVR { bits }
482    }
483}
484impl W {
485    #[doc = r" Reset value of the register"]
486    #[inline]
487    pub fn reset_value() -> W {
488        W { bits: 4096 }
489    }
490    #[doc = r" Writes raw bits to the register"]
491    #[inline]
492    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
493        self.bits = bits;
494        self
495    }
496    #[doc = "Bits 25:26 - Main PLL division factor for PLLCLK (system clock)"]
497    #[inline]
498    pub fn pllr(&mut self) -> _PLLRW {
499        _PLLRW { w: self }
500    }
501    #[doc = "Bit 24 - Main PLL PLLCLK output enable"]
502    #[inline]
503    pub fn pllren(&mut self) -> _PLLRENW {
504        _PLLRENW { w: self }
505    }
506    #[doc = "Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"]
507    #[inline]
508    pub fn pllq(&mut self) -> _PLLQW {
509        _PLLQW { w: self }
510    }
511    #[doc = "Bit 20 - Main PLL PLLUSB1CLK output enable"]
512    #[inline]
513    pub fn pllqen(&mut self) -> _PLLQENW {
514        _PLLQENW { w: self }
515    }
516    #[doc = "Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"]
517    #[inline]
518    pub fn pllp(&mut self) -> _PLLPW {
519        _PLLPW { w: self }
520    }
521    #[doc = "Bit 16 - Main PLL PLLSAI3CLK output enable"]
522    #[inline]
523    pub fn pllpen(&mut self) -> _PLLPENW {
524        _PLLPENW { w: self }
525    }
526    #[doc = "Bits 8:14 - Main PLL multiplication factor for VCO"]
527    #[inline]
528    pub fn plln(&mut self) -> _PLLNW {
529        _PLLNW { w: self }
530    }
531    #[doc = "Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
532    #[inline]
533    pub fn pllm(&mut self) -> _PLLMW {
534        _PLLMW { w: self }
535    }
536    #[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
537    #[inline]
538    pub fn pllsrc(&mut self) -> _PLLSRCW {
539        _PLLSRCW { w: self }
540    }
541    #[doc = "Bits 27:31 - Main PLL division factor for PLLSAI2CLK"]
542    #[inline]
543    pub fn pllpdiv(&mut self) -> _PLLPDIVW {
544        _PLLPDIVW { w: self }
545    }
546}
stm32l4x2_pac/rcc/pllcfgr.rs

stm32l4x2_pac/rcc/
pllcfgr.rs
