stm32l4x2_pac/rcc/
icscr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::ICSCR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct HSITRIMR {
47    bits: u8,
48}
49impl HSITRIMR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct HSICALR {
58    bits: u8,
59}
60impl HSICALR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bits(&self) -> u8 {
64        self.bits
65    }
66}
67#[doc = r" Value of the field"]
68pub struct MSITRIMR {
69    bits: u8,
70}
71impl MSITRIMR {
72    #[doc = r" Value of the field as raw bits"]
73    #[inline]
74    pub fn bits(&self) -> u8 {
75        self.bits
76    }
77}
78#[doc = r" Value of the field"]
79pub struct MSICALR {
80    bits: u8,
81}
82impl MSICALR {
83    #[doc = r" Value of the field as raw bits"]
84    #[inline]
85    pub fn bits(&self) -> u8 {
86        self.bits
87    }
88}
89#[doc = r" Proxy"]
90pub struct _HSITRIMW<'a> {
91    w: &'a mut W,
92}
93impl<'a> _HSITRIMW<'a> {
94    #[doc = r" Writes raw bits to the field"]
95    #[inline]
96    pub unsafe fn bits(self, value: u8) -> &'a mut W {
97        const MASK: u8 = 31;
98        const OFFSET: u8 = 24;
99        self.w.bits &= !((MASK as u32) << OFFSET);
100        self.w.bits |= ((value & MASK) as u32) << OFFSET;
101        self.w
102    }
103}
104#[doc = r" Proxy"]
105pub struct _MSITRIMW<'a> {
106    w: &'a mut W,
107}
108impl<'a> _MSITRIMW<'a> {
109    #[doc = r" Writes raw bits to the field"]
110    #[inline]
111    pub unsafe fn bits(self, value: u8) -> &'a mut W {
112        const MASK: u8 = 255;
113        const OFFSET: u8 = 8;
114        self.w.bits &= !((MASK as u32) << OFFSET);
115        self.w.bits |= ((value & MASK) as u32) << OFFSET;
116        self.w
117    }
118}
119impl R {
120    #[doc = r" Value of the register as raw bits"]
121    #[inline]
122    pub fn bits(&self) -> u32 {
123        self.bits
124    }
125    #[doc = "Bits 24:28 - HSI clock trimming"]
126    #[inline]
127    pub fn hsitrim(&self) -> HSITRIMR {
128        let bits = {
129            const MASK: u8 = 31;
130            const OFFSET: u8 = 24;
131            ((self.bits >> OFFSET) & MASK as u32) as u8
132        };
133        HSITRIMR { bits }
134    }
135    #[doc = "Bits 16:23 - HSI clock calibration"]
136    #[inline]
137    pub fn hsical(&self) -> HSICALR {
138        let bits = {
139            const MASK: u8 = 255;
140            const OFFSET: u8 = 16;
141            ((self.bits >> OFFSET) & MASK as u32) as u8
142        };
143        HSICALR { bits }
144    }
145    #[doc = "Bits 8:15 - MSI clock trimming"]
146    #[inline]
147    pub fn msitrim(&self) -> MSITRIMR {
148        let bits = {
149            const MASK: u8 = 255;
150            const OFFSET: u8 = 8;
151            ((self.bits >> OFFSET) & MASK as u32) as u8
152        };
153        MSITRIMR { bits }
154    }
155    #[doc = "Bits 0:7 - MSI clock calibration"]
156    #[inline]
157    pub fn msical(&self) -> MSICALR {
158        let bits = {
159            const MASK: u8 = 255;
160            const OFFSET: u8 = 0;
161            ((self.bits >> OFFSET) & MASK as u32) as u8
162        };
163        MSICALR { bits }
164    }
165}
166impl W {
167    #[doc = r" Reset value of the register"]
168    #[inline]
169    pub fn reset_value() -> W {
170        W { bits: 268435456 }
171    }
172    #[doc = r" Writes raw bits to the register"]
173    #[inline]
174    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
175        self.bits = bits;
176        self
177    }
178    #[doc = "Bits 24:28 - HSI clock trimming"]
179    #[inline]
180    pub fn hsitrim(&mut self) -> _HSITRIMW {
181        _HSITRIMW { w: self }
182    }
183    #[doc = "Bits 8:15 - MSI clock trimming"]
184    #[inline]
185    pub fn msitrim(&mut self) -> _MSITRIMW {
186        _MSITRIMW { w: self }
187    }
188}
stm32l4x2_pac/rcc/icscr.rs

stm32l4x2_pac/rcc/
icscr.rs
