stm32l476/lcd/
lcd_fcr.rs

1#[doc = "Register `LCD_FCR` reader"]
2pub type R = crate::R<LcdFcrSpec>;
3#[doc = "Register `LCD_FCR` writer"]
4pub type W = crate::W<LcdFcrSpec>;
5#[doc = "High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Hd {
8    #[doc = "0: Permanent high drive disabled"]
9    B0x0 = 0,
10    #[doc = "1: Permanent high drive enabled. When HD=1, then the PON bits have to be programmed tom001."]
11    B0x1 = 1,
12}
13impl From<Hd> for bool {
14    #[inline(always)]
15    fn from(variant: Hd) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `HD` reader - High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated."]
20pub type HdR = crate::BitReader<Hd>;
21impl HdR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Hd {
25        match self.bits {
26            false => Hd::B0x0,
27            true => Hd::B0x1,
28        }
29    }
30    #[doc = "Permanent high drive disabled"]
31    #[inline(always)]
32    pub fn is_b_0x0(&self) -> bool {
33        *self == Hd::B0x0
34    }
35    #[doc = "Permanent high drive enabled. When HD=1, then the PON bits have to be programmed tom001."]
36    #[inline(always)]
37    pub fn is_b_0x1(&self) -> bool {
38        *self == Hd::B0x1
39    }
40}
41#[doc = "Field `HD` writer - High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated."]
42pub type HdW<'a, REG> = crate::BitWriter<'a, REG, Hd>;
43impl<'a, REG> HdW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Permanent high drive disabled"]
48    #[inline(always)]
49    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
50        self.variant(Hd::B0x0)
51    }
52    #[doc = "Permanent high drive enabled. When HD=1, then the PON bits have to be programmed tom001."]
53    #[inline(always)]
54    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
55        self.variant(Hd::B0x1)
56    }
57}
58#[doc = "Start of frame interrupt enable This bit is set and cleared by software.\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Sofie {
61    #[doc = "0: LCD start-of-frame interrupt disabled"]
62    B0x0 = 0,
63    #[doc = "1: LCD start-of-frame interrupt enabled"]
64    B0x1 = 1,
65}
66impl From<Sofie> for bool {
67    #[inline(always)]
68    fn from(variant: Sofie) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `SOFIE` reader - Start of frame interrupt enable This bit is set and cleared by software."]
73pub type SofieR = crate::BitReader<Sofie>;
74impl SofieR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Sofie {
78        match self.bits {
79            false => Sofie::B0x0,
80            true => Sofie::B0x1,
81        }
82    }
83    #[doc = "LCD start-of-frame interrupt disabled"]
84    #[inline(always)]
85    pub fn is_b_0x0(&self) -> bool {
86        *self == Sofie::B0x0
87    }
88    #[doc = "LCD start-of-frame interrupt enabled"]
89    #[inline(always)]
90    pub fn is_b_0x1(&self) -> bool {
91        *self == Sofie::B0x1
92    }
93}
94#[doc = "Field `SOFIE` writer - Start of frame interrupt enable This bit is set and cleared by software."]
95pub type SofieW<'a, REG> = crate::BitWriter<'a, REG, Sofie>;
96impl<'a, REG> SofieW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "LCD start-of-frame interrupt disabled"]
101    #[inline(always)]
102    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
103        self.variant(Sofie::B0x0)
104    }
105    #[doc = "LCD start-of-frame interrupt enabled"]
106    #[inline(always)]
107    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
108        self.variant(Sofie::B0x1)
109    }
110}
111#[doc = "Update display done interrupt enable This bit is set and cleared by software.\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum Uddie {
114    #[doc = "0: LCD Update display done interrupt disabled"]
115    B0x0 = 0,
116    #[doc = "1: LCD Update display done interrupt enabled"]
117    B0x1 = 1,
118}
119impl From<Uddie> for bool {
120    #[inline(always)]
121    fn from(variant: Uddie) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `UDDIE` reader - Update display done interrupt enable This bit is set and cleared by software."]
126pub type UddieR = crate::BitReader<Uddie>;
127impl UddieR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> Uddie {
131        match self.bits {
132            false => Uddie::B0x0,
133            true => Uddie::B0x1,
134        }
135    }
136    #[doc = "LCD Update display done interrupt disabled"]
137    #[inline(always)]
138    pub fn is_b_0x0(&self) -> bool {
139        *self == Uddie::B0x0
140    }
141    #[doc = "LCD Update display done interrupt enabled"]
142    #[inline(always)]
143    pub fn is_b_0x1(&self) -> bool {
144        *self == Uddie::B0x1
145    }
146}
147#[doc = "Field `UDDIE` writer - Update display done interrupt enable This bit is set and cleared by software."]
148pub type UddieW<'a, REG> = crate::BitWriter<'a, REG, Uddie>;
149impl<'a, REG> UddieW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "LCD Update display done interrupt disabled"]
154    #[inline(always)]
155    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
156        self.variant(Uddie::B0x0)
157    }
158    #[doc = "LCD Update display done interrupt enabled"]
159    #[inline(always)]
160    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
161        self.variant(Uddie::B0x1)
162    }
163}
164#[doc = "Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. Amshort pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse is never longer than one half prescaled LCD clock period. PON duration example with LCDCLK = 32.768mkHz and PS=0x03:\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166#[repr(u8)]
167pub enum Pon {
168    #[doc = "0: 0 ms"]
169    B0x0 = 0,
170    #[doc = "1: 244 ms"]
171    B0x1 = 1,
172    #[doc = "2: 488 ms"]
173    B0x2 = 2,
174    #[doc = "3: 782 ms"]
175    B0x3 = 3,
176    #[doc = "4: 976 ms"]
177    B0x4 = 4,
178    #[doc = "5: 1.22 ms"]
179    B0x5 = 5,
180    #[doc = "6: 1.46 ms"]
181    B0x6 = 6,
182    #[doc = "7: 1.71 ms"]
183    B0x7 = 7,
184}
185impl From<Pon> for u8 {
186    #[inline(always)]
187    fn from(variant: Pon) -> Self {
188        variant as _
189    }
190}
191impl crate::FieldSpec for Pon {
192    type Ux = u8;
193}
194impl crate::IsEnum for Pon {}
195#[doc = "Field `PON` reader - Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. Amshort pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse is never longer than one half prescaled LCD clock period. PON duration example with LCDCLK = 32.768mkHz and PS=0x03:"]
196pub type PonR = crate::FieldReader<Pon>;
197impl PonR {
198    #[doc = "Get enumerated values variant"]
199    #[inline(always)]
200    pub const fn variant(&self) -> Pon {
201        match self.bits {
202            0 => Pon::B0x0,
203            1 => Pon::B0x1,
204            2 => Pon::B0x2,
205            3 => Pon::B0x3,
206            4 => Pon::B0x4,
207            5 => Pon::B0x5,
208            6 => Pon::B0x6,
209            7 => Pon::B0x7,
210            _ => unreachable!(),
211        }
212    }
213    #[doc = "0 ms"]
214    #[inline(always)]
215    pub fn is_b_0x0(&self) -> bool {
216        *self == Pon::B0x0
217    }
218    #[doc = "244 ms"]
219    #[inline(always)]
220    pub fn is_b_0x1(&self) -> bool {
221        *self == Pon::B0x1
222    }
223    #[doc = "488 ms"]
224    #[inline(always)]
225    pub fn is_b_0x2(&self) -> bool {
226        *self == Pon::B0x2
227    }
228    #[doc = "782 ms"]
229    #[inline(always)]
230    pub fn is_b_0x3(&self) -> bool {
231        *self == Pon::B0x3
232    }
233    #[doc = "976 ms"]
234    #[inline(always)]
235    pub fn is_b_0x4(&self) -> bool {
236        *self == Pon::B0x4
237    }
238    #[doc = "1.22 ms"]
239    #[inline(always)]
240    pub fn is_b_0x5(&self) -> bool {
241        *self == Pon::B0x5
242    }
243    #[doc = "1.46 ms"]
244    #[inline(always)]
245    pub fn is_b_0x6(&self) -> bool {
246        *self == Pon::B0x6
247    }
248    #[doc = "1.71 ms"]
249    #[inline(always)]
250    pub fn is_b_0x7(&self) -> bool {
251        *self == Pon::B0x7
252    }
253}
254#[doc = "Field `PON` writer - Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. Amshort pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse is never longer than one half prescaled LCD clock period. PON duration example with LCDCLK = 32.768mkHz and PS=0x03:"]
255pub type PonW<'a, REG> = crate::FieldWriter<'a, REG, 3, Pon, crate::Safe>;
256impl<'a, REG> PonW<'a, REG>
257where
258    REG: crate::Writable + crate::RegisterSpec,
259    REG::Ux: From<u8>,
260{
261    #[doc = "0 ms"]
262    #[inline(always)]
263    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
264        self.variant(Pon::B0x0)
265    }
266    #[doc = "244 ms"]
267    #[inline(always)]
268    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
269        self.variant(Pon::B0x1)
270    }
271    #[doc = "488 ms"]
272    #[inline(always)]
273    pub fn b_0x2(self) -> &'a mut crate::W<REG> {
274        self.variant(Pon::B0x2)
275    }
276    #[doc = "782 ms"]
277    #[inline(always)]
278    pub fn b_0x3(self) -> &'a mut crate::W<REG> {
279        self.variant(Pon::B0x3)
280    }
281    #[doc = "976 ms"]
282    #[inline(always)]
283    pub fn b_0x4(self) -> &'a mut crate::W<REG> {
284        self.variant(Pon::B0x4)
285    }
286    #[doc = "1.22 ms"]
287    #[inline(always)]
288    pub fn b_0x5(self) -> &'a mut crate::W<REG> {
289        self.variant(Pon::B0x5)
290    }
291    #[doc = "1.46 ms"]
292    #[inline(always)]
293    pub fn b_0x6(self) -> &'a mut crate::W<REG> {
294        self.variant(Pon::B0x6)
295    }
296    #[doc = "1.71 ms"]
297    #[inline(always)]
298    pub fn b_0x7(self) -> &'a mut crate::W<REG> {
299        self.variant(Pon::B0x7)
300    }
301}
302#[doc = "Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. ......\n\nValue on reset: 0"]
303#[derive(Clone, Copy, Debug, PartialEq, Eq)]
304#[repr(u8)]
305pub enum Dead {
306    #[doc = "0: No dead time"]
307    B0x0 = 0,
308    #[doc = "1: 1 phase period dead time"]
309    B0x1 = 1,
310    #[doc = "2: 2 phase period dead time"]
311    B0x2 = 2,
312    #[doc = "7: 7 phase period dead time"]
313    B0x7 = 7,
314}
315impl From<Dead> for u8 {
316    #[inline(always)]
317    fn from(variant: Dead) -> Self {
318        variant as _
319    }
320}
321impl crate::FieldSpec for Dead {
322    type Ux = u8;
323}
324impl crate::IsEnum for Dead {}
325#[doc = "Field `DEAD` reader - Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. ......"]
326pub type DeadR = crate::FieldReader<Dead>;
327impl DeadR {
328    #[doc = "Get enumerated values variant"]
329    #[inline(always)]
330    pub const fn variant(&self) -> Option<Dead> {
331        match self.bits {
332            0 => Some(Dead::B0x0),
333            1 => Some(Dead::B0x1),
334            2 => Some(Dead::B0x2),
335            7 => Some(Dead::B0x7),
336            _ => None,
337        }
338    }
339    #[doc = "No dead time"]
340    #[inline(always)]
341    pub fn is_b_0x0(&self) -> bool {
342        *self == Dead::B0x0
343    }
344    #[doc = "1 phase period dead time"]
345    #[inline(always)]
346    pub fn is_b_0x1(&self) -> bool {
347        *self == Dead::B0x1
348    }
349    #[doc = "2 phase period dead time"]
350    #[inline(always)]
351    pub fn is_b_0x2(&self) -> bool {
352        *self == Dead::B0x2
353    }
354    #[doc = "7 phase period dead time"]
355    #[inline(always)]
356    pub fn is_b_0x7(&self) -> bool {
357        *self == Dead::B0x7
358    }
359}
360#[doc = "Field `DEAD` writer - Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. ......"]
361pub type DeadW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dead>;
362impl<'a, REG> DeadW<'a, REG>
363where
364    REG: crate::Writable + crate::RegisterSpec,
365    REG::Ux: From<u8>,
366{
367    #[doc = "No dead time"]
368    #[inline(always)]
369    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
370        self.variant(Dead::B0x0)
371    }
372    #[doc = "1 phase period dead time"]
373    #[inline(always)]
374    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
375        self.variant(Dead::B0x1)
376    }
377    #[doc = "2 phase period dead time"]
378    #[inline(always)]
379    pub fn b_0x2(self) -> &'a mut crate::W<REG> {
380        self.variant(Dead::B0x2)
381    }
382    #[doc = "7 phase period dead time"]
383    #[inline(always)]
384    pub fn b_0x7(self) -> &'a mut crate::W<REG> {
385        self.variant(Dead::B0x7)
386    }
387}
388#[doc = "Contrast control\n\nValue on reset: 0"]
389#[derive(Clone, Copy, Debug, PartialEq, Eq)]
390#[repr(u8)]
391pub enum Cc {
392    #[doc = "0: V<sub>LCD0</sub>"]
393    B0x0 = 0,
394    #[doc = "1: V<sub>LCD1</sub>"]
395    B0x1 = 1,
396    #[doc = "2: V<sub>LCD2</sub>"]
397    B0x2 = 2,
398    #[doc = "3: V<sub>LCD3</sub>"]
399    B0x3 = 3,
400    #[doc = "4: V<sub>LCD4</sub>"]
401    B0x4 = 4,
402    #[doc = "5: V<sub>LCD5</sub>"]
403    B0x5 = 5,
404    #[doc = "6: V<sub>LCD6</sub>"]
405    B0x6 = 6,
406    #[doc = "7: V<sub>LCD7</sub>"]
407    B0x7 = 7,
408}
409impl From<Cc> for u8 {
410    #[inline(always)]
411    fn from(variant: Cc) -> Self {
412        variant as _
413    }
414}
415impl crate::FieldSpec for Cc {
416    type Ux = u8;
417}
418impl crate::IsEnum for Cc {}
419#[doc = "Field `CC` reader - Contrast control"]
420pub type CcR = crate::FieldReader<Cc>;
421impl CcR {
422    #[doc = "Get enumerated values variant"]
423    #[inline(always)]
424    pub const fn variant(&self) -> Cc {
425        match self.bits {
426            0 => Cc::B0x0,
427            1 => Cc::B0x1,
428            2 => Cc::B0x2,
429            3 => Cc::B0x3,
430            4 => Cc::B0x4,
431            5 => Cc::B0x5,
432            6 => Cc::B0x6,
433            7 => Cc::B0x7,
434            _ => unreachable!(),
435        }
436    }
437    #[doc = "V<sub>LCD0</sub>"]
438    #[inline(always)]
439    pub fn is_b_0x0(&self) -> bool {
440        *self == Cc::B0x0
441    }
442    #[doc = "V<sub>LCD1</sub>"]
443    #[inline(always)]
444    pub fn is_b_0x1(&self) -> bool {
445        *self == Cc::B0x1
446    }
447    #[doc = "V<sub>LCD2</sub>"]
448    #[inline(always)]
449    pub fn is_b_0x2(&self) -> bool {
450        *self == Cc::B0x2
451    }
452    #[doc = "V<sub>LCD3</sub>"]
453    #[inline(always)]
454    pub fn is_b_0x3(&self) -> bool {
455        *self == Cc::B0x3
456    }
457    #[doc = "V<sub>LCD4</sub>"]
458    #[inline(always)]
459    pub fn is_b_0x4(&self) -> bool {
460        *self == Cc::B0x4
461    }
462    #[doc = "V<sub>LCD5</sub>"]
463    #[inline(always)]
464    pub fn is_b_0x5(&self) -> bool {
465        *self == Cc::B0x5
466    }
467    #[doc = "V<sub>LCD6</sub>"]
468    #[inline(always)]
469    pub fn is_b_0x6(&self) -> bool {
470        *self == Cc::B0x6
471    }
472    #[doc = "V<sub>LCD7</sub>"]
473    #[inline(always)]
474    pub fn is_b_0x7(&self) -> bool {
475        *self == Cc::B0x7
476    }
477}
478#[doc = "Field `CC` writer - Contrast control"]
479pub type CcW<'a, REG> = crate::FieldWriter<'a, REG, 3, Cc, crate::Safe>;
480impl<'a, REG> CcW<'a, REG>
481where
482    REG: crate::Writable + crate::RegisterSpec,
483    REG::Ux: From<u8>,
484{
485    #[doc = "V<sub>LCD0</sub>"]
486    #[inline(always)]
487    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
488        self.variant(Cc::B0x0)
489    }
490    #[doc = "V<sub>LCD1</sub>"]
491    #[inline(always)]
492    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
493        self.variant(Cc::B0x1)
494    }
495    #[doc = "V<sub>LCD2</sub>"]
496    #[inline(always)]
497    pub fn b_0x2(self) -> &'a mut crate::W<REG> {
498        self.variant(Cc::B0x2)
499    }
500    #[doc = "V<sub>LCD3</sub>"]
501    #[inline(always)]
502    pub fn b_0x3(self) -> &'a mut crate::W<REG> {
503        self.variant(Cc::B0x3)
504    }
505    #[doc = "V<sub>LCD4</sub>"]
506    #[inline(always)]
507    pub fn b_0x4(self) -> &'a mut crate::W<REG> {
508        self.variant(Cc::B0x4)
509    }
510    #[doc = "V<sub>LCD5</sub>"]
511    #[inline(always)]
512    pub fn b_0x5(self) -> &'a mut crate::W<REG> {
513        self.variant(Cc::B0x5)
514    }
515    #[doc = "V<sub>LCD6</sub>"]
516    #[inline(always)]
517    pub fn b_0x6(self) -> &'a mut crate::W<REG> {
518        self.variant(Cc::B0x6)
519    }
520    #[doc = "V<sub>LCD7</sub>"]
521    #[inline(always)]
522    pub fn b_0x7(self) -> &'a mut crate::W<REG> {
523        self.variant(Cc::B0x7)
524    }
525}
526#[doc = "Blink frequency selection\n\nValue on reset: 0"]
527#[derive(Clone, Copy, Debug, PartialEq, Eq)]
528#[repr(u8)]
529pub enum Blinkf {
530    #[doc = "0: f<sub>LCD</sub>/8"]
531    B0x0 = 0,
532    #[doc = "1: f<sub>LCD</sub>/16"]
533    B0x1 = 1,
534    #[doc = "2: f<sub>LCD</sub>/32"]
535    B0x2 = 2,
536    #[doc = "3: f<sub>LCD</sub>/64"]
537    B0x3 = 3,
538    #[doc = "4: f<sub>LCD</sub>/128"]
539    B0x4 = 4,
540    #[doc = "5: f<sub>LCD</sub>/256"]
541    B0x5 = 5,
542    #[doc = "6: f<sub>LCD</sub>/512"]
543    B0x6 = 6,
544    #[doc = "7: f<sub>LCD</sub>/1024"]
545    B0x7 = 7,
546}
547impl From<Blinkf> for u8 {
548    #[inline(always)]
549    fn from(variant: Blinkf) -> Self {
550        variant as _
551    }
552}
553impl crate::FieldSpec for Blinkf {
554    type Ux = u8;
555}
556impl crate::IsEnum for Blinkf {}
557#[doc = "Field `BLINKF` reader - Blink frequency selection"]
558pub type BlinkfR = crate::FieldReader<Blinkf>;
559impl BlinkfR {
560    #[doc = "Get enumerated values variant"]
561    #[inline(always)]
562    pub const fn variant(&self) -> Blinkf {
563        match self.bits {
564            0 => Blinkf::B0x0,
565            1 => Blinkf::B0x1,
566            2 => Blinkf::B0x2,
567            3 => Blinkf::B0x3,
568            4 => Blinkf::B0x4,
569            5 => Blinkf::B0x5,
570            6 => Blinkf::B0x6,
571            7 => Blinkf::B0x7,
572            _ => unreachable!(),
573        }
574    }
575    #[doc = "f<sub>LCD</sub>/8"]
576    #[inline(always)]
577    pub fn is_b_0x0(&self) -> bool {
578        *self == Blinkf::B0x0
579    }
580    #[doc = "f<sub>LCD</sub>/16"]
581    #[inline(always)]
582    pub fn is_b_0x1(&self) -> bool {
583        *self == Blinkf::B0x1
584    }
585    #[doc = "f<sub>LCD</sub>/32"]
586    #[inline(always)]
587    pub fn is_b_0x2(&self) -> bool {
588        *self == Blinkf::B0x2
589    }
590    #[doc = "f<sub>LCD</sub>/64"]
591    #[inline(always)]
592    pub fn is_b_0x3(&self) -> bool {
593        *self == Blinkf::B0x3
594    }
595    #[doc = "f<sub>LCD</sub>/128"]
596    #[inline(always)]
597    pub fn is_b_0x4(&self) -> bool {
598        *self == Blinkf::B0x4
599    }
600    #[doc = "f<sub>LCD</sub>/256"]
601    #[inline(always)]
602    pub fn is_b_0x5(&self) -> bool {
603        *self == Blinkf::B0x5
604    }
605    #[doc = "f<sub>LCD</sub>/512"]
606    #[inline(always)]
607    pub fn is_b_0x6(&self) -> bool {
608        *self == Blinkf::B0x6
609    }
610    #[doc = "f<sub>LCD</sub>/1024"]
611    #[inline(always)]
612    pub fn is_b_0x7(&self) -> bool {
613        *self == Blinkf::B0x7
614    }
615}
616#[doc = "Field `BLINKF` writer - Blink frequency selection"]
617pub type BlinkfW<'a, REG> = crate::FieldWriter<'a, REG, 3, Blinkf, crate::Safe>;
618impl<'a, REG> BlinkfW<'a, REG>
619where
620    REG: crate::Writable + crate::RegisterSpec,
621    REG::Ux: From<u8>,
622{
623    #[doc = "f<sub>LCD</sub>/8"]
624    #[inline(always)]
625    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
626        self.variant(Blinkf::B0x0)
627    }
628    #[doc = "f<sub>LCD</sub>/16"]
629    #[inline(always)]
630    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
631        self.variant(Blinkf::B0x1)
632    }
633    #[doc = "f<sub>LCD</sub>/32"]
634    #[inline(always)]
635    pub fn b_0x2(self) -> &'a mut crate::W<REG> {
636        self.variant(Blinkf::B0x2)
637    }
638    #[doc = "f<sub>LCD</sub>/64"]
639    #[inline(always)]
640    pub fn b_0x3(self) -> &'a mut crate::W<REG> {
641        self.variant(Blinkf::B0x3)
642    }
643    #[doc = "f<sub>LCD</sub>/128"]
644    #[inline(always)]
645    pub fn b_0x4(self) -> &'a mut crate::W<REG> {
646        self.variant(Blinkf::B0x4)
647    }
648    #[doc = "f<sub>LCD</sub>/256"]
649    #[inline(always)]
650    pub fn b_0x5(self) -> &'a mut crate::W<REG> {
651        self.variant(Blinkf::B0x5)
652    }
653    #[doc = "f<sub>LCD</sub>/512"]
654    #[inline(always)]
655    pub fn b_0x6(self) -> &'a mut crate::W<REG> {
656        self.variant(Blinkf::B0x6)
657    }
658    #[doc = "f<sub>LCD</sub>/1024"]
659    #[inline(always)]
660    pub fn b_0x7(self) -> &'a mut crate::W<REG> {
661        self.variant(Blinkf::B0x7)
662    }
663}
664#[doc = "Blink mode selection\n\nValue on reset: 0"]
665#[derive(Clone, Copy, Debug, PartialEq, Eq)]
666#[repr(u8)]
667pub enum Blink {
668    #[doc = "0: Blink disabled"]
669    B0x0 = 0,
670    #[doc = "1: Blink enabled on SEG\\[0\\], COM\\[0\\] (1 pixel)"]
671    B0x1 = 1,
672    #[doc = "2: Blink enabled on SEG\\[0\\], all COMs (up to 8 pixels depending on the programmed duty)"]
673    B0x2 = 2,
674    #[doc = "3: Blink enabled on all SEGs and all COMs (all pixels)"]
675    B0x3 = 3,
676}
677impl From<Blink> for u8 {
678    #[inline(always)]
679    fn from(variant: Blink) -> Self {
680        variant as _
681    }
682}
683impl crate::FieldSpec for Blink {
684    type Ux = u8;
685}
686impl crate::IsEnum for Blink {}
687#[doc = "Field `BLINK` reader - Blink mode selection"]
688pub type BlinkR = crate::FieldReader<Blink>;
689impl BlinkR {
690    #[doc = "Get enumerated values variant"]
691    #[inline(always)]
692    pub const fn variant(&self) -> Blink {
693        match self.bits {
694            0 => Blink::B0x0,
695            1 => Blink::B0x1,
696            2 => Blink::B0x2,
697            3 => Blink::B0x3,
698            _ => unreachable!(),
699        }
700    }
701    #[doc = "Blink disabled"]
702    #[inline(always)]
703    pub fn is_b_0x0(&self) -> bool {
704        *self == Blink::B0x0
705    }
706    #[doc = "Blink enabled on SEG\\[0\\], COM\\[0\\] (1 pixel)"]
707    #[inline(always)]
708    pub fn is_b_0x1(&self) -> bool {
709        *self == Blink::B0x1
710    }
711    #[doc = "Blink enabled on SEG\\[0\\], all COMs (up to 8 pixels depending on the programmed duty)"]
712    #[inline(always)]
713    pub fn is_b_0x2(&self) -> bool {
714        *self == Blink::B0x2
715    }
716    #[doc = "Blink enabled on all SEGs and all COMs (all pixels)"]
717    #[inline(always)]
718    pub fn is_b_0x3(&self) -> bool {
719        *self == Blink::B0x3
720    }
721}
722#[doc = "Field `BLINK` writer - Blink mode selection"]
723pub type BlinkW<'a, REG> = crate::FieldWriter<'a, REG, 2, Blink, crate::Safe>;
724impl<'a, REG> BlinkW<'a, REG>
725where
726    REG: crate::Writable + crate::RegisterSpec,
727    REG::Ux: From<u8>,
728{
729    #[doc = "Blink disabled"]
730    #[inline(always)]
731    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
732        self.variant(Blink::B0x0)
733    }
734    #[doc = "Blink enabled on SEG\\[0\\], COM\\[0\\] (1 pixel)"]
735    #[inline(always)]
736    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
737        self.variant(Blink::B0x1)
738    }
739    #[doc = "Blink enabled on SEG\\[0\\], all COMs (up to 8 pixels depending on the programmed duty)"]
740    #[inline(always)]
741    pub fn b_0x2(self) -> &'a mut crate::W<REG> {
742        self.variant(Blink::B0x2)
743    }
744    #[doc = "Blink enabled on all SEGs and all COMs (all pixels)"]
745    #[inline(always)]
746    pub fn b_0x3(self) -> &'a mut crate::W<REG> {
747        self.variant(Blink::B0x3)
748    }
749}
750#[doc = "DIV clock divider\n\nValue on reset: 0"]
751#[derive(Clone, Copy, Debug, PartialEq, Eq)]
752#[repr(u8)]
753pub enum Div {
754    #[doc = "0: ck_div = ck_ps/16"]
755    B0x0 = 0,
756    #[doc = "1: ck_div = ck_ps/17"]
757    B0x1 = 1,
758    #[doc = "15: ck_div = ck_ps/31"]
759    B0xF = 15,
760}
761impl From<Div> for u8 {
762    #[inline(always)]
763    fn from(variant: Div) -> Self {
764        variant as _
765    }
766}
767impl crate::FieldSpec for Div {
768    type Ux = u8;
769}
770impl crate::IsEnum for Div {}
771#[doc = "Field `DIV` reader - DIV clock divider"]
772pub type DivR = crate::FieldReader<Div>;
773impl DivR {
774    #[doc = "Get enumerated values variant"]
775    #[inline(always)]
776    pub const fn variant(&self) -> Option<Div> {
777        match self.bits {
778            0 => Some(Div::B0x0),
779            1 => Some(Div::B0x1),
780            15 => Some(Div::B0xF),
781            _ => None,
782        }
783    }
784    #[doc = "ck_div = ck_ps/16"]
785    #[inline(always)]
786    pub fn is_b_0x0(&self) -> bool {
787        *self == Div::B0x0
788    }
789    #[doc = "ck_div = ck_ps/17"]
790    #[inline(always)]
791    pub fn is_b_0x1(&self) -> bool {
792        *self == Div::B0x1
793    }
794    #[doc = "ck_div = ck_ps/31"]
795    #[inline(always)]
796    pub fn is_b_0x_f(&self) -> bool {
797        *self == Div::B0xF
798    }
799}
800#[doc = "Field `DIV` writer - DIV clock divider"]
801pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4, Div>;
802impl<'a, REG> DivW<'a, REG>
803where
804    REG: crate::Writable + crate::RegisterSpec,
805    REG::Ux: From<u8>,
806{
807    #[doc = "ck_div = ck_ps/16"]
808    #[inline(always)]
809    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
810        self.variant(Div::B0x0)
811    }
812    #[doc = "ck_div = ck_ps/17"]
813    #[inline(always)]
814    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
815        self.variant(Div::B0x1)
816    }
817    #[doc = "ck_div = ck_ps/31"]
818    #[inline(always)]
819    pub fn b_0x_f(self) -> &'a mut crate::W<REG> {
820        self.variant(Div::B0xF)
821    }
822}
823#[doc = "PS 16-bit prescaler\n\nValue on reset: 0"]
824#[derive(Clone, Copy, Debug, PartialEq, Eq)]
825#[repr(u8)]
826pub enum Ps {
827    #[doc = "0: ck_ps = LCDCLK"]
828    B0x0 = 0,
829    #[doc = "1: ck_ps = LCDCLK/2"]
830    B0x1 = 1,
831    #[doc = "15: ck_ps = LCDCLK/32768"]
832    B0xF = 15,
833}
834impl From<Ps> for u8 {
835    #[inline(always)]
836    fn from(variant: Ps) -> Self {
837        variant as _
838    }
839}
840impl crate::FieldSpec for Ps {
841    type Ux = u8;
842}
843impl crate::IsEnum for Ps {}
844#[doc = "Field `PS` reader - PS 16-bit prescaler"]
845pub type PsR = crate::FieldReader<Ps>;
846impl PsR {
847    #[doc = "Get enumerated values variant"]
848    #[inline(always)]
849    pub const fn variant(&self) -> Option<Ps> {
850        match self.bits {
851            0 => Some(Ps::B0x0),
852            1 => Some(Ps::B0x1),
853            15 => Some(Ps::B0xF),
854            _ => None,
855        }
856    }
857    #[doc = "ck_ps = LCDCLK"]
858    #[inline(always)]
859    pub fn is_b_0x0(&self) -> bool {
860        *self == Ps::B0x0
861    }
862    #[doc = "ck_ps = LCDCLK/2"]
863    #[inline(always)]
864    pub fn is_b_0x1(&self) -> bool {
865        *self == Ps::B0x1
866    }
867    #[doc = "ck_ps = LCDCLK/32768"]
868    #[inline(always)]
869    pub fn is_b_0x_f(&self) -> bool {
870        *self == Ps::B0xF
871    }
872}
873#[doc = "Field `PS` writer - PS 16-bit prescaler"]
874pub type PsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ps>;
875impl<'a, REG> PsW<'a, REG>
876where
877    REG: crate::Writable + crate::RegisterSpec,
878    REG::Ux: From<u8>,
879{
880    #[doc = "ck_ps = LCDCLK"]
881    #[inline(always)]
882    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
883        self.variant(Ps::B0x0)
884    }
885    #[doc = "ck_ps = LCDCLK/2"]
886    #[inline(always)]
887    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
888        self.variant(Ps::B0x1)
889    }
890    #[doc = "ck_ps = LCDCLK/32768"]
891    #[inline(always)]
892    pub fn b_0x_f(self) -> &'a mut crate::W<REG> {
893        self.variant(Ps::B0xF)
894    }
895}
896impl R {
897    #[doc = "Bit 0 - High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated."]
898    #[inline(always)]
899    pub fn hd(&self) -> HdR {
900        HdR::new((self.bits & 1) != 0)
901    }
902    #[doc = "Bit 1 - Start of frame interrupt enable This bit is set and cleared by software."]
903    #[inline(always)]
904    pub fn sofie(&self) -> SofieR {
905        SofieR::new(((self.bits >> 1) & 1) != 0)
906    }
907    #[doc = "Bit 3 - Update display done interrupt enable This bit is set and cleared by software."]
908    #[inline(always)]
909    pub fn uddie(&self) -> UddieR {
910        UddieR::new(((self.bits >> 3) & 1) != 0)
911    }
912    #[doc = "Bits 4:6 - Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. Amshort pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse is never longer than one half prescaled LCD clock period. PON duration example with LCDCLK = 32.768mkHz and PS=0x03:"]
913    #[inline(always)]
914    pub fn pon(&self) -> PonR {
915        PonR::new(((self.bits >> 4) & 7) as u8)
916    }
917    #[doc = "Bits 7:9 - Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. ......"]
918    #[inline(always)]
919    pub fn dead(&self) -> DeadR {
920        DeadR::new(((self.bits >> 7) & 7) as u8)
921    }
922    #[doc = "Bits 10:12 - Contrast control"]
923    #[inline(always)]
924    pub fn cc(&self) -> CcR {
925        CcR::new(((self.bits >> 10) & 7) as u8)
926    }
927    #[doc = "Bits 13:15 - Blink frequency selection"]
928    #[inline(always)]
929    pub fn blinkf(&self) -> BlinkfR {
930        BlinkfR::new(((self.bits >> 13) & 7) as u8)
931    }
932    #[doc = "Bits 16:17 - Blink mode selection"]
933    #[inline(always)]
934    pub fn blink(&self) -> BlinkR {
935        BlinkR::new(((self.bits >> 16) & 3) as u8)
936    }
937    #[doc = "Bits 18:21 - DIV clock divider"]
938    #[inline(always)]
939    pub fn div(&self) -> DivR {
940        DivR::new(((self.bits >> 18) & 0x0f) as u8)
941    }
942    #[doc = "Bits 22:25 - PS 16-bit prescaler"]
943    #[inline(always)]
944    pub fn ps(&self) -> PsR {
945        PsR::new(((self.bits >> 22) & 0x0f) as u8)
946    }
947}
948impl W {
949    #[doc = "Bit 0 - High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated."]
950    #[inline(always)]
951    pub fn hd(&mut self) -> HdW<LcdFcrSpec> {
952        HdW::new(self, 0)
953    }
954    #[doc = "Bit 1 - Start of frame interrupt enable This bit is set and cleared by software."]
955    #[inline(always)]
956    pub fn sofie(&mut self) -> SofieW<LcdFcrSpec> {
957        SofieW::new(self, 1)
958    }
959    #[doc = "Bit 3 - Update display done interrupt enable This bit is set and cleared by software."]
960    #[inline(always)]
961    pub fn uddie(&mut self) -> UddieW<LcdFcrSpec> {
962        UddieW::new(self, 3)
963    }
964    #[doc = "Bits 4:6 - Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. Amshort pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse is never longer than one half prescaled LCD clock period. PON duration example with LCDCLK = 32.768mkHz and PS=0x03:"]
965    #[inline(always)]
966    pub fn pon(&mut self) -> PonW<LcdFcrSpec> {
967        PonW::new(self, 4)
968    }
969    #[doc = "Bits 7:9 - Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. ......"]
970    #[inline(always)]
971    pub fn dead(&mut self) -> DeadW<LcdFcrSpec> {
972        DeadW::new(self, 7)
973    }
974    #[doc = "Bits 10:12 - Contrast control"]
975    #[inline(always)]
976    pub fn cc(&mut self) -> CcW<LcdFcrSpec> {
977        CcW::new(self, 10)
978    }
979    #[doc = "Bits 13:15 - Blink frequency selection"]
980    #[inline(always)]
981    pub fn blinkf(&mut self) -> BlinkfW<LcdFcrSpec> {
982        BlinkfW::new(self, 13)
983    }
984    #[doc = "Bits 16:17 - Blink mode selection"]
985    #[inline(always)]
986    pub fn blink(&mut self) -> BlinkW<LcdFcrSpec> {
987        BlinkW::new(self, 16)
988    }
989    #[doc = "Bits 18:21 - DIV clock divider"]
990    #[inline(always)]
991    pub fn div(&mut self) -> DivW<LcdFcrSpec> {
992        DivW::new(self, 18)
993    }
994    #[doc = "Bits 22:25 - PS 16-bit prescaler"]
995    #[inline(always)]
996    pub fn ps(&mut self) -> PsW<LcdFcrSpec> {
997        PsW::new(self, 22)
998    }
999}
1000#[doc = "LCD frame control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_fcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_fcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1001pub struct LcdFcrSpec;
1002impl crate::RegisterSpec for LcdFcrSpec {
1003    type Ux = u32;
1004}
1005#[doc = "`read()` method returns [`lcd_fcr::R`](R) reader structure"]
1006impl crate::Readable for LcdFcrSpec {}
1007#[doc = "`write(|w| ..)` method takes [`lcd_fcr::W`](W) writer structure"]
1008impl crate::Writable for LcdFcrSpec {
1009    type Safety = crate::Unsafe;
1010}
1011#[doc = "`reset()` method sets LCD_FCR to value 0"]
1012impl crate::Resettable for LcdFcrSpec {}
stm32l476/lcd/lcd_fcr.rs

stm32l476/lcd/
lcd_fcr.rs
