stm32l476/dbgmcu/
apb1_fzr1.rs1#[doc = "Register `APB1_FZR1` reader"]
2pub type R = crate::R<Apb1Fzr1Spec>;
3#[doc = "Register `APB1_FZR1` writer"]
4pub type W = crate::W<Apb1Fzr1Spec>;
5#[doc = "Field `DBG_TIMER2_STOP` reader - Debug Timer 2 stopped when Core is halted"]
6pub type DbgTimer2StopR = crate::BitReader;
7#[doc = "Field `DBG_TIMER2_STOP` writer - Debug Timer 2 stopped when Core is halted"]
8pub type DbgTimer2StopW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DBG_TIM3_STOP` reader - TIM3 counter stopped when core is halted"]
10pub type DbgTim3StopR = crate::BitReader;
11#[doc = "Field `DBG_TIM3_STOP` writer - TIM3 counter stopped when core is halted"]
12pub type DbgTim3StopW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DBG_TIM4_STOP` reader - TIM4 counter stopped when core is halted"]
14pub type DbgTim4StopR = crate::BitReader;
15#[doc = "Field `DBG_TIM4_STOP` writer - TIM4 counter stopped when core is halted"]
16pub type DbgTim4StopW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DBG_TIM5_STOP` reader - TIM5 counter stopped when core is halted"]
18pub type DbgTim5StopR = crate::BitReader;
19#[doc = "Field `DBG_TIM5_STOP` writer - TIM5 counter stopped when core is halted"]
20pub type DbgTim5StopW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DBG_TIMER6_STOP` reader - Debug Timer 6 stopped when Core is halted"]
22pub type DbgTimer6StopR = crate::BitReader;
23#[doc = "Field `DBG_TIMER6_STOP` writer - Debug Timer 6 stopped when Core is halted"]
24pub type DbgTimer6StopW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DBG_TIM7_STOP` reader - TIM7 counter stopped when core is halted"]
26pub type DbgTim7StopR = crate::BitReader;
27#[doc = "Field `DBG_TIM7_STOP` writer - TIM7 counter stopped when core is halted"]
28pub type DbgTim7StopW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DBG_RTC_STOP` reader - Debug RTC stopped when Core is halted"]
30pub type DbgRtcStopR = crate::BitReader;
31#[doc = "Field `DBG_RTC_STOP` writer - Debug RTC stopped when Core is halted"]
32pub type DbgRtcStopW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DBG_WWDG_STOP` reader - Debug Window Wachdog stopped when Core is halted"]
34pub type DbgWwdgStopR = crate::BitReader;
35#[doc = "Field `DBG_WWDG_STOP` writer - Debug Window Wachdog stopped when Core is halted"]
36pub type DbgWwdgStopW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DBG_IWDG_STOP` reader - Debug Independent Wachdog stopped when Core is halted"]
38pub type DbgIwdgStopR = crate::BitReader;
39#[doc = "Field `DBG_IWDG_STOP` writer - Debug Independent Wachdog stopped when Core is halted"]
40pub type DbgIwdgStopW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DBG_I2C1_STOP` reader - I2C1 SMBUS timeout mode stopped when core is halted"]
42pub type DbgI2c1StopR = crate::BitReader;
43#[doc = "Field `DBG_I2C1_STOP` writer - I2C1 SMBUS timeout mode stopped when core is halted"]
44pub type DbgI2c1StopW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `DBG_I2C2_STOP` reader - I2C2 SMBUS timeout mode stopped when core is halted"]
46pub type DbgI2c2StopR = crate::BitReader;
47#[doc = "Field `DBG_I2C2_STOP` writer - I2C2 SMBUS timeout mode stopped when core is halted"]
48pub type DbgI2c2StopW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `DBG_I2C3_STOP` reader - I2C3 SMBUS timeout counter stopped when core is halted"]
50pub type DbgI2c3StopR = crate::BitReader;
51#[doc = "Field `DBG_I2C3_STOP` writer - I2C3 SMBUS timeout counter stopped when core is halted"]
52pub type DbgI2c3StopW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `DBG_CAN_STOP` reader - bxCAN stopped when core is halted"]
54pub type DbgCanStopR = crate::BitReader;
55#[doc = "Field `DBG_CAN_STOP` writer - bxCAN stopped when core is halted"]
56pub type DbgCanStopW<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DBG_LPTIMER_STOP` reader - LPTIM1 counter stopped when core is halted"]
58pub type DbgLptimerStopR = crate::BitReader;
59#[doc = "Field `DBG_LPTIMER_STOP` writer - LPTIM1 counter stopped when core is halted"]
60pub type DbgLptimerStopW<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62 #[doc = "Bit 0 - Debug Timer 2 stopped when Core is halted"]
63 #[inline(always)]
64 pub fn dbg_timer2_stop(&self) -> DbgTimer2StopR {
65 DbgTimer2StopR::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bit 1 - TIM3 counter stopped when core is halted"]
68 #[inline(always)]
69 pub fn dbg_tim3_stop(&self) -> DbgTim3StopR {
70 DbgTim3StopR::new(((self.bits >> 1) & 1) != 0)
71 }
72 #[doc = "Bit 2 - TIM4 counter stopped when core is halted"]
73 #[inline(always)]
74 pub fn dbg_tim4_stop(&self) -> DbgTim4StopR {
75 DbgTim4StopR::new(((self.bits >> 2) & 1) != 0)
76 }
77 #[doc = "Bit 3 - TIM5 counter stopped when core is halted"]
78 #[inline(always)]
79 pub fn dbg_tim5_stop(&self) -> DbgTim5StopR {
80 DbgTim5StopR::new(((self.bits >> 3) & 1) != 0)
81 }
82 #[doc = "Bit 4 - Debug Timer 6 stopped when Core is halted"]
83 #[inline(always)]
84 pub fn dbg_timer6_stop(&self) -> DbgTimer6StopR {
85 DbgTimer6StopR::new(((self.bits >> 4) & 1) != 0)
86 }
87 #[doc = "Bit 5 - TIM7 counter stopped when core is halted"]
88 #[inline(always)]
89 pub fn dbg_tim7_stop(&self) -> DbgTim7StopR {
90 DbgTim7StopR::new(((self.bits >> 5) & 1) != 0)
91 }
92 #[doc = "Bit 10 - Debug RTC stopped when Core is halted"]
93 #[inline(always)]
94 pub fn dbg_rtc_stop(&self) -> DbgRtcStopR {
95 DbgRtcStopR::new(((self.bits >> 10) & 1) != 0)
96 }
97 #[doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted"]
98 #[inline(always)]
99 pub fn dbg_wwdg_stop(&self) -> DbgWwdgStopR {
100 DbgWwdgStopR::new(((self.bits >> 11) & 1) != 0)
101 }
102 #[doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted"]
103 #[inline(always)]
104 pub fn dbg_iwdg_stop(&self) -> DbgIwdgStopR {
105 DbgIwdgStopR::new(((self.bits >> 12) & 1) != 0)
106 }
107 #[doc = "Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted"]
108 #[inline(always)]
109 pub fn dbg_i2c1_stop(&self) -> DbgI2c1StopR {
110 DbgI2c1StopR::new(((self.bits >> 21) & 1) != 0)
111 }
112 #[doc = "Bit 22 - I2C2 SMBUS timeout mode stopped when core is halted"]
113 #[inline(always)]
114 pub fn dbg_i2c2_stop(&self) -> DbgI2c2StopR {
115 DbgI2c2StopR::new(((self.bits >> 22) & 1) != 0)
116 }
117 #[doc = "Bit 23 - I2C3 SMBUS timeout counter stopped when core is halted"]
118 #[inline(always)]
119 pub fn dbg_i2c3_stop(&self) -> DbgI2c3StopR {
120 DbgI2c3StopR::new(((self.bits >> 23) & 1) != 0)
121 }
122 #[doc = "Bit 25 - bxCAN stopped when core is halted"]
123 #[inline(always)]
124 pub fn dbg_can_stop(&self) -> DbgCanStopR {
125 DbgCanStopR::new(((self.bits >> 25) & 1) != 0)
126 }
127 #[doc = "Bit 31 - LPTIM1 counter stopped when core is halted"]
128 #[inline(always)]
129 pub fn dbg_lptimer_stop(&self) -> DbgLptimerStopR {
130 DbgLptimerStopR::new(((self.bits >> 31) & 1) != 0)
131 }
132}
133impl W {
134 #[doc = "Bit 0 - Debug Timer 2 stopped when Core is halted"]
135 #[inline(always)]
136 pub fn dbg_timer2_stop(&mut self) -> DbgTimer2StopW<Apb1Fzr1Spec> {
137 DbgTimer2StopW::new(self, 0)
138 }
139 #[doc = "Bit 1 - TIM3 counter stopped when core is halted"]
140 #[inline(always)]
141 pub fn dbg_tim3_stop(&mut self) -> DbgTim3StopW<Apb1Fzr1Spec> {
142 DbgTim3StopW::new(self, 1)
143 }
144 #[doc = "Bit 2 - TIM4 counter stopped when core is halted"]
145 #[inline(always)]
146 pub fn dbg_tim4_stop(&mut self) -> DbgTim4StopW<Apb1Fzr1Spec> {
147 DbgTim4StopW::new(self, 2)
148 }
149 #[doc = "Bit 3 - TIM5 counter stopped when core is halted"]
150 #[inline(always)]
151 pub fn dbg_tim5_stop(&mut self) -> DbgTim5StopW<Apb1Fzr1Spec> {
152 DbgTim5StopW::new(self, 3)
153 }
154 #[doc = "Bit 4 - Debug Timer 6 stopped when Core is halted"]
155 #[inline(always)]
156 pub fn dbg_timer6_stop(&mut self) -> DbgTimer6StopW<Apb1Fzr1Spec> {
157 DbgTimer6StopW::new(self, 4)
158 }
159 #[doc = "Bit 5 - TIM7 counter stopped when core is halted"]
160 #[inline(always)]
161 pub fn dbg_tim7_stop(&mut self) -> DbgTim7StopW<Apb1Fzr1Spec> {
162 DbgTim7StopW::new(self, 5)
163 }
164 #[doc = "Bit 10 - Debug RTC stopped when Core is halted"]
165 #[inline(always)]
166 pub fn dbg_rtc_stop(&mut self) -> DbgRtcStopW<Apb1Fzr1Spec> {
167 DbgRtcStopW::new(self, 10)
168 }
169 #[doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted"]
170 #[inline(always)]
171 pub fn dbg_wwdg_stop(&mut self) -> DbgWwdgStopW<Apb1Fzr1Spec> {
172 DbgWwdgStopW::new(self, 11)
173 }
174 #[doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted"]
175 #[inline(always)]
176 pub fn dbg_iwdg_stop(&mut self) -> DbgIwdgStopW<Apb1Fzr1Spec> {
177 DbgIwdgStopW::new(self, 12)
178 }
179 #[doc = "Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted"]
180 #[inline(always)]
181 pub fn dbg_i2c1_stop(&mut self) -> DbgI2c1StopW<Apb1Fzr1Spec> {
182 DbgI2c1StopW::new(self, 21)
183 }
184 #[doc = "Bit 22 - I2C2 SMBUS timeout mode stopped when core is halted"]
185 #[inline(always)]
186 pub fn dbg_i2c2_stop(&mut self) -> DbgI2c2StopW<Apb1Fzr1Spec> {
187 DbgI2c2StopW::new(self, 22)
188 }
189 #[doc = "Bit 23 - I2C3 SMBUS timeout counter stopped when core is halted"]
190 #[inline(always)]
191 pub fn dbg_i2c3_stop(&mut self) -> DbgI2c3StopW<Apb1Fzr1Spec> {
192 DbgI2c3StopW::new(self, 23)
193 }
194 #[doc = "Bit 25 - bxCAN stopped when core is halted"]
195 #[inline(always)]
196 pub fn dbg_can_stop(&mut self) -> DbgCanStopW<Apb1Fzr1Spec> {
197 DbgCanStopW::new(self, 25)
198 }
199 #[doc = "Bit 31 - LPTIM1 counter stopped when core is halted"]
200 #[inline(always)]
201 pub fn dbg_lptimer_stop(&mut self) -> DbgLptimerStopW<Apb1Fzr1Spec> {
202 DbgLptimerStopW::new(self, 31)
203 }
204}
205#[doc = "APB Low Freeze Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`apb1_fzr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fzr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
206pub struct Apb1Fzr1Spec;
207impl crate::RegisterSpec for Apb1Fzr1Spec {
208 type Ux = u32;
209}
210#[doc = "`read()` method returns [`apb1_fzr1::R`](R) reader structure"]
211impl crate::Readable for Apb1Fzr1Spec {}
212#[doc = "`write(|w| ..)` method takes [`apb1_fzr1::W`](W) writer structure"]
213impl crate::Writable for Apb1Fzr1Spec {
214 type Safety = crate::Unsafe;
215}
216#[doc = "`reset()` method sets APB1_FZR1 to value 0"]
217impl crate::Resettable for Apb1Fzr1Spec {}