1#[doc = "Register `CCIPR` reader"]
2pub type R = crate::R<CciprSpec>;
3#[doc = "Register `CCIPR` writer"]
4pub type W = crate::W<CciprSpec>;
5#[doc = "Field `USART1SEL` reader - USART1 clock source selection"]
6pub type Usart1selR = crate::FieldReader;
7#[doc = "Field `USART1SEL` writer - USART1 clock source selection"]
8pub type Usart1selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `USART2SEL` reader - USART2 clock source selection"]
10pub type Usart2selR = crate::FieldReader;
11#[doc = "Field `USART2SEL` writer - USART2 clock source selection"]
12pub type Usart2selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `USART3SEL` reader - USART3 clock source selection"]
14pub type Usart3selR = crate::FieldReader;
15#[doc = "Field `USART3SEL` writer - USART3 clock source selection"]
16pub type Usart3selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `UART4SEL` reader - UART4 clock source selection"]
18pub type Uart4selR = crate::FieldReader;
19#[doc = "Field `UART4SEL` writer - UART4 clock source selection"]
20pub type Uart4selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `UART5SEL` reader - UART5 clock source selection"]
22pub type Uart5selR = crate::FieldReader;
23#[doc = "Field `UART5SEL` writer - UART5 clock source selection"]
24pub type Uart5selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `LPUART1SEL` reader - LPUART1 clock source selection"]
26pub type Lpuart1selR = crate::FieldReader;
27#[doc = "Field `LPUART1SEL` writer - LPUART1 clock source selection"]
28pub type Lpuart1selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `I2C1SEL` reader - I2C1 clock source selection"]
30pub type I2c1selR = crate::FieldReader;
31#[doc = "Field `I2C1SEL` writer - I2C1 clock source selection"]
32pub type I2c1selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `I2C2SEL` reader - I2C2 clock source selection"]
34pub type I2c2selR = crate::FieldReader;
35#[doc = "Field `I2C2SEL` writer - I2C2 clock source selection"]
36pub type I2c2selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `I2C3SEL` reader - I2C3 clock source selection"]
38pub type I2c3selR = crate::FieldReader;
39#[doc = "Field `I2C3SEL` writer - I2C3 clock source selection"]
40pub type I2c3selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `LPTIM1SEL` reader - Low power timer 1 clock source selection"]
42pub type Lptim1selR = crate::FieldReader;
43#[doc = "Field `LPTIM1SEL` writer - Low power timer 1 clock source selection"]
44pub type Lptim1selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45#[doc = "Field `LPTIM2SEL` reader - Low power timer 2 clock source selection"]
46pub type Lptim2selR = crate::FieldReader;
47#[doc = "Field `LPTIM2SEL` writer - Low power timer 2 clock source selection"]
48pub type Lptim2selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
49#[doc = "Field `SAI1SEL` reader - SAI1 clock source selection"]
50pub type Sai1selR = crate::FieldReader;
51#[doc = "Field `SAI1SEL` writer - SAI1 clock source selection"]
52pub type Sai1selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
53#[doc = "Field `SAI2SEL` reader - SAI2 clock source selection"]
54pub type Sai2selR = crate::FieldReader;
55#[doc = "Field `SAI2SEL` writer - SAI2 clock source selection"]
56pub type Sai2selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
57#[doc = "Field `CLK48SEL` reader - 48 MHz clock source selection"]
58pub type Clk48selR = crate::FieldReader;
59#[doc = "Field `CLK48SEL` writer - 48 MHz clock source selection"]
60pub type Clk48selW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
61#[doc = "Field `ADCSEL` reader - ADCs clock source selection"]
62pub type AdcselR = crate::FieldReader;
63#[doc = "Field `ADCSEL` writer - ADCs clock source selection"]
64pub type AdcselW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
65#[doc = "Field `SWPMI1SEL` reader - SWPMI1 clock source selection"]
66pub type Swpmi1selR = crate::BitReader;
67#[doc = "Field `SWPMI1SEL` writer - SWPMI1 clock source selection"]
68pub type Swpmi1selW<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `DFSDMSEL` reader - DFSDM clock source selection"]
70pub type DfsdmselR = crate::BitReader;
71#[doc = "Field `DFSDMSEL` writer - DFSDM clock source selection"]
72pub type DfsdmselW<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74 #[doc = "Bits 0:1 - USART1 clock source selection"]
75 #[inline(always)]
76 pub fn usart1sel(&self) -> Usart1selR {
77 Usart1selR::new((self.bits & 3) as u8)
78 }
79 #[doc = "Bits 2:3 - USART2 clock source selection"]
80 #[inline(always)]
81 pub fn usart2sel(&self) -> Usart2selR {
82 Usart2selR::new(((self.bits >> 2) & 3) as u8)
83 }
84 #[doc = "Bits 4:5 - USART3 clock source selection"]
85 #[inline(always)]
86 pub fn usart3sel(&self) -> Usart3selR {
87 Usart3selR::new(((self.bits >> 4) & 3) as u8)
88 }
89 #[doc = "Bits 6:7 - UART4 clock source selection"]
90 #[inline(always)]
91 pub fn uart4sel(&self) -> Uart4selR {
92 Uart4selR::new(((self.bits >> 6) & 3) as u8)
93 }
94 #[doc = "Bits 8:9 - UART5 clock source selection"]
95 #[inline(always)]
96 pub fn uart5sel(&self) -> Uart5selR {
97 Uart5selR::new(((self.bits >> 8) & 3) as u8)
98 }
99 #[doc = "Bits 10:11 - LPUART1 clock source selection"]
100 #[inline(always)]
101 pub fn lpuart1sel(&self) -> Lpuart1selR {
102 Lpuart1selR::new(((self.bits >> 10) & 3) as u8)
103 }
104 #[doc = "Bits 12:13 - I2C1 clock source selection"]
105 #[inline(always)]
106 pub fn i2c1sel(&self) -> I2c1selR {
107 I2c1selR::new(((self.bits >> 12) & 3) as u8)
108 }
109 #[doc = "Bits 14:15 - I2C2 clock source selection"]
110 #[inline(always)]
111 pub fn i2c2sel(&self) -> I2c2selR {
112 I2c2selR::new(((self.bits >> 14) & 3) as u8)
113 }
114 #[doc = "Bits 16:17 - I2C3 clock source selection"]
115 #[inline(always)]
116 pub fn i2c3sel(&self) -> I2c3selR {
117 I2c3selR::new(((self.bits >> 16) & 3) as u8)
118 }
119 #[doc = "Bits 18:19 - Low power timer 1 clock source selection"]
120 #[inline(always)]
121 pub fn lptim1sel(&self) -> Lptim1selR {
122 Lptim1selR::new(((self.bits >> 18) & 3) as u8)
123 }
124 #[doc = "Bits 20:21 - Low power timer 2 clock source selection"]
125 #[inline(always)]
126 pub fn lptim2sel(&self) -> Lptim2selR {
127 Lptim2selR::new(((self.bits >> 20) & 3) as u8)
128 }
129 #[doc = "Bits 22:23 - SAI1 clock source selection"]
130 #[inline(always)]
131 pub fn sai1sel(&self) -> Sai1selR {
132 Sai1selR::new(((self.bits >> 22) & 3) as u8)
133 }
134 #[doc = "Bits 24:25 - SAI2 clock source selection"]
135 #[inline(always)]
136 pub fn sai2sel(&self) -> Sai2selR {
137 Sai2selR::new(((self.bits >> 24) & 3) as u8)
138 }
139 #[doc = "Bits 26:27 - 48 MHz clock source selection"]
140 #[inline(always)]
141 pub fn clk48sel(&self) -> Clk48selR {
142 Clk48selR::new(((self.bits >> 26) & 3) as u8)
143 }
144 #[doc = "Bits 28:29 - ADCs clock source selection"]
145 #[inline(always)]
146 pub fn adcsel(&self) -> AdcselR {
147 AdcselR::new(((self.bits >> 28) & 3) as u8)
148 }
149 #[doc = "Bit 30 - SWPMI1 clock source selection"]
150 #[inline(always)]
151 pub fn swpmi1sel(&self) -> Swpmi1selR {
152 Swpmi1selR::new(((self.bits >> 30) & 1) != 0)
153 }
154 #[doc = "Bit 31 - DFSDM clock source selection"]
155 #[inline(always)]
156 pub fn dfsdmsel(&self) -> DfsdmselR {
157 DfsdmselR::new(((self.bits >> 31) & 1) != 0)
158 }
159}
160impl W {
161 #[doc = "Bits 0:1 - USART1 clock source selection"]
162 #[inline(always)]
163 pub fn usart1sel(&mut self) -> Usart1selW<CciprSpec> {
164 Usart1selW::new(self, 0)
165 }
166 #[doc = "Bits 2:3 - USART2 clock source selection"]
167 #[inline(always)]
168 pub fn usart2sel(&mut self) -> Usart2selW<CciprSpec> {
169 Usart2selW::new(self, 2)
170 }
171 #[doc = "Bits 4:5 - USART3 clock source selection"]
172 #[inline(always)]
173 pub fn usart3sel(&mut self) -> Usart3selW<CciprSpec> {
174 Usart3selW::new(self, 4)
175 }
176 #[doc = "Bits 6:7 - UART4 clock source selection"]
177 #[inline(always)]
178 pub fn uart4sel(&mut self) -> Uart4selW<CciprSpec> {
179 Uart4selW::new(self, 6)
180 }
181 #[doc = "Bits 8:9 - UART5 clock source selection"]
182 #[inline(always)]
183 pub fn uart5sel(&mut self) -> Uart5selW<CciprSpec> {
184 Uart5selW::new(self, 8)
185 }
186 #[doc = "Bits 10:11 - LPUART1 clock source selection"]
187 #[inline(always)]
188 pub fn lpuart1sel(&mut self) -> Lpuart1selW<CciprSpec> {
189 Lpuart1selW::new(self, 10)
190 }
191 #[doc = "Bits 12:13 - I2C1 clock source selection"]
192 #[inline(always)]
193 pub fn i2c1sel(&mut self) -> I2c1selW<CciprSpec> {
194 I2c1selW::new(self, 12)
195 }
196 #[doc = "Bits 14:15 - I2C2 clock source selection"]
197 #[inline(always)]
198 pub fn i2c2sel(&mut self) -> I2c2selW<CciprSpec> {
199 I2c2selW::new(self, 14)
200 }
201 #[doc = "Bits 16:17 - I2C3 clock source selection"]
202 #[inline(always)]
203 pub fn i2c3sel(&mut self) -> I2c3selW<CciprSpec> {
204 I2c3selW::new(self, 16)
205 }
206 #[doc = "Bits 18:19 - Low power timer 1 clock source selection"]
207 #[inline(always)]
208 pub fn lptim1sel(&mut self) -> Lptim1selW<CciprSpec> {
209 Lptim1selW::new(self, 18)
210 }
211 #[doc = "Bits 20:21 - Low power timer 2 clock source selection"]
212 #[inline(always)]
213 pub fn lptim2sel(&mut self) -> Lptim2selW<CciprSpec> {
214 Lptim2selW::new(self, 20)
215 }
216 #[doc = "Bits 22:23 - SAI1 clock source selection"]
217 #[inline(always)]
218 pub fn sai1sel(&mut self) -> Sai1selW<CciprSpec> {
219 Sai1selW::new(self, 22)
220 }
221 #[doc = "Bits 24:25 - SAI2 clock source selection"]
222 #[inline(always)]
223 pub fn sai2sel(&mut self) -> Sai2selW<CciprSpec> {
224 Sai2selW::new(self, 24)
225 }
226 #[doc = "Bits 26:27 - 48 MHz clock source selection"]
227 #[inline(always)]
228 pub fn clk48sel(&mut self) -> Clk48selW<CciprSpec> {
229 Clk48selW::new(self, 26)
230 }
231 #[doc = "Bits 28:29 - ADCs clock source selection"]
232 #[inline(always)]
233 pub fn adcsel(&mut self) -> AdcselW<CciprSpec> {
234 AdcselW::new(self, 28)
235 }
236 #[doc = "Bit 30 - SWPMI1 clock source selection"]
237 #[inline(always)]
238 pub fn swpmi1sel(&mut self) -> Swpmi1selW<CciprSpec> {
239 Swpmi1selW::new(self, 30)
240 }
241 #[doc = "Bit 31 - DFSDM clock source selection"]
242 #[inline(always)]
243 pub fn dfsdmsel(&mut self) -> DfsdmselW<CciprSpec> {
244 DfsdmselW::new(self, 31)
245 }
246}
247#[doc = "CCIPR\n\nYou can [`read`](crate::Reg::read) this register and get [`ccipr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
248pub struct CciprSpec;
249impl crate::RegisterSpec for CciprSpec {
250 type Ux = u32;
251}
252#[doc = "`read()` method returns [`ccipr::R`](R) reader structure"]
253impl crate::Readable for CciprSpec {}
254#[doc = "`write(|w| ..)` method takes [`ccipr::W`](W) writer structure"]
255impl crate::Writable for CciprSpec {
256 type Safety = crate::Unsafe;
257}
258#[doc = "`reset()` method sets CCIPR to value 0"]
259impl crate::Resettable for CciprSpec {}