1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 ch0cfgr1: Ch0cfgr1,
5 ch0cfgr2: Ch0cfgr2,
6 ch0awscdr: Ch0awscdr,
7 ch0wdatr: Ch0wdatr,
8 ch0datinr: Ch0datinr,
9 ch0dlyr: Ch0dlyr,
10 _reserved6: [u8; 0x08],
11 ch1cfgr1: Ch1cfgr1,
12 ch1cfgr2: Ch1cfgr2,
13 ch1awscdr: Ch1awscdr,
14 ch1wdatr: Ch1wdatr,
15 ch1datinr: Ch1datinr,
16 ch1dlyr: Ch1dlyr,
17 _reserved12: [u8; 0x08],
18 ch2cfgr1: Ch2cfgr1,
19 ch2cfgr2: Ch2cfgr2,
20 ch2awscdr: Ch2awscdr,
21 ch2wdatr: Ch2wdatr,
22 ch2datinr: Ch2datinr,
23 ch2dlyr: Ch2dlyr,
24 _reserved18: [u8; 0x08],
25 ch3cfgr1: Ch3cfgr1,
26 ch3cfgr2: Ch3cfgr2,
27 ch3awscdr: Ch3awscdr,
28 ch3wdatr: Ch3wdatr,
29 ch3datinr: Ch3datinr,
30 ch3dlyr: Ch3dlyr,
31 _reserved24: [u8; 0x08],
32 ch4cfgr1: Ch4cfgr1,
33 ch4cfgr2: Ch4cfgr2,
34 ch4awscdr: Ch4awscdr,
35 ch4wdatr: Ch4wdatr,
36 ch4datinr: Ch4datinr,
37 ch4dlyr: Ch4dlyr,
38 _reserved30: [u8; 0x08],
39 ch5cfgr1: Ch5cfgr1,
40 ch5cfgr2: Ch5cfgr2,
41 ch5awscdr: Ch5awscdr,
42 ch5wdatr: Ch5wdatr,
43 ch5datinr: Ch5datinr,
44 ch5dlyr: Ch5dlyr,
45 _reserved36: [u8; 0x08],
46 ch6cfgr1: Ch6cfgr1,
47 ch6cfgr2: Ch6cfgr2,
48 ch6awscdr: Ch6awscdr,
49 ch6wdatr: Ch6wdatr,
50 ch6datinr: Ch6datinr,
51 ch6dlyr: Ch6dlyr,
52 _reserved42: [u8; 0x08],
53 ch7cfgr1: Ch7cfgr1,
54 ch7cfgr2: Ch7cfgr2,
55 ch7awscdr: Ch7awscdr,
56 ch7wdatr: Ch7wdatr,
57 ch7datinr: Ch7datinr,
58 ch7dlyr: Ch7dlyr,
59 _reserved48: [u8; 0x08],
60 dfsdm_flt0cr1: DfsdmFlt0cr1,
61 dfsdm_flt0cr2: DfsdmFlt0cr2,
62 dfsdm_flt0isr: DfsdmFlt0isr,
63 dfsdm_flt0icr: DfsdmFlt0icr,
64 dfsdm_flt0jchgr: DfsdmFlt0jchgr,
65 dfsdm_flt0fcr: DfsdmFlt0fcr,
66 dfsdm_flt0jdatar: DfsdmFlt0jdatar,
67 dfsdm_flt0rdatar: DfsdmFlt0rdatar,
68 dfsdm_flt0awhtr: DfsdmFlt0awhtr,
69 dfsdm_flt0awltr: DfsdmFlt0awltr,
70 dfsdm_flt0awsr: DfsdmFlt0awsr,
71 dfsdm_flt0awcfr: DfsdmFlt0awcfr,
72 dfsdm_flt0exmax: DfsdmFlt0exmax,
73 dfsdm_flt0exmin: DfsdmFlt0exmin,
74 dfsdm_flt0cnvtimr: DfsdmFlt0cnvtimr,
75 _reserved63: [u8; 0x44],
76 dfsdm_flt1cr1: DfsdmFlt1cr1,
77 dfsdm_flt1cr2: DfsdmFlt1cr2,
78 dfsdm_flt1isr: DfsdmFlt1isr,
79 dfsdm_flt1icr: DfsdmFlt1icr,
80 dfsdm_flt1chgr: DfsdmFlt1chgr,
81 dfsdm_flt1fcr: DfsdmFlt1fcr,
82 dfsdm_flt1jdatar: DfsdmFlt1jdatar,
83 dfsdm_flt1rdatar: DfsdmFlt1rdatar,
84 dfsdm_flt1awhtr: DfsdmFlt1awhtr,
85 dfsdm_flt1awltr: DfsdmFlt1awltr,
86 dfsdm_flt1awsr: DfsdmFlt1awsr,
87 dfsdm_flt1awcfr: DfsdmFlt1awcfr,
88 dfsdm_flt1exmax: DfsdmFlt1exmax,
89 dfsdm_flt1exmin: DfsdmFlt1exmin,
90 dfsdm_flt1cnvtimr: DfsdmFlt1cnvtimr,
91 _reserved78: [u8; 0x44],
92 dfsdm_flt2cr1: DfsdmFlt2cr1,
93 dfsdm_flt2cr2: DfsdmFlt2cr2,
94 dfsdm_flt2isr: DfsdmFlt2isr,
95 dfsdm_flt2icr: DfsdmFlt2icr,
96 dfsdm_flt2jchgr: DfsdmFlt2jchgr,
97 dfsdm_flt2fcr: DfsdmFlt2fcr,
98 dfsdm_flt2jdatar: DfsdmFlt2jdatar,
99 dfsdm_flt2rdatar: DfsdmFlt2rdatar,
100 dfsdm_flt2awhtr: DfsdmFlt2awhtr,
101 dfsdm_flt2awltr: DfsdmFlt2awltr,
102 dfsdm_flt2awsr: DfsdmFlt2awsr,
103 dfsdm_flt2awcfr: DfsdmFlt2awcfr,
104 dfsdm_flt2exmax: DfsdmFlt2exmax,
105 dfsdm_flt2exmin: DfsdmFlt2exmin,
106 dfsdm_flt2cnvtimr: DfsdmFlt2cnvtimr,
107 _reserved93: [u8; 0x44],
108 dfsdm_flt3cr1: DfsdmFlt3cr1,
109 dfsdm_flt3cr2: DfsdmFlt3cr2,
110 dfsdm_flt3isr: DfsdmFlt3isr,
111 dfsdm_flt3icr: DfsdmFlt3icr,
112 dfsdm_flt3jchgr: DfsdmFlt3jchgr,
113 dfsdm_flt3fcr: DfsdmFlt3fcr,
114 dfsdm_flt3jdatar: DfsdmFlt3jdatar,
115 dfsdm_flt3rdatar: DfsdmFlt3rdatar,
116 dfsdm_flt3awhtr: DfsdmFlt3awhtr,
117 dfsdm_flt3awltr: DfsdmFlt3awltr,
118 dfsdm_flt3awsr: DfsdmFlt3awsr,
119 dfsdm_flt3awcfr: DfsdmFlt3awcfr,
120 dfsdm_flt3exmax: DfsdmFlt3exmax,
121 dfsdm_flt3exmin: DfsdmFlt3exmin,
122 dfsdm_flt3cnvtimr: DfsdmFlt3cnvtimr,
123}
124impl RegisterBlock {
125 #[doc = "0x00 - channel configuration y register"]
126 #[inline(always)]
127 pub const fn ch0cfgr1(&self) -> &Ch0cfgr1 {
128 &self.ch0cfgr1
129 }
130 #[doc = "0x04 - channel configuration y register"]
131 #[inline(always)]
132 pub const fn ch0cfgr2(&self) -> &Ch0cfgr2 {
133 &self.ch0cfgr2
134 }
135 #[doc = "0x08 - analog watchdog and short-circuit detector register"]
136 #[inline(always)]
137 pub const fn ch0awscdr(&self) -> &Ch0awscdr {
138 &self.ch0awscdr
139 }
140 #[doc = "0x0c - channel watchdog filter data register"]
141 #[inline(always)]
142 pub const fn ch0wdatr(&self) -> &Ch0wdatr {
143 &self.ch0wdatr
144 }
145 #[doc = "0x10 - channel data input register"]
146 #[inline(always)]
147 pub const fn ch0datinr(&self) -> &Ch0datinr {
148 &self.ch0datinr
149 }
150 #[doc = "0x14 - channel y delay register"]
151 #[inline(always)]
152 pub const fn ch0dlyr(&self) -> &Ch0dlyr {
153 &self.ch0dlyr
154 }
155 #[doc = "0x20 - CH1CFGR1"]
156 #[inline(always)]
157 pub const fn ch1cfgr1(&self) -> &Ch1cfgr1 {
158 &self.ch1cfgr1
159 }
160 #[doc = "0x24 - CH1CFGR2"]
161 #[inline(always)]
162 pub const fn ch1cfgr2(&self) -> &Ch1cfgr2 {
163 &self.ch1cfgr2
164 }
165 #[doc = "0x28 - CH1AWSCDR"]
166 #[inline(always)]
167 pub const fn ch1awscdr(&self) -> &Ch1awscdr {
168 &self.ch1awscdr
169 }
170 #[doc = "0x2c - CH1WDATR"]
171 #[inline(always)]
172 pub const fn ch1wdatr(&self) -> &Ch1wdatr {
173 &self.ch1wdatr
174 }
175 #[doc = "0x30 - CH1DATINR"]
176 #[inline(always)]
177 pub const fn ch1datinr(&self) -> &Ch1datinr {
178 &self.ch1datinr
179 }
180 #[doc = "0x34 - channel y delay register"]
181 #[inline(always)]
182 pub const fn ch1dlyr(&self) -> &Ch1dlyr {
183 &self.ch1dlyr
184 }
185 #[doc = "0x40 - CH2CFGR1"]
186 #[inline(always)]
187 pub const fn ch2cfgr1(&self) -> &Ch2cfgr1 {
188 &self.ch2cfgr1
189 }
190 #[doc = "0x44 - CH2CFGR2"]
191 #[inline(always)]
192 pub const fn ch2cfgr2(&self) -> &Ch2cfgr2 {
193 &self.ch2cfgr2
194 }
195 #[doc = "0x48 - CH2AWSCDR"]
196 #[inline(always)]
197 pub const fn ch2awscdr(&self) -> &Ch2awscdr {
198 &self.ch2awscdr
199 }
200 #[doc = "0x4c - CH2WDATR"]
201 #[inline(always)]
202 pub const fn ch2wdatr(&self) -> &Ch2wdatr {
203 &self.ch2wdatr
204 }
205 #[doc = "0x50 - CH2DATINR"]
206 #[inline(always)]
207 pub const fn ch2datinr(&self) -> &Ch2datinr {
208 &self.ch2datinr
209 }
210 #[doc = "0x54 - channel y delay register"]
211 #[inline(always)]
212 pub const fn ch2dlyr(&self) -> &Ch2dlyr {
213 &self.ch2dlyr
214 }
215 #[doc = "0x60 - CH3CFGR1"]
216 #[inline(always)]
217 pub const fn ch3cfgr1(&self) -> &Ch3cfgr1 {
218 &self.ch3cfgr1
219 }
220 #[doc = "0x64 - CH3CFGR2"]
221 #[inline(always)]
222 pub const fn ch3cfgr2(&self) -> &Ch3cfgr2 {
223 &self.ch3cfgr2
224 }
225 #[doc = "0x68 - CH3AWSCDR"]
226 #[inline(always)]
227 pub const fn ch3awscdr(&self) -> &Ch3awscdr {
228 &self.ch3awscdr
229 }
230 #[doc = "0x6c - CH3WDATR"]
231 #[inline(always)]
232 pub const fn ch3wdatr(&self) -> &Ch3wdatr {
233 &self.ch3wdatr
234 }
235 #[doc = "0x70 - CH3DATINR"]
236 #[inline(always)]
237 pub const fn ch3datinr(&self) -> &Ch3datinr {
238 &self.ch3datinr
239 }
240 #[doc = "0x74 - channel y delay register"]
241 #[inline(always)]
242 pub const fn ch3dlyr(&self) -> &Ch3dlyr {
243 &self.ch3dlyr
244 }
245 #[doc = "0x80 - CH4CFGR1"]
246 #[inline(always)]
247 pub const fn ch4cfgr1(&self) -> &Ch4cfgr1 {
248 &self.ch4cfgr1
249 }
250 #[doc = "0x84 - CH4CFGR2"]
251 #[inline(always)]
252 pub const fn ch4cfgr2(&self) -> &Ch4cfgr2 {
253 &self.ch4cfgr2
254 }
255 #[doc = "0x88 - CH4AWSCDR"]
256 #[inline(always)]
257 pub const fn ch4awscdr(&self) -> &Ch4awscdr {
258 &self.ch4awscdr
259 }
260 #[doc = "0x8c - CH4WDATR"]
261 #[inline(always)]
262 pub const fn ch4wdatr(&self) -> &Ch4wdatr {
263 &self.ch4wdatr
264 }
265 #[doc = "0x90 - CH4DATINR"]
266 #[inline(always)]
267 pub const fn ch4datinr(&self) -> &Ch4datinr {
268 &self.ch4datinr
269 }
270 #[doc = "0x94 - channel y delay register"]
271 #[inline(always)]
272 pub const fn ch4dlyr(&self) -> &Ch4dlyr {
273 &self.ch4dlyr
274 }
275 #[doc = "0xa0 - CH5CFGR1"]
276 #[inline(always)]
277 pub const fn ch5cfgr1(&self) -> &Ch5cfgr1 {
278 &self.ch5cfgr1
279 }
280 #[doc = "0xa4 - CH5CFGR2"]
281 #[inline(always)]
282 pub const fn ch5cfgr2(&self) -> &Ch5cfgr2 {
283 &self.ch5cfgr2
284 }
285 #[doc = "0xa8 - CH5AWSCDR"]
286 #[inline(always)]
287 pub const fn ch5awscdr(&self) -> &Ch5awscdr {
288 &self.ch5awscdr
289 }
290 #[doc = "0xac - CH5WDATR"]
291 #[inline(always)]
292 pub const fn ch5wdatr(&self) -> &Ch5wdatr {
293 &self.ch5wdatr
294 }
295 #[doc = "0xb0 - CH5DATINR"]
296 #[inline(always)]
297 pub const fn ch5datinr(&self) -> &Ch5datinr {
298 &self.ch5datinr
299 }
300 #[doc = "0xb4 - channel y delay register"]
301 #[inline(always)]
302 pub const fn ch5dlyr(&self) -> &Ch5dlyr {
303 &self.ch5dlyr
304 }
305 #[doc = "0xc0 - CH6CFGR1"]
306 #[inline(always)]
307 pub const fn ch6cfgr1(&self) -> &Ch6cfgr1 {
308 &self.ch6cfgr1
309 }
310 #[doc = "0xc4 - CH6CFGR2"]
311 #[inline(always)]
312 pub const fn ch6cfgr2(&self) -> &Ch6cfgr2 {
313 &self.ch6cfgr2
314 }
315 #[doc = "0xc8 - CH6AWSCDR"]
316 #[inline(always)]
317 pub const fn ch6awscdr(&self) -> &Ch6awscdr {
318 &self.ch6awscdr
319 }
320 #[doc = "0xcc - CH6WDATR"]
321 #[inline(always)]
322 pub const fn ch6wdatr(&self) -> &Ch6wdatr {
323 &self.ch6wdatr
324 }
325 #[doc = "0xd0 - CH6DATINR"]
326 #[inline(always)]
327 pub const fn ch6datinr(&self) -> &Ch6datinr {
328 &self.ch6datinr
329 }
330 #[doc = "0xd4 - channel y delay register"]
331 #[inline(always)]
332 pub const fn ch6dlyr(&self) -> &Ch6dlyr {
333 &self.ch6dlyr
334 }
335 #[doc = "0xe0 - CH7CFGR1"]
336 #[inline(always)]
337 pub const fn ch7cfgr1(&self) -> &Ch7cfgr1 {
338 &self.ch7cfgr1
339 }
340 #[doc = "0xe4 - CH7CFGR2"]
341 #[inline(always)]
342 pub const fn ch7cfgr2(&self) -> &Ch7cfgr2 {
343 &self.ch7cfgr2
344 }
345 #[doc = "0xe8 - CH7AWSCDR"]
346 #[inline(always)]
347 pub const fn ch7awscdr(&self) -> &Ch7awscdr {
348 &self.ch7awscdr
349 }
350 #[doc = "0xec - CH7WDATR"]
351 #[inline(always)]
352 pub const fn ch7wdatr(&self) -> &Ch7wdatr {
353 &self.ch7wdatr
354 }
355 #[doc = "0xf0 - CH7DATINR"]
356 #[inline(always)]
357 pub const fn ch7datinr(&self) -> &Ch7datinr {
358 &self.ch7datinr
359 }
360 #[doc = "0xf4 - channel y delay register"]
361 #[inline(always)]
362 pub const fn ch7dlyr(&self) -> &Ch7dlyr {
363 &self.ch7dlyr
364 }
365 #[doc = "0x100 - control register 1"]
366 #[inline(always)]
367 pub const fn dfsdm_flt0cr1(&self) -> &DfsdmFlt0cr1 {
368 &self.dfsdm_flt0cr1
369 }
370 #[doc = "0x104 - control register 2"]
371 #[inline(always)]
372 pub const fn dfsdm_flt0cr2(&self) -> &DfsdmFlt0cr2 {
373 &self.dfsdm_flt0cr2
374 }
375 #[doc = "0x108 - interrupt and status register"]
376 #[inline(always)]
377 pub const fn dfsdm_flt0isr(&self) -> &DfsdmFlt0isr {
378 &self.dfsdm_flt0isr
379 }
380 #[doc = "0x10c - interrupt flag clear register"]
381 #[inline(always)]
382 pub const fn dfsdm_flt0icr(&self) -> &DfsdmFlt0icr {
383 &self.dfsdm_flt0icr
384 }
385 #[doc = "0x110 - injected channel group selection register"]
386 #[inline(always)]
387 pub const fn dfsdm_flt0jchgr(&self) -> &DfsdmFlt0jchgr {
388 &self.dfsdm_flt0jchgr
389 }
390 #[doc = "0x114 - filter control register"]
391 #[inline(always)]
392 pub const fn dfsdm_flt0fcr(&self) -> &DfsdmFlt0fcr {
393 &self.dfsdm_flt0fcr
394 }
395 #[doc = "0x118 - data register for injected group"]
396 #[inline(always)]
397 pub const fn dfsdm_flt0jdatar(&self) -> &DfsdmFlt0jdatar {
398 &self.dfsdm_flt0jdatar
399 }
400 #[doc = "0x11c - data register for the regular channel"]
401 #[inline(always)]
402 pub const fn dfsdm_flt0rdatar(&self) -> &DfsdmFlt0rdatar {
403 &self.dfsdm_flt0rdatar
404 }
405 #[doc = "0x120 - analog watchdog high threshold register"]
406 #[inline(always)]
407 pub const fn dfsdm_flt0awhtr(&self) -> &DfsdmFlt0awhtr {
408 &self.dfsdm_flt0awhtr
409 }
410 #[doc = "0x124 - analog watchdog low threshold register"]
411 #[inline(always)]
412 pub const fn dfsdm_flt0awltr(&self) -> &DfsdmFlt0awltr {
413 &self.dfsdm_flt0awltr
414 }
415 #[doc = "0x128 - analog watchdog status register"]
416 #[inline(always)]
417 pub const fn dfsdm_flt0awsr(&self) -> &DfsdmFlt0awsr {
418 &self.dfsdm_flt0awsr
419 }
420 #[doc = "0x12c - analog watchdog clear flag register"]
421 #[inline(always)]
422 pub const fn dfsdm_flt0awcfr(&self) -> &DfsdmFlt0awcfr {
423 &self.dfsdm_flt0awcfr
424 }
425 #[doc = "0x130 - Extremes detector maximum register"]
426 #[inline(always)]
427 pub const fn dfsdm_flt0exmax(&self) -> &DfsdmFlt0exmax {
428 &self.dfsdm_flt0exmax
429 }
430 #[doc = "0x134 - Extremes detector minimum register"]
431 #[inline(always)]
432 pub const fn dfsdm_flt0exmin(&self) -> &DfsdmFlt0exmin {
433 &self.dfsdm_flt0exmin
434 }
435 #[doc = "0x138 - conversion timer register"]
436 #[inline(always)]
437 pub const fn dfsdm_flt0cnvtimr(&self) -> &DfsdmFlt0cnvtimr {
438 &self.dfsdm_flt0cnvtimr
439 }
440 #[doc = "0x180 - control register 1"]
441 #[inline(always)]
442 pub const fn dfsdm_flt1cr1(&self) -> &DfsdmFlt1cr1 {
443 &self.dfsdm_flt1cr1
444 }
445 #[doc = "0x184 - control register 2"]
446 #[inline(always)]
447 pub const fn dfsdm_flt1cr2(&self) -> &DfsdmFlt1cr2 {
448 &self.dfsdm_flt1cr2
449 }
450 #[doc = "0x188 - interrupt and status register"]
451 #[inline(always)]
452 pub const fn dfsdm_flt1isr(&self) -> &DfsdmFlt1isr {
453 &self.dfsdm_flt1isr
454 }
455 #[doc = "0x18c - interrupt flag clear register"]
456 #[inline(always)]
457 pub const fn dfsdm_flt1icr(&self) -> &DfsdmFlt1icr {
458 &self.dfsdm_flt1icr
459 }
460 #[doc = "0x190 - injected channel group selection register"]
461 #[inline(always)]
462 pub const fn dfsdm_flt1chgr(&self) -> &DfsdmFlt1chgr {
463 &self.dfsdm_flt1chgr
464 }
465 #[doc = "0x194 - filter control register"]
466 #[inline(always)]
467 pub const fn dfsdm_flt1fcr(&self) -> &DfsdmFlt1fcr {
468 &self.dfsdm_flt1fcr
469 }
470 #[doc = "0x198 - data register for injected group"]
471 #[inline(always)]
472 pub const fn dfsdm_flt1jdatar(&self) -> &DfsdmFlt1jdatar {
473 &self.dfsdm_flt1jdatar
474 }
475 #[doc = "0x19c - data register for the regular channel"]
476 #[inline(always)]
477 pub const fn dfsdm_flt1rdatar(&self) -> &DfsdmFlt1rdatar {
478 &self.dfsdm_flt1rdatar
479 }
480 #[doc = "0x1a0 - analog watchdog high threshold register"]
481 #[inline(always)]
482 pub const fn dfsdm_flt1awhtr(&self) -> &DfsdmFlt1awhtr {
483 &self.dfsdm_flt1awhtr
484 }
485 #[doc = "0x1a4 - analog watchdog low threshold register"]
486 #[inline(always)]
487 pub const fn dfsdm_flt1awltr(&self) -> &DfsdmFlt1awltr {
488 &self.dfsdm_flt1awltr
489 }
490 #[doc = "0x1a8 - analog watchdog status register"]
491 #[inline(always)]
492 pub const fn dfsdm_flt1awsr(&self) -> &DfsdmFlt1awsr {
493 &self.dfsdm_flt1awsr
494 }
495 #[doc = "0x1ac - analog watchdog clear flag register"]
496 #[inline(always)]
497 pub const fn dfsdm_flt1awcfr(&self) -> &DfsdmFlt1awcfr {
498 &self.dfsdm_flt1awcfr
499 }
500 #[doc = "0x1b0 - Extremes detector maximum register"]
501 #[inline(always)]
502 pub const fn dfsdm_flt1exmax(&self) -> &DfsdmFlt1exmax {
503 &self.dfsdm_flt1exmax
504 }
505 #[doc = "0x1b4 - Extremes detector minimum register"]
506 #[inline(always)]
507 pub const fn dfsdm_flt1exmin(&self) -> &DfsdmFlt1exmin {
508 &self.dfsdm_flt1exmin
509 }
510 #[doc = "0x1b8 - conversion timer register"]
511 #[inline(always)]
512 pub const fn dfsdm_flt1cnvtimr(&self) -> &DfsdmFlt1cnvtimr {
513 &self.dfsdm_flt1cnvtimr
514 }
515 #[doc = "0x200 - control register 1"]
516 #[inline(always)]
517 pub const fn dfsdm_flt2cr1(&self) -> &DfsdmFlt2cr1 {
518 &self.dfsdm_flt2cr1
519 }
520 #[doc = "0x204 - control register 2"]
521 #[inline(always)]
522 pub const fn dfsdm_flt2cr2(&self) -> &DfsdmFlt2cr2 {
523 &self.dfsdm_flt2cr2
524 }
525 #[doc = "0x208 - interrupt and status register"]
526 #[inline(always)]
527 pub const fn dfsdm_flt2isr(&self) -> &DfsdmFlt2isr {
528 &self.dfsdm_flt2isr
529 }
530 #[doc = "0x20c - interrupt flag clear register"]
531 #[inline(always)]
532 pub const fn dfsdm_flt2icr(&self) -> &DfsdmFlt2icr {
533 &self.dfsdm_flt2icr
534 }
535 #[doc = "0x210 - injected channel group selection register"]
536 #[inline(always)]
537 pub const fn dfsdm_flt2jchgr(&self) -> &DfsdmFlt2jchgr {
538 &self.dfsdm_flt2jchgr
539 }
540 #[doc = "0x214 - filter control register"]
541 #[inline(always)]
542 pub const fn dfsdm_flt2fcr(&self) -> &DfsdmFlt2fcr {
543 &self.dfsdm_flt2fcr
544 }
545 #[doc = "0x218 - data register for injected group"]
546 #[inline(always)]
547 pub const fn dfsdm_flt2jdatar(&self) -> &DfsdmFlt2jdatar {
548 &self.dfsdm_flt2jdatar
549 }
550 #[doc = "0x21c - data register for the regular channel"]
551 #[inline(always)]
552 pub const fn dfsdm_flt2rdatar(&self) -> &DfsdmFlt2rdatar {
553 &self.dfsdm_flt2rdatar
554 }
555 #[doc = "0x220 - analog watchdog high threshold register"]
556 #[inline(always)]
557 pub const fn dfsdm_flt2awhtr(&self) -> &DfsdmFlt2awhtr {
558 &self.dfsdm_flt2awhtr
559 }
560 #[doc = "0x224 - analog watchdog low threshold register"]
561 #[inline(always)]
562 pub const fn dfsdm_flt2awltr(&self) -> &DfsdmFlt2awltr {
563 &self.dfsdm_flt2awltr
564 }
565 #[doc = "0x228 - analog watchdog status register"]
566 #[inline(always)]
567 pub const fn dfsdm_flt2awsr(&self) -> &DfsdmFlt2awsr {
568 &self.dfsdm_flt2awsr
569 }
570 #[doc = "0x22c - analog watchdog clear flag register"]
571 #[inline(always)]
572 pub const fn dfsdm_flt2awcfr(&self) -> &DfsdmFlt2awcfr {
573 &self.dfsdm_flt2awcfr
574 }
575 #[doc = "0x230 - Extremes detector maximum register"]
576 #[inline(always)]
577 pub const fn dfsdm_flt2exmax(&self) -> &DfsdmFlt2exmax {
578 &self.dfsdm_flt2exmax
579 }
580 #[doc = "0x234 - Extremes detector minimum register"]
581 #[inline(always)]
582 pub const fn dfsdm_flt2exmin(&self) -> &DfsdmFlt2exmin {
583 &self.dfsdm_flt2exmin
584 }
585 #[doc = "0x238 - conversion timer register"]
586 #[inline(always)]
587 pub const fn dfsdm_flt2cnvtimr(&self) -> &DfsdmFlt2cnvtimr {
588 &self.dfsdm_flt2cnvtimr
589 }
590 #[doc = "0x280 - control register 1"]
591 #[inline(always)]
592 pub const fn dfsdm_flt3cr1(&self) -> &DfsdmFlt3cr1 {
593 &self.dfsdm_flt3cr1
594 }
595 #[doc = "0x284 - control register 2"]
596 #[inline(always)]
597 pub const fn dfsdm_flt3cr2(&self) -> &DfsdmFlt3cr2 {
598 &self.dfsdm_flt3cr2
599 }
600 #[doc = "0x288 - interrupt and status register"]
601 #[inline(always)]
602 pub const fn dfsdm_flt3isr(&self) -> &DfsdmFlt3isr {
603 &self.dfsdm_flt3isr
604 }
605 #[doc = "0x28c - interrupt flag clear register"]
606 #[inline(always)]
607 pub const fn dfsdm_flt3icr(&self) -> &DfsdmFlt3icr {
608 &self.dfsdm_flt3icr
609 }
610 #[doc = "0x290 - injected channel group selection register"]
611 #[inline(always)]
612 pub const fn dfsdm_flt3jchgr(&self) -> &DfsdmFlt3jchgr {
613 &self.dfsdm_flt3jchgr
614 }
615 #[doc = "0x294 - filter control register"]
616 #[inline(always)]
617 pub const fn dfsdm_flt3fcr(&self) -> &DfsdmFlt3fcr {
618 &self.dfsdm_flt3fcr
619 }
620 #[doc = "0x298 - data register for injected group"]
621 #[inline(always)]
622 pub const fn dfsdm_flt3jdatar(&self) -> &DfsdmFlt3jdatar {
623 &self.dfsdm_flt3jdatar
624 }
625 #[doc = "0x29c - data register for the regular channel"]
626 #[inline(always)]
627 pub const fn dfsdm_flt3rdatar(&self) -> &DfsdmFlt3rdatar {
628 &self.dfsdm_flt3rdatar
629 }
630 #[doc = "0x2a0 - analog watchdog high threshold register"]
631 #[inline(always)]
632 pub const fn dfsdm_flt3awhtr(&self) -> &DfsdmFlt3awhtr {
633 &self.dfsdm_flt3awhtr
634 }
635 #[doc = "0x2a4 - analog watchdog low threshold register"]
636 #[inline(always)]
637 pub const fn dfsdm_flt3awltr(&self) -> &DfsdmFlt3awltr {
638 &self.dfsdm_flt3awltr
639 }
640 #[doc = "0x2a8 - analog watchdog status register"]
641 #[inline(always)]
642 pub const fn dfsdm_flt3awsr(&self) -> &DfsdmFlt3awsr {
643 &self.dfsdm_flt3awsr
644 }
645 #[doc = "0x2ac - analog watchdog clear flag register"]
646 #[inline(always)]
647 pub const fn dfsdm_flt3awcfr(&self) -> &DfsdmFlt3awcfr {
648 &self.dfsdm_flt3awcfr
649 }
650 #[doc = "0x2b0 - Extremes detector maximum register"]
651 #[inline(always)]
652 pub const fn dfsdm_flt3exmax(&self) -> &DfsdmFlt3exmax {
653 &self.dfsdm_flt3exmax
654 }
655 #[doc = "0x2b4 - Extremes detector minimum register"]
656 #[inline(always)]
657 pub const fn dfsdm_flt3exmin(&self) -> &DfsdmFlt3exmin {
658 &self.dfsdm_flt3exmin
659 }
660 #[doc = "0x2b8 - conversion timer register"]
661 #[inline(always)]
662 pub const fn dfsdm_flt3cnvtimr(&self) -> &DfsdmFlt3cnvtimr {
663 &self.dfsdm_flt3cnvtimr
664 }
665}
666#[doc = "CH0CFGR1 (rw) register accessor: channel configuration y register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0cfgr1`] module"]
667#[doc(alias = "CH0CFGR1")]
668pub type Ch0cfgr1 = crate::Reg<ch0cfgr1::Ch0cfgr1Spec>;
669#[doc = "channel configuration y register"]
670pub mod ch0cfgr1;
671#[doc = "CH0CFGR2 (rw) register accessor: channel configuration y register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0cfgr2`] module"]
672#[doc(alias = "CH0CFGR2")]
673pub type Ch0cfgr2 = crate::Reg<ch0cfgr2::Ch0cfgr2Spec>;
674#[doc = "channel configuration y register"]
675pub mod ch0cfgr2;
676#[doc = "CH0AWSCDR (rw) register accessor: analog watchdog and short-circuit detector register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0awscdr`] module"]
677#[doc(alias = "CH0AWSCDR")]
678pub type Ch0awscdr = crate::Reg<ch0awscdr::Ch0awscdrSpec>;
679#[doc = "analog watchdog and short-circuit detector register"]
680pub mod ch0awscdr;
681#[doc = "CH0WDATR (rw) register accessor: channel watchdog filter data register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0wdatr`] module"]
682#[doc(alias = "CH0WDATR")]
683pub type Ch0wdatr = crate::Reg<ch0wdatr::Ch0wdatrSpec>;
684#[doc = "channel watchdog filter data register"]
685pub mod ch0wdatr;
686#[doc = "CH0DATINR (rw) register accessor: channel data input register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0datinr`] module"]
687#[doc(alias = "CH0DATINR")]
688pub type Ch0datinr = crate::Reg<ch0datinr::Ch0datinrSpec>;
689#[doc = "channel data input register"]
690pub mod ch0datinr;
691#[doc = "CH0DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch0dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0dlyr`] module"]
692#[doc(alias = "CH0DLYR")]
693pub type Ch0dlyr = crate::Reg<ch0dlyr::Ch0dlyrSpec>;
694#[doc = "channel y delay register"]
695pub mod ch0dlyr;
696#[doc = "CH1CFGR1 (rw) register accessor: CH1CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1cfgr1`] module"]
697#[doc(alias = "CH1CFGR1")]
698pub type Ch1cfgr1 = crate::Reg<ch1cfgr1::Ch1cfgr1Spec>;
699#[doc = "CH1CFGR1"]
700pub mod ch1cfgr1;
701#[doc = "CH1CFGR2 (rw) register accessor: CH1CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1cfgr2`] module"]
702#[doc(alias = "CH1CFGR2")]
703pub type Ch1cfgr2 = crate::Reg<ch1cfgr2::Ch1cfgr2Spec>;
704#[doc = "CH1CFGR2"]
705pub mod ch1cfgr2;
706#[doc = "CH1AWSCDR (rw) register accessor: CH1AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1awscdr`] module"]
707#[doc(alias = "CH1AWSCDR")]
708pub type Ch1awscdr = crate::Reg<ch1awscdr::Ch1awscdrSpec>;
709#[doc = "CH1AWSCDR"]
710pub mod ch1awscdr;
711#[doc = "CH1WDATR (rw) register accessor: CH1WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1wdatr`] module"]
712#[doc(alias = "CH1WDATR")]
713pub type Ch1wdatr = crate::Reg<ch1wdatr::Ch1wdatrSpec>;
714#[doc = "CH1WDATR"]
715pub mod ch1wdatr;
716#[doc = "CH1DATINR (rw) register accessor: CH1DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1datinr`] module"]
717#[doc(alias = "CH1DATINR")]
718pub type Ch1datinr = crate::Reg<ch1datinr::Ch1datinrSpec>;
719#[doc = "CH1DATINR"]
720pub mod ch1datinr;
721#[doc = "CH1DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch1dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1dlyr`] module"]
722#[doc(alias = "CH1DLYR")]
723pub type Ch1dlyr = crate::Reg<ch1dlyr::Ch1dlyrSpec>;
724#[doc = "channel y delay register"]
725pub mod ch1dlyr;
726#[doc = "CH2CFGR1 (rw) register accessor: CH2CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2cfgr1`] module"]
727#[doc(alias = "CH2CFGR1")]
728pub type Ch2cfgr1 = crate::Reg<ch2cfgr1::Ch2cfgr1Spec>;
729#[doc = "CH2CFGR1"]
730pub mod ch2cfgr1;
731#[doc = "CH2CFGR2 (rw) register accessor: CH2CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2cfgr2`] module"]
732#[doc(alias = "CH2CFGR2")]
733pub type Ch2cfgr2 = crate::Reg<ch2cfgr2::Ch2cfgr2Spec>;
734#[doc = "CH2CFGR2"]
735pub mod ch2cfgr2;
736#[doc = "CH2AWSCDR (rw) register accessor: CH2AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2awscdr`] module"]
737#[doc(alias = "CH2AWSCDR")]
738pub type Ch2awscdr = crate::Reg<ch2awscdr::Ch2awscdrSpec>;
739#[doc = "CH2AWSCDR"]
740pub mod ch2awscdr;
741#[doc = "CH2WDATR (rw) register accessor: CH2WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2wdatr`] module"]
742#[doc(alias = "CH2WDATR")]
743pub type Ch2wdatr = crate::Reg<ch2wdatr::Ch2wdatrSpec>;
744#[doc = "CH2WDATR"]
745pub mod ch2wdatr;
746#[doc = "CH2DATINR (rw) register accessor: CH2DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2datinr`] module"]
747#[doc(alias = "CH2DATINR")]
748pub type Ch2datinr = crate::Reg<ch2datinr::Ch2datinrSpec>;
749#[doc = "CH2DATINR"]
750pub mod ch2datinr;
751#[doc = "CH2DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch2dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2dlyr`] module"]
752#[doc(alias = "CH2DLYR")]
753pub type Ch2dlyr = crate::Reg<ch2dlyr::Ch2dlyrSpec>;
754#[doc = "channel y delay register"]
755pub mod ch2dlyr;
756#[doc = "CH3CFGR1 (rw) register accessor: CH3CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3cfgr1`] module"]
757#[doc(alias = "CH3CFGR1")]
758pub type Ch3cfgr1 = crate::Reg<ch3cfgr1::Ch3cfgr1Spec>;
759#[doc = "CH3CFGR1"]
760pub mod ch3cfgr1;
761#[doc = "CH3CFGR2 (rw) register accessor: CH3CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3cfgr2`] module"]
762#[doc(alias = "CH3CFGR2")]
763pub type Ch3cfgr2 = crate::Reg<ch3cfgr2::Ch3cfgr2Spec>;
764#[doc = "CH3CFGR2"]
765pub mod ch3cfgr2;
766#[doc = "CH3AWSCDR (rw) register accessor: CH3AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3awscdr`] module"]
767#[doc(alias = "CH3AWSCDR")]
768pub type Ch3awscdr = crate::Reg<ch3awscdr::Ch3awscdrSpec>;
769#[doc = "CH3AWSCDR"]
770pub mod ch3awscdr;
771#[doc = "CH3WDATR (rw) register accessor: CH3WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3wdatr`] module"]
772#[doc(alias = "CH3WDATR")]
773pub type Ch3wdatr = crate::Reg<ch3wdatr::Ch3wdatrSpec>;
774#[doc = "CH3WDATR"]
775pub mod ch3wdatr;
776#[doc = "CH3DATINR (rw) register accessor: CH3DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3datinr`] module"]
777#[doc(alias = "CH3DATINR")]
778pub type Ch3datinr = crate::Reg<ch3datinr::Ch3datinrSpec>;
779#[doc = "CH3DATINR"]
780pub mod ch3datinr;
781#[doc = "CH3DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch3dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3dlyr`] module"]
782#[doc(alias = "CH3DLYR")]
783pub type Ch3dlyr = crate::Reg<ch3dlyr::Ch3dlyrSpec>;
784#[doc = "channel y delay register"]
785pub mod ch3dlyr;
786#[doc = "CH4CFGR1 (rw) register accessor: CH4CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch4cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4cfgr1`] module"]
787#[doc(alias = "CH4CFGR1")]
788pub type Ch4cfgr1 = crate::Reg<ch4cfgr1::Ch4cfgr1Spec>;
789#[doc = "CH4CFGR1"]
790pub mod ch4cfgr1;
791#[doc = "CH4CFGR2 (rw) register accessor: CH4CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch4cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4cfgr2`] module"]
792#[doc(alias = "CH4CFGR2")]
793pub type Ch4cfgr2 = crate::Reg<ch4cfgr2::Ch4cfgr2Spec>;
794#[doc = "CH4CFGR2"]
795pub mod ch4cfgr2;
796#[doc = "CH4AWSCDR (rw) register accessor: CH4AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch4awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4awscdr`] module"]
797#[doc(alias = "CH4AWSCDR")]
798pub type Ch4awscdr = crate::Reg<ch4awscdr::Ch4awscdrSpec>;
799#[doc = "CH4AWSCDR"]
800pub mod ch4awscdr;
801#[doc = "CH4WDATR (rw) register accessor: CH4WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch4wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4wdatr`] module"]
802#[doc(alias = "CH4WDATR")]
803pub type Ch4wdatr = crate::Reg<ch4wdatr::Ch4wdatrSpec>;
804#[doc = "CH4WDATR"]
805pub mod ch4wdatr;
806#[doc = "CH4DATINR (rw) register accessor: CH4DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch4datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4datinr`] module"]
807#[doc(alias = "CH4DATINR")]
808pub type Ch4datinr = crate::Reg<ch4datinr::Ch4datinrSpec>;
809#[doc = "CH4DATINR"]
810pub mod ch4datinr;
811#[doc = "CH4DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch4dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4dlyr`] module"]
812#[doc(alias = "CH4DLYR")]
813pub type Ch4dlyr = crate::Reg<ch4dlyr::Ch4dlyrSpec>;
814#[doc = "channel y delay register"]
815pub mod ch4dlyr;
816#[doc = "CH5CFGR1 (rw) register accessor: CH5CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch5cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5cfgr1`] module"]
817#[doc(alias = "CH5CFGR1")]
818pub type Ch5cfgr1 = crate::Reg<ch5cfgr1::Ch5cfgr1Spec>;
819#[doc = "CH5CFGR1"]
820pub mod ch5cfgr1;
821#[doc = "CH5CFGR2 (rw) register accessor: CH5CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch5cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5cfgr2`] module"]
822#[doc(alias = "CH5CFGR2")]
823pub type Ch5cfgr2 = crate::Reg<ch5cfgr2::Ch5cfgr2Spec>;
824#[doc = "CH5CFGR2"]
825pub mod ch5cfgr2;
826#[doc = "CH5AWSCDR (rw) register accessor: CH5AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch5awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5awscdr`] module"]
827#[doc(alias = "CH5AWSCDR")]
828pub type Ch5awscdr = crate::Reg<ch5awscdr::Ch5awscdrSpec>;
829#[doc = "CH5AWSCDR"]
830pub mod ch5awscdr;
831#[doc = "CH5WDATR (rw) register accessor: CH5WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch5wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5wdatr`] module"]
832#[doc(alias = "CH5WDATR")]
833pub type Ch5wdatr = crate::Reg<ch5wdatr::Ch5wdatrSpec>;
834#[doc = "CH5WDATR"]
835pub mod ch5wdatr;
836#[doc = "CH5DATINR (rw) register accessor: CH5DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch5datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5datinr`] module"]
837#[doc(alias = "CH5DATINR")]
838pub type Ch5datinr = crate::Reg<ch5datinr::Ch5datinrSpec>;
839#[doc = "CH5DATINR"]
840pub mod ch5datinr;
841#[doc = "CH5DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch5dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5dlyr`] module"]
842#[doc(alias = "CH5DLYR")]
843pub type Ch5dlyr = crate::Reg<ch5dlyr::Ch5dlyrSpec>;
844#[doc = "channel y delay register"]
845pub mod ch5dlyr;
846#[doc = "CH6CFGR1 (rw) register accessor: CH6CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch6cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6cfgr1`] module"]
847#[doc(alias = "CH6CFGR1")]
848pub type Ch6cfgr1 = crate::Reg<ch6cfgr1::Ch6cfgr1Spec>;
849#[doc = "CH6CFGR1"]
850pub mod ch6cfgr1;
851#[doc = "CH6CFGR2 (rw) register accessor: CH6CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch6cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6cfgr2`] module"]
852#[doc(alias = "CH6CFGR2")]
853pub type Ch6cfgr2 = crate::Reg<ch6cfgr2::Ch6cfgr2Spec>;
854#[doc = "CH6CFGR2"]
855pub mod ch6cfgr2;
856#[doc = "CH6AWSCDR (rw) register accessor: CH6AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch6awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6awscdr`] module"]
857#[doc(alias = "CH6AWSCDR")]
858pub type Ch6awscdr = crate::Reg<ch6awscdr::Ch6awscdrSpec>;
859#[doc = "CH6AWSCDR"]
860pub mod ch6awscdr;
861#[doc = "CH6WDATR (rw) register accessor: CH6WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch6wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6wdatr`] module"]
862#[doc(alias = "CH6WDATR")]
863pub type Ch6wdatr = crate::Reg<ch6wdatr::Ch6wdatrSpec>;
864#[doc = "CH6WDATR"]
865pub mod ch6wdatr;
866#[doc = "CH6DATINR (rw) register accessor: CH6DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch6datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6datinr`] module"]
867#[doc(alias = "CH6DATINR")]
868pub type Ch6datinr = crate::Reg<ch6datinr::Ch6datinrSpec>;
869#[doc = "CH6DATINR"]
870pub mod ch6datinr;
871#[doc = "CH6DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch6dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6dlyr`] module"]
872#[doc(alias = "CH6DLYR")]
873pub type Ch6dlyr = crate::Reg<ch6dlyr::Ch6dlyrSpec>;
874#[doc = "channel y delay register"]
875pub mod ch6dlyr;
876#[doc = "CH7CFGR1 (rw) register accessor: CH7CFGR1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch7cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7cfgr1`] module"]
877#[doc(alias = "CH7CFGR1")]
878pub type Ch7cfgr1 = crate::Reg<ch7cfgr1::Ch7cfgr1Spec>;
879#[doc = "CH7CFGR1"]
880pub mod ch7cfgr1;
881#[doc = "CH7CFGR2 (rw) register accessor: CH7CFGR2\n\nYou can [`read`](crate::Reg::read) this register and get [`ch7cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7cfgr2`] module"]
882#[doc(alias = "CH7CFGR2")]
883pub type Ch7cfgr2 = crate::Reg<ch7cfgr2::Ch7cfgr2Spec>;
884#[doc = "CH7CFGR2"]
885pub mod ch7cfgr2;
886#[doc = "CH7AWSCDR (rw) register accessor: CH7AWSCDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch7awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7awscdr`] module"]
887#[doc(alias = "CH7AWSCDR")]
888pub type Ch7awscdr = crate::Reg<ch7awscdr::Ch7awscdrSpec>;
889#[doc = "CH7AWSCDR"]
890pub mod ch7awscdr;
891#[doc = "CH7WDATR (rw) register accessor: CH7WDATR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch7wdatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7wdatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7wdatr`] module"]
892#[doc(alias = "CH7WDATR")]
893pub type Ch7wdatr = crate::Reg<ch7wdatr::Ch7wdatrSpec>;
894#[doc = "CH7WDATR"]
895pub mod ch7wdatr;
896#[doc = "CH7DATINR (rw) register accessor: CH7DATINR\n\nYou can [`read`](crate::Reg::read) this register and get [`ch7datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7datinr`] module"]
897#[doc(alias = "CH7DATINR")]
898pub type Ch7datinr = crate::Reg<ch7datinr::Ch7datinrSpec>;
899#[doc = "CH7DATINR"]
900pub mod ch7datinr;
901#[doc = "CH7DLYR (rw) register accessor: channel y delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch7dlyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7dlyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7dlyr`] module"]
902#[doc(alias = "CH7DLYR")]
903pub type Ch7dlyr = crate::Reg<ch7dlyr::Ch7dlyrSpec>;
904#[doc = "channel y delay register"]
905pub mod ch7dlyr;
906#[doc = "DFSDM_FLT0CR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0cr1`] module"]
907#[doc(alias = "DFSDM_FLT0CR1")]
908pub type DfsdmFlt0cr1 = crate::Reg<dfsdm_flt0cr1::DfsdmFlt0cr1Spec>;
909#[doc = "control register 1"]
910pub mod dfsdm_flt0cr1;
911#[doc = "DFSDM_FLT0CR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0cr2`] module"]
912#[doc(alias = "DFSDM_FLT0CR2")]
913pub type DfsdmFlt0cr2 = crate::Reg<dfsdm_flt0cr2::DfsdmFlt0cr2Spec>;
914#[doc = "control register 2"]
915pub mod dfsdm_flt0cr2;
916#[doc = "DFSDM_FLT0ISR (r) register accessor: interrupt and status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0isr`] module"]
917#[doc(alias = "DFSDM_FLT0ISR")]
918pub type DfsdmFlt0isr = crate::Reg<dfsdm_flt0isr::DfsdmFlt0isrSpec>;
919#[doc = "interrupt and status register"]
920pub mod dfsdm_flt0isr;
921#[doc = "DFSDM_FLT0ICR (rw) register accessor: interrupt flag clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0icr`] module"]
922#[doc(alias = "DFSDM_FLT0ICR")]
923pub type DfsdmFlt0icr = crate::Reg<dfsdm_flt0icr::DfsdmFlt0icrSpec>;
924#[doc = "interrupt flag clear register"]
925pub mod dfsdm_flt0icr;
926#[doc = "DFSDM_FLT0JCHGR (rw) register accessor: injected channel group selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0jchgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0jchgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0jchgr`] module"]
927#[doc(alias = "DFSDM_FLT0JCHGR")]
928pub type DfsdmFlt0jchgr = crate::Reg<dfsdm_flt0jchgr::DfsdmFlt0jchgrSpec>;
929#[doc = "injected channel group selection register"]
930pub mod dfsdm_flt0jchgr;
931#[doc = "DFSDM_FLT0FCR (rw) register accessor: filter control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0fcr`] module"]
932#[doc(alias = "DFSDM_FLT0FCR")]
933pub type DfsdmFlt0fcr = crate::Reg<dfsdm_flt0fcr::DfsdmFlt0fcrSpec>;
934#[doc = "filter control register"]
935pub mod dfsdm_flt0fcr;
936#[doc = "DFSDM_FLT0JDATAR (r) register accessor: data register for injected group\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0jdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0jdatar`] module"]
937#[doc(alias = "DFSDM_FLT0JDATAR")]
938pub type DfsdmFlt0jdatar = crate::Reg<dfsdm_flt0jdatar::DfsdmFlt0jdatarSpec>;
939#[doc = "data register for injected group"]
940pub mod dfsdm_flt0jdatar;
941#[doc = "DFSDM_FLT0RDATAR (r) register accessor: data register for the regular channel\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0rdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0rdatar`] module"]
942#[doc(alias = "DFSDM_FLT0RDATAR")]
943pub type DfsdmFlt0rdatar = crate::Reg<dfsdm_flt0rdatar::DfsdmFlt0rdatarSpec>;
944#[doc = "data register for the regular channel"]
945pub mod dfsdm_flt0rdatar;
946#[doc = "DFSDM_FLT0AWHTR (rw) register accessor: analog watchdog high threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0awhtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0awhtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0awhtr`] module"]
947#[doc(alias = "DFSDM_FLT0AWHTR")]
948pub type DfsdmFlt0awhtr = crate::Reg<dfsdm_flt0awhtr::DfsdmFlt0awhtrSpec>;
949#[doc = "analog watchdog high threshold register"]
950pub mod dfsdm_flt0awhtr;
951#[doc = "DFSDM_FLT0AWLTR (rw) register accessor: analog watchdog low threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0awltr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0awltr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0awltr`] module"]
952#[doc(alias = "DFSDM_FLT0AWLTR")]
953pub type DfsdmFlt0awltr = crate::Reg<dfsdm_flt0awltr::DfsdmFlt0awltrSpec>;
954#[doc = "analog watchdog low threshold register"]
955pub mod dfsdm_flt0awltr;
956#[doc = "DFSDM_FLT0AWSR (r) register accessor: analog watchdog status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0awsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0awsr`] module"]
957#[doc(alias = "DFSDM_FLT0AWSR")]
958pub type DfsdmFlt0awsr = crate::Reg<dfsdm_flt0awsr::DfsdmFlt0awsrSpec>;
959#[doc = "analog watchdog status register"]
960pub mod dfsdm_flt0awsr;
961#[doc = "DFSDM_FLT0AWCFR (rw) register accessor: analog watchdog clear flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0awcfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0awcfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0awcfr`] module"]
962#[doc(alias = "DFSDM_FLT0AWCFR")]
963pub type DfsdmFlt0awcfr = crate::Reg<dfsdm_flt0awcfr::DfsdmFlt0awcfrSpec>;
964#[doc = "analog watchdog clear flag register"]
965pub mod dfsdm_flt0awcfr;
966#[doc = "DFSDM_FLT0EXMAX (r) register accessor: Extremes detector maximum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0exmax::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0exmax`] module"]
967#[doc(alias = "DFSDM_FLT0EXMAX")]
968pub type DfsdmFlt0exmax = crate::Reg<dfsdm_flt0exmax::DfsdmFlt0exmaxSpec>;
969#[doc = "Extremes detector maximum register"]
970pub mod dfsdm_flt0exmax;
971#[doc = "DFSDM_FLT0EXMIN (r) register accessor: Extremes detector minimum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0exmin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0exmin`] module"]
972#[doc(alias = "DFSDM_FLT0EXMIN")]
973pub type DfsdmFlt0exmin = crate::Reg<dfsdm_flt0exmin::DfsdmFlt0exminSpec>;
974#[doc = "Extremes detector minimum register"]
975pub mod dfsdm_flt0exmin;
976#[doc = "DFSDM_FLT0CNVTIMR (r) register accessor: conversion timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0cnvtimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt0cnvtimr`] module"]
977#[doc(alias = "DFSDM_FLT0CNVTIMR")]
978pub type DfsdmFlt0cnvtimr = crate::Reg<dfsdm_flt0cnvtimr::DfsdmFlt0cnvtimrSpec>;
979#[doc = "conversion timer register"]
980pub mod dfsdm_flt0cnvtimr;
981#[doc = "DFSDM_FLT1CR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1cr1`] module"]
982#[doc(alias = "DFSDM_FLT1CR1")]
983pub type DfsdmFlt1cr1 = crate::Reg<dfsdm_flt1cr1::DfsdmFlt1cr1Spec>;
984#[doc = "control register 1"]
985pub mod dfsdm_flt1cr1;
986#[doc = "DFSDM_FLT1CR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1cr2`] module"]
987#[doc(alias = "DFSDM_FLT1CR2")]
988pub type DfsdmFlt1cr2 = crate::Reg<dfsdm_flt1cr2::DfsdmFlt1cr2Spec>;
989#[doc = "control register 2"]
990pub mod dfsdm_flt1cr2;
991#[doc = "DFSDM_FLT1ISR (r) register accessor: interrupt and status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1isr`] module"]
992#[doc(alias = "DFSDM_FLT1ISR")]
993pub type DfsdmFlt1isr = crate::Reg<dfsdm_flt1isr::DfsdmFlt1isrSpec>;
994#[doc = "interrupt and status register"]
995pub mod dfsdm_flt1isr;
996#[doc = "DFSDM_FLT1ICR (rw) register accessor: interrupt flag clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1icr`] module"]
997#[doc(alias = "DFSDM_FLT1ICR")]
998pub type DfsdmFlt1icr = crate::Reg<dfsdm_flt1icr::DfsdmFlt1icrSpec>;
999#[doc = "interrupt flag clear register"]
1000pub mod dfsdm_flt1icr;
1001#[doc = "DFSDM_FLT1CHGR (rw) register accessor: injected channel group selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1chgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1chgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1chgr`] module"]
1002#[doc(alias = "DFSDM_FLT1CHGR")]
1003pub type DfsdmFlt1chgr = crate::Reg<dfsdm_flt1chgr::DfsdmFlt1chgrSpec>;
1004#[doc = "injected channel group selection register"]
1005pub mod dfsdm_flt1chgr;
1006#[doc = "DFSDM_FLT1FCR (rw) register accessor: filter control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1fcr`] module"]
1007#[doc(alias = "DFSDM_FLT1FCR")]
1008pub type DfsdmFlt1fcr = crate::Reg<dfsdm_flt1fcr::DfsdmFlt1fcrSpec>;
1009#[doc = "filter control register"]
1010pub mod dfsdm_flt1fcr;
1011#[doc = "DFSDM_FLT1JDATAR (r) register accessor: data register for injected group\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1jdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1jdatar`] module"]
1012#[doc(alias = "DFSDM_FLT1JDATAR")]
1013pub type DfsdmFlt1jdatar = crate::Reg<dfsdm_flt1jdatar::DfsdmFlt1jdatarSpec>;
1014#[doc = "data register for injected group"]
1015pub mod dfsdm_flt1jdatar;
1016#[doc = "DFSDM_FLT1RDATAR (r) register accessor: data register for the regular channel\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1rdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1rdatar`] module"]
1017#[doc(alias = "DFSDM_FLT1RDATAR")]
1018pub type DfsdmFlt1rdatar = crate::Reg<dfsdm_flt1rdatar::DfsdmFlt1rdatarSpec>;
1019#[doc = "data register for the regular channel"]
1020pub mod dfsdm_flt1rdatar;
1021#[doc = "DFSDM_FLT1AWHTR (rw) register accessor: analog watchdog high threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1awhtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1awhtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1awhtr`] module"]
1022#[doc(alias = "DFSDM_FLT1AWHTR")]
1023pub type DfsdmFlt1awhtr = crate::Reg<dfsdm_flt1awhtr::DfsdmFlt1awhtrSpec>;
1024#[doc = "analog watchdog high threshold register"]
1025pub mod dfsdm_flt1awhtr;
1026#[doc = "DFSDM_FLT1AWLTR (rw) register accessor: analog watchdog low threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1awltr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1awltr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1awltr`] module"]
1027#[doc(alias = "DFSDM_FLT1AWLTR")]
1028pub type DfsdmFlt1awltr = crate::Reg<dfsdm_flt1awltr::DfsdmFlt1awltrSpec>;
1029#[doc = "analog watchdog low threshold register"]
1030pub mod dfsdm_flt1awltr;
1031#[doc = "DFSDM_FLT1AWSR (r) register accessor: analog watchdog status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1awsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1awsr`] module"]
1032#[doc(alias = "DFSDM_FLT1AWSR")]
1033pub type DfsdmFlt1awsr = crate::Reg<dfsdm_flt1awsr::DfsdmFlt1awsrSpec>;
1034#[doc = "analog watchdog status register"]
1035pub mod dfsdm_flt1awsr;
1036#[doc = "DFSDM_FLT1AWCFR (rw) register accessor: analog watchdog clear flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1awcfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt1awcfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1awcfr`] module"]
1037#[doc(alias = "DFSDM_FLT1AWCFR")]
1038pub type DfsdmFlt1awcfr = crate::Reg<dfsdm_flt1awcfr::DfsdmFlt1awcfrSpec>;
1039#[doc = "analog watchdog clear flag register"]
1040pub mod dfsdm_flt1awcfr;
1041#[doc = "DFSDM_FLT1EXMAX (r) register accessor: Extremes detector maximum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1exmax::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1exmax`] module"]
1042#[doc(alias = "DFSDM_FLT1EXMAX")]
1043pub type DfsdmFlt1exmax = crate::Reg<dfsdm_flt1exmax::DfsdmFlt1exmaxSpec>;
1044#[doc = "Extremes detector maximum register"]
1045pub mod dfsdm_flt1exmax;
1046#[doc = "DFSDM_FLT1EXMIN (r) register accessor: Extremes detector minimum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1exmin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1exmin`] module"]
1047#[doc(alias = "DFSDM_FLT1EXMIN")]
1048pub type DfsdmFlt1exmin = crate::Reg<dfsdm_flt1exmin::DfsdmFlt1exminSpec>;
1049#[doc = "Extremes detector minimum register"]
1050pub mod dfsdm_flt1exmin;
1051#[doc = "DFSDM_FLT1CNVTIMR (r) register accessor: conversion timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt1cnvtimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt1cnvtimr`] module"]
1052#[doc(alias = "DFSDM_FLT1CNVTIMR")]
1053pub type DfsdmFlt1cnvtimr = crate::Reg<dfsdm_flt1cnvtimr::DfsdmFlt1cnvtimrSpec>;
1054#[doc = "conversion timer register"]
1055pub mod dfsdm_flt1cnvtimr;
1056#[doc = "DFSDM_FLT2CR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2cr1`] module"]
1057#[doc(alias = "DFSDM_FLT2CR1")]
1058pub type DfsdmFlt2cr1 = crate::Reg<dfsdm_flt2cr1::DfsdmFlt2cr1Spec>;
1059#[doc = "control register 1"]
1060pub mod dfsdm_flt2cr1;
1061#[doc = "DFSDM_FLT2CR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2cr2`] module"]
1062#[doc(alias = "DFSDM_FLT2CR2")]
1063pub type DfsdmFlt2cr2 = crate::Reg<dfsdm_flt2cr2::DfsdmFlt2cr2Spec>;
1064#[doc = "control register 2"]
1065pub mod dfsdm_flt2cr2;
1066#[doc = "DFSDM_FLT2ISR (r) register accessor: interrupt and status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2isr`] module"]
1067#[doc(alias = "DFSDM_FLT2ISR")]
1068pub type DfsdmFlt2isr = crate::Reg<dfsdm_flt2isr::DfsdmFlt2isrSpec>;
1069#[doc = "interrupt and status register"]
1070pub mod dfsdm_flt2isr;
1071#[doc = "DFSDM_FLT2ICR (rw) register accessor: interrupt flag clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2icr`] module"]
1072#[doc(alias = "DFSDM_FLT2ICR")]
1073pub type DfsdmFlt2icr = crate::Reg<dfsdm_flt2icr::DfsdmFlt2icrSpec>;
1074#[doc = "interrupt flag clear register"]
1075pub mod dfsdm_flt2icr;
1076#[doc = "DFSDM_FLT2JCHGR (rw) register accessor: injected channel group selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2jchgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2jchgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2jchgr`] module"]
1077#[doc(alias = "DFSDM_FLT2JCHGR")]
1078pub type DfsdmFlt2jchgr = crate::Reg<dfsdm_flt2jchgr::DfsdmFlt2jchgrSpec>;
1079#[doc = "injected channel group selection register"]
1080pub mod dfsdm_flt2jchgr;
1081#[doc = "DFSDM_FLT2FCR (rw) register accessor: filter control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2fcr`] module"]
1082#[doc(alias = "DFSDM_FLT2FCR")]
1083pub type DfsdmFlt2fcr = crate::Reg<dfsdm_flt2fcr::DfsdmFlt2fcrSpec>;
1084#[doc = "filter control register"]
1085pub mod dfsdm_flt2fcr;
1086#[doc = "DFSDM_FLT2JDATAR (r) register accessor: data register for injected group\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2jdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2jdatar`] module"]
1087#[doc(alias = "DFSDM_FLT2JDATAR")]
1088pub type DfsdmFlt2jdatar = crate::Reg<dfsdm_flt2jdatar::DfsdmFlt2jdatarSpec>;
1089#[doc = "data register for injected group"]
1090pub mod dfsdm_flt2jdatar;
1091#[doc = "DFSDM_FLT2RDATAR (r) register accessor: data register for the regular channel\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2rdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2rdatar`] module"]
1092#[doc(alias = "DFSDM_FLT2RDATAR")]
1093pub type DfsdmFlt2rdatar = crate::Reg<dfsdm_flt2rdatar::DfsdmFlt2rdatarSpec>;
1094#[doc = "data register for the regular channel"]
1095pub mod dfsdm_flt2rdatar;
1096#[doc = "DFSDM_FLT2AWHTR (rw) register accessor: analog watchdog high threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2awhtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2awhtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2awhtr`] module"]
1097#[doc(alias = "DFSDM_FLT2AWHTR")]
1098pub type DfsdmFlt2awhtr = crate::Reg<dfsdm_flt2awhtr::DfsdmFlt2awhtrSpec>;
1099#[doc = "analog watchdog high threshold register"]
1100pub mod dfsdm_flt2awhtr;
1101#[doc = "DFSDM_FLT2AWLTR (rw) register accessor: analog watchdog low threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2awltr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2awltr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2awltr`] module"]
1102#[doc(alias = "DFSDM_FLT2AWLTR")]
1103pub type DfsdmFlt2awltr = crate::Reg<dfsdm_flt2awltr::DfsdmFlt2awltrSpec>;
1104#[doc = "analog watchdog low threshold register"]
1105pub mod dfsdm_flt2awltr;
1106#[doc = "DFSDM_FLT2AWSR (r) register accessor: analog watchdog status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2awsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2awsr`] module"]
1107#[doc(alias = "DFSDM_FLT2AWSR")]
1108pub type DfsdmFlt2awsr = crate::Reg<dfsdm_flt2awsr::DfsdmFlt2awsrSpec>;
1109#[doc = "analog watchdog status register"]
1110pub mod dfsdm_flt2awsr;
1111#[doc = "DFSDM_FLT2AWCFR (rw) register accessor: analog watchdog clear flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2awcfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt2awcfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2awcfr`] module"]
1112#[doc(alias = "DFSDM_FLT2AWCFR")]
1113pub type DfsdmFlt2awcfr = crate::Reg<dfsdm_flt2awcfr::DfsdmFlt2awcfrSpec>;
1114#[doc = "analog watchdog clear flag register"]
1115pub mod dfsdm_flt2awcfr;
1116#[doc = "DFSDM_FLT2EXMAX (r) register accessor: Extremes detector maximum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2exmax::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2exmax`] module"]
1117#[doc(alias = "DFSDM_FLT2EXMAX")]
1118pub type DfsdmFlt2exmax = crate::Reg<dfsdm_flt2exmax::DfsdmFlt2exmaxSpec>;
1119#[doc = "Extremes detector maximum register"]
1120pub mod dfsdm_flt2exmax;
1121#[doc = "DFSDM_FLT2EXMIN (r) register accessor: Extremes detector minimum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2exmin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2exmin`] module"]
1122#[doc(alias = "DFSDM_FLT2EXMIN")]
1123pub type DfsdmFlt2exmin = crate::Reg<dfsdm_flt2exmin::DfsdmFlt2exminSpec>;
1124#[doc = "Extremes detector minimum register"]
1125pub mod dfsdm_flt2exmin;
1126#[doc = "DFSDM_FLT2CNVTIMR (r) register accessor: conversion timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt2cnvtimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt2cnvtimr`] module"]
1127#[doc(alias = "DFSDM_FLT2CNVTIMR")]
1128pub type DfsdmFlt2cnvtimr = crate::Reg<dfsdm_flt2cnvtimr::DfsdmFlt2cnvtimrSpec>;
1129#[doc = "conversion timer register"]
1130pub mod dfsdm_flt2cnvtimr;
1131#[doc = "DFSDM_FLT3CR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3cr1`] module"]
1132#[doc(alias = "DFSDM_FLT3CR1")]
1133pub type DfsdmFlt3cr1 = crate::Reg<dfsdm_flt3cr1::DfsdmFlt3cr1Spec>;
1134#[doc = "control register 1"]
1135pub mod dfsdm_flt3cr1;
1136#[doc = "DFSDM_FLT3CR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3cr2`] module"]
1137#[doc(alias = "DFSDM_FLT3CR2")]
1138pub type DfsdmFlt3cr2 = crate::Reg<dfsdm_flt3cr2::DfsdmFlt3cr2Spec>;
1139#[doc = "control register 2"]
1140pub mod dfsdm_flt3cr2;
1141#[doc = "DFSDM_FLT3ISR (r) register accessor: interrupt and status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3isr`] module"]
1142#[doc(alias = "DFSDM_FLT3ISR")]
1143pub type DfsdmFlt3isr = crate::Reg<dfsdm_flt3isr::DfsdmFlt3isrSpec>;
1144#[doc = "interrupt and status register"]
1145pub mod dfsdm_flt3isr;
1146#[doc = "DFSDM_FLT3ICR (rw) register accessor: interrupt flag clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3icr`] module"]
1147#[doc(alias = "DFSDM_FLT3ICR")]
1148pub type DfsdmFlt3icr = crate::Reg<dfsdm_flt3icr::DfsdmFlt3icrSpec>;
1149#[doc = "interrupt flag clear register"]
1150pub mod dfsdm_flt3icr;
1151#[doc = "DFSDM_FLT3JCHGR (rw) register accessor: injected channel group selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3jchgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3jchgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3jchgr`] module"]
1152#[doc(alias = "DFSDM_FLT3JCHGR")]
1153pub type DfsdmFlt3jchgr = crate::Reg<dfsdm_flt3jchgr::DfsdmFlt3jchgrSpec>;
1154#[doc = "injected channel group selection register"]
1155pub mod dfsdm_flt3jchgr;
1156#[doc = "DFSDM_FLT3FCR (rw) register accessor: filter control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3fcr`] module"]
1157#[doc(alias = "DFSDM_FLT3FCR")]
1158pub type DfsdmFlt3fcr = crate::Reg<dfsdm_flt3fcr::DfsdmFlt3fcrSpec>;
1159#[doc = "filter control register"]
1160pub mod dfsdm_flt3fcr;
1161#[doc = "DFSDM_FLT3JDATAR (r) register accessor: data register for injected group\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3jdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3jdatar`] module"]
1162#[doc(alias = "DFSDM_FLT3JDATAR")]
1163pub type DfsdmFlt3jdatar = crate::Reg<dfsdm_flt3jdatar::DfsdmFlt3jdatarSpec>;
1164#[doc = "data register for injected group"]
1165pub mod dfsdm_flt3jdatar;
1166#[doc = "DFSDM_FLT3RDATAR (r) register accessor: data register for the regular channel\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3rdatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3rdatar`] module"]
1167#[doc(alias = "DFSDM_FLT3RDATAR")]
1168pub type DfsdmFlt3rdatar = crate::Reg<dfsdm_flt3rdatar::DfsdmFlt3rdatarSpec>;
1169#[doc = "data register for the regular channel"]
1170pub mod dfsdm_flt3rdatar;
1171#[doc = "DFSDM_FLT3AWHTR (rw) register accessor: analog watchdog high threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3awhtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3awhtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3awhtr`] module"]
1172#[doc(alias = "DFSDM_FLT3AWHTR")]
1173pub type DfsdmFlt3awhtr = crate::Reg<dfsdm_flt3awhtr::DfsdmFlt3awhtrSpec>;
1174#[doc = "analog watchdog high threshold register"]
1175pub mod dfsdm_flt3awhtr;
1176#[doc = "DFSDM_FLT3AWLTR (rw) register accessor: analog watchdog low threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3awltr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3awltr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3awltr`] module"]
1177#[doc(alias = "DFSDM_FLT3AWLTR")]
1178pub type DfsdmFlt3awltr = crate::Reg<dfsdm_flt3awltr::DfsdmFlt3awltrSpec>;
1179#[doc = "analog watchdog low threshold register"]
1180pub mod dfsdm_flt3awltr;
1181#[doc = "DFSDM_FLT3AWSR (r) register accessor: analog watchdog status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3awsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3awsr`] module"]
1182#[doc(alias = "DFSDM_FLT3AWSR")]
1183pub type DfsdmFlt3awsr = crate::Reg<dfsdm_flt3awsr::DfsdmFlt3awsrSpec>;
1184#[doc = "analog watchdog status register"]
1185pub mod dfsdm_flt3awsr;
1186#[doc = "DFSDM_FLT3AWCFR (rw) register accessor: analog watchdog clear flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3awcfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt3awcfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3awcfr`] module"]
1187#[doc(alias = "DFSDM_FLT3AWCFR")]
1188pub type DfsdmFlt3awcfr = crate::Reg<dfsdm_flt3awcfr::DfsdmFlt3awcfrSpec>;
1189#[doc = "analog watchdog clear flag register"]
1190pub mod dfsdm_flt3awcfr;
1191#[doc = "DFSDM_FLT3EXMAX (r) register accessor: Extremes detector maximum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3exmax::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3exmax`] module"]
1192#[doc(alias = "DFSDM_FLT3EXMAX")]
1193pub type DfsdmFlt3exmax = crate::Reg<dfsdm_flt3exmax::DfsdmFlt3exmaxSpec>;
1194#[doc = "Extremes detector maximum register"]
1195pub mod dfsdm_flt3exmax;
1196#[doc = "DFSDM_FLT3EXMIN (r) register accessor: Extremes detector minimum register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3exmin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3exmin`] module"]
1197#[doc(alias = "DFSDM_FLT3EXMIN")]
1198pub type DfsdmFlt3exmin = crate::Reg<dfsdm_flt3exmin::DfsdmFlt3exminSpec>;
1199#[doc = "Extremes detector minimum register"]
1200pub mod dfsdm_flt3exmin;
1201#[doc = "DFSDM_FLT3CNVTIMR (r) register accessor: conversion timer register\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt3cnvtimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dfsdm_flt3cnvtimr`] module"]
1202#[doc(alias = "DFSDM_FLT3CNVTIMR")]
1203pub type DfsdmFlt3cnvtimr = crate::Reg<dfsdm_flt3cnvtimr::DfsdmFlt3cnvtimrSpec>;
1204#[doc = "conversion timer register"]
1205pub mod dfsdm_flt3cnvtimr;