1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR2 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `RTOEN`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum RTOENR {
48 #[doc = "Receiver timeout feature disabled"]
49 DISABLED,
50 #[doc = "Receiver timeout feature enabled"]
51 ENABLED,
52}
53impl RTOENR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 RTOENR::DISABLED => false,
69 RTOENR::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> RTOENR {
76 match value {
77 false => RTOENR::DISABLED,
78 true => RTOENR::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == RTOENR::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == RTOENR::ENABLED
90 }
91}
92#[doc = "Possible values of the field `ABREN`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum ABRENR {
95 #[doc = "Auto baud rate detection is disabled"]
96 DISABLED,
97 #[doc = "Auto baud rate detection is enabled"]
98 ENABLED,
99}
100impl ABRENR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 ABRENR::DISABLED => false,
116 ABRENR::ENABLED => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> ABRENR {
123 match value {
124 false => ABRENR::DISABLED,
125 true => ABRENR::ENABLED,
126 }
127 }
128 #[doc = "Checks if the value of the field is `DISABLED`"]
129 #[inline]
130 pub fn is_disabled(&self) -> bool {
131 *self == ABRENR::DISABLED
132 }
133 #[doc = "Checks if the value of the field is `ENABLED`"]
134 #[inline]
135 pub fn is_enabled(&self) -> bool {
136 *self == ABRENR::ENABLED
137 }
138}
139#[doc = "Possible values of the field `MSBFIRST`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum MSBFIRSTR {
142 #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
143 LSB,
144 #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
145 MSB,
146}
147impl MSBFIRSTR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 MSBFIRSTR::LSB => false,
163 MSBFIRSTR::MSB => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> MSBFIRSTR {
170 match value {
171 false => MSBFIRSTR::LSB,
172 true => MSBFIRSTR::MSB,
173 }
174 }
175 #[doc = "Checks if the value of the field is `LSB`"]
176 #[inline]
177 pub fn is_lsb(&self) -> bool {
178 *self == MSBFIRSTR::LSB
179 }
180 #[doc = "Checks if the value of the field is `MSB`"]
181 #[inline]
182 pub fn is_msb(&self) -> bool {
183 *self == MSBFIRSTR::MSB
184 }
185}
186#[doc = "Possible values of the field `DATAINV`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum DATAINVR {
189 #[doc = "Logical data from the data register are send/received in positive/direct logic"]
190 POSITIVE,
191 #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
192 NEGATIVE,
193}
194impl DATAINVR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 DATAINVR::POSITIVE => false,
210 DATAINVR::NEGATIVE => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> DATAINVR {
217 match value {
218 false => DATAINVR::POSITIVE,
219 true => DATAINVR::NEGATIVE,
220 }
221 }
222 #[doc = "Checks if the value of the field is `POSITIVE`"]
223 #[inline]
224 pub fn is_positive(&self) -> bool {
225 *self == DATAINVR::POSITIVE
226 }
227 #[doc = "Checks if the value of the field is `NEGATIVE`"]
228 #[inline]
229 pub fn is_negative(&self) -> bool {
230 *self == DATAINVR::NEGATIVE
231 }
232}
233#[doc = "Possible values of the field `TXINV`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum TXINVR {
236 #[doc = "TX pin signal works using the standard logic levels"]
237 STANDARD,
238 #[doc = "TX pin signal values are inverted"]
239 INVERTED,
240}
241impl TXINVR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 TXINVR::STANDARD => false,
257 TXINVR::INVERTED => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> TXINVR {
264 match value {
265 false => TXINVR::STANDARD,
266 true => TXINVR::INVERTED,
267 }
268 }
269 #[doc = "Checks if the value of the field is `STANDARD`"]
270 #[inline]
271 pub fn is_standard(&self) -> bool {
272 *self == TXINVR::STANDARD
273 }
274 #[doc = "Checks if the value of the field is `INVERTED`"]
275 #[inline]
276 pub fn is_inverted(&self) -> bool {
277 *self == TXINVR::INVERTED
278 }
279}
280#[doc = "Possible values of the field `RXINV`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum RXINVR {
283 #[doc = "RX pin signal works using the standard logic levels"]
284 STANDARD,
285 #[doc = "RX pin signal values are inverted"]
286 INVERTED,
287}
288impl RXINVR {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 RXINVR::STANDARD => false,
304 RXINVR::INVERTED => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> RXINVR {
311 match value {
312 false => RXINVR::STANDARD,
313 true => RXINVR::INVERTED,
314 }
315 }
316 #[doc = "Checks if the value of the field is `STANDARD`"]
317 #[inline]
318 pub fn is_standard(&self) -> bool {
319 *self == RXINVR::STANDARD
320 }
321 #[doc = "Checks if the value of the field is `INVERTED`"]
322 #[inline]
323 pub fn is_inverted(&self) -> bool {
324 *self == RXINVR::INVERTED
325 }
326}
327#[doc = "Possible values of the field `SWAP`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum SWAPR {
330 #[doc = "TX/RX pins are used as defined in standard pinout"]
331 STANDARD,
332 #[doc = "The TX and RX pins functions are swapped"]
333 SWAPPED,
334}
335impl SWAPR {
336 #[doc = r" Returns `true` if the bit is clear (0)"]
337 #[inline]
338 pub fn bit_is_clear(&self) -> bool {
339 !self.bit()
340 }
341 #[doc = r" Returns `true` if the bit is set (1)"]
342 #[inline]
343 pub fn bit_is_set(&self) -> bool {
344 self.bit()
345 }
346 #[doc = r" Value of the field as raw bits"]
347 #[inline]
348 pub fn bit(&self) -> bool {
349 match *self {
350 SWAPR::STANDARD => false,
351 SWAPR::SWAPPED => true,
352 }
353 }
354 #[allow(missing_docs)]
355 #[doc(hidden)]
356 #[inline]
357 pub fn _from(value: bool) -> SWAPR {
358 match value {
359 false => SWAPR::STANDARD,
360 true => SWAPR::SWAPPED,
361 }
362 }
363 #[doc = "Checks if the value of the field is `STANDARD`"]
364 #[inline]
365 pub fn is_standard(&self) -> bool {
366 *self == SWAPR::STANDARD
367 }
368 #[doc = "Checks if the value of the field is `SWAPPED`"]
369 #[inline]
370 pub fn is_swapped(&self) -> bool {
371 *self == SWAPR::SWAPPED
372 }
373}
374#[doc = "Possible values of the field `LINEN`"]
375#[derive(Clone, Copy, Debug, PartialEq)]
376pub enum LINENR {
377 #[doc = "LIN mode disabled"]
378 DISABLED,
379 #[doc = "LIN mode enabled"]
380 ENABLED,
381}
382impl LINENR {
383 #[doc = r" Returns `true` if the bit is clear (0)"]
384 #[inline]
385 pub fn bit_is_clear(&self) -> bool {
386 !self.bit()
387 }
388 #[doc = r" Returns `true` if the bit is set (1)"]
389 #[inline]
390 pub fn bit_is_set(&self) -> bool {
391 self.bit()
392 }
393 #[doc = r" Value of the field as raw bits"]
394 #[inline]
395 pub fn bit(&self) -> bool {
396 match *self {
397 LINENR::DISABLED => false,
398 LINENR::ENABLED => true,
399 }
400 }
401 #[allow(missing_docs)]
402 #[doc(hidden)]
403 #[inline]
404 pub fn _from(value: bool) -> LINENR {
405 match value {
406 false => LINENR::DISABLED,
407 true => LINENR::ENABLED,
408 }
409 }
410 #[doc = "Checks if the value of the field is `DISABLED`"]
411 #[inline]
412 pub fn is_disabled(&self) -> bool {
413 *self == LINENR::DISABLED
414 }
415 #[doc = "Checks if the value of the field is `ENABLED`"]
416 #[inline]
417 pub fn is_enabled(&self) -> bool {
418 *self == LINENR::ENABLED
419 }
420}
421#[doc = "Possible values of the field `STOP`"]
422#[derive(Clone, Copy, Debug, PartialEq)]
423pub enum STOPR {
424 #[doc = "1 stop bit"]
425 STOP1,
426 #[doc = "0.5 stop bit"]
427 STOP0P5,
428 #[doc = "2 stop bit"]
429 STOP2,
430 #[doc = "1.5 stop bit"]
431 STOP1P5,
432}
433impl STOPR {
434 #[doc = r" Value of the field as raw bits"]
435 #[inline]
436 pub fn bits(&self) -> u8 {
437 match *self {
438 STOPR::STOP1 => 0,
439 STOPR::STOP0P5 => 1,
440 STOPR::STOP2 => 2,
441 STOPR::STOP1P5 => 3,
442 }
443 }
444 #[allow(missing_docs)]
445 #[doc(hidden)]
446 #[inline]
447 pub fn _from(value: u8) -> STOPR {
448 match value {
449 0 => STOPR::STOP1,
450 1 => STOPR::STOP0P5,
451 2 => STOPR::STOP2,
452 3 => STOPR::STOP1P5,
453 _ => unreachable!(),
454 }
455 }
456 #[doc = "Checks if the value of the field is `STOP1`"]
457 #[inline]
458 pub fn is_stop1(&self) -> bool {
459 *self == STOPR::STOP1
460 }
461 #[doc = "Checks if the value of the field is `STOP0P5`"]
462 #[inline]
463 pub fn is_stop0p5(&self) -> bool {
464 *self == STOPR::STOP0P5
465 }
466 #[doc = "Checks if the value of the field is `STOP2`"]
467 #[inline]
468 pub fn is_stop2(&self) -> bool {
469 *self == STOPR::STOP2
470 }
471 #[doc = "Checks if the value of the field is `STOP1P5`"]
472 #[inline]
473 pub fn is_stop1p5(&self) -> bool {
474 *self == STOPR::STOP1P5
475 }
476}
477#[doc = "Possible values of the field `CLKEN`"]
478#[derive(Clone, Copy, Debug, PartialEq)]
479pub enum CLKENR {
480 #[doc = "CK pin disabled"]
481 DISABLED,
482 #[doc = "CK pin enabled"]
483 ENABLED,
484}
485impl CLKENR {
486 #[doc = r" Returns `true` if the bit is clear (0)"]
487 #[inline]
488 pub fn bit_is_clear(&self) -> bool {
489 !self.bit()
490 }
491 #[doc = r" Returns `true` if the bit is set (1)"]
492 #[inline]
493 pub fn bit_is_set(&self) -> bool {
494 self.bit()
495 }
496 #[doc = r" Value of the field as raw bits"]
497 #[inline]
498 pub fn bit(&self) -> bool {
499 match *self {
500 CLKENR::DISABLED => false,
501 CLKENR::ENABLED => true,
502 }
503 }
504 #[allow(missing_docs)]
505 #[doc(hidden)]
506 #[inline]
507 pub fn _from(value: bool) -> CLKENR {
508 match value {
509 false => CLKENR::DISABLED,
510 true => CLKENR::ENABLED,
511 }
512 }
513 #[doc = "Checks if the value of the field is `DISABLED`"]
514 #[inline]
515 pub fn is_disabled(&self) -> bool {
516 *self == CLKENR::DISABLED
517 }
518 #[doc = "Checks if the value of the field is `ENABLED`"]
519 #[inline]
520 pub fn is_enabled(&self) -> bool {
521 *self == CLKENR::ENABLED
522 }
523}
524#[doc = "Possible values of the field `CPOL`"]
525#[derive(Clone, Copy, Debug, PartialEq)]
526pub enum CPOLR {
527 #[doc = "Steady low value on CK pin outside transmission window"]
528 LOW,
529 #[doc = "Steady high value on CK pin outside transmission window"]
530 HIGH,
531}
532impl CPOLR {
533 #[doc = r" Returns `true` if the bit is clear (0)"]
534 #[inline]
535 pub fn bit_is_clear(&self) -> bool {
536 !self.bit()
537 }
538 #[doc = r" Returns `true` if the bit is set (1)"]
539 #[inline]
540 pub fn bit_is_set(&self) -> bool {
541 self.bit()
542 }
543 #[doc = r" Value of the field as raw bits"]
544 #[inline]
545 pub fn bit(&self) -> bool {
546 match *self {
547 CPOLR::LOW => false,
548 CPOLR::HIGH => true,
549 }
550 }
551 #[allow(missing_docs)]
552 #[doc(hidden)]
553 #[inline]
554 pub fn _from(value: bool) -> CPOLR {
555 match value {
556 false => CPOLR::LOW,
557 true => CPOLR::HIGH,
558 }
559 }
560 #[doc = "Checks if the value of the field is `LOW`"]
561 #[inline]
562 pub fn is_low(&self) -> bool {
563 *self == CPOLR::LOW
564 }
565 #[doc = "Checks if the value of the field is `HIGH`"]
566 #[inline]
567 pub fn is_high(&self) -> bool {
568 *self == CPOLR::HIGH
569 }
570}
571#[doc = "Possible values of the field `CPHA`"]
572#[derive(Clone, Copy, Debug, PartialEq)]
573pub enum CPHAR {
574 #[doc = "The first clock transition is the first data capture edge"]
575 FIRST,
576 #[doc = "The second clock transition is the first data capture edge"]
577 SECOND,
578}
579impl CPHAR {
580 #[doc = r" Returns `true` if the bit is clear (0)"]
581 #[inline]
582 pub fn bit_is_clear(&self) -> bool {
583 !self.bit()
584 }
585 #[doc = r" Returns `true` if the bit is set (1)"]
586 #[inline]
587 pub fn bit_is_set(&self) -> bool {
588 self.bit()
589 }
590 #[doc = r" Value of the field as raw bits"]
591 #[inline]
592 pub fn bit(&self) -> bool {
593 match *self {
594 CPHAR::FIRST => false,
595 CPHAR::SECOND => true,
596 }
597 }
598 #[allow(missing_docs)]
599 #[doc(hidden)]
600 #[inline]
601 pub fn _from(value: bool) -> CPHAR {
602 match value {
603 false => CPHAR::FIRST,
604 true => CPHAR::SECOND,
605 }
606 }
607 #[doc = "Checks if the value of the field is `FIRST`"]
608 #[inline]
609 pub fn is_first(&self) -> bool {
610 *self == CPHAR::FIRST
611 }
612 #[doc = "Checks if the value of the field is `SECOND`"]
613 #[inline]
614 pub fn is_second(&self) -> bool {
615 *self == CPHAR::SECOND
616 }
617}
618#[doc = "Possible values of the field `LBCL`"]
619#[derive(Clone, Copy, Debug, PartialEq)]
620pub enum LBCLR {
621 #[doc = "The clock pulse of the last data bit is not output to the CK pin"]
622 NOTOUTPUT,
623 #[doc = "The clock pulse of the last data bit is output to the CK pin"]
624 OUTPUT,
625}
626impl LBCLR {
627 #[doc = r" Returns `true` if the bit is clear (0)"]
628 #[inline]
629 pub fn bit_is_clear(&self) -> bool {
630 !self.bit()
631 }
632 #[doc = r" Returns `true` if the bit is set (1)"]
633 #[inline]
634 pub fn bit_is_set(&self) -> bool {
635 self.bit()
636 }
637 #[doc = r" Value of the field as raw bits"]
638 #[inline]
639 pub fn bit(&self) -> bool {
640 match *self {
641 LBCLR::NOTOUTPUT => false,
642 LBCLR::OUTPUT => true,
643 }
644 }
645 #[allow(missing_docs)]
646 #[doc(hidden)]
647 #[inline]
648 pub fn _from(value: bool) -> LBCLR {
649 match value {
650 false => LBCLR::NOTOUTPUT,
651 true => LBCLR::OUTPUT,
652 }
653 }
654 #[doc = "Checks if the value of the field is `NOTOUTPUT`"]
655 #[inline]
656 pub fn is_not_output(&self) -> bool {
657 *self == LBCLR::NOTOUTPUT
658 }
659 #[doc = "Checks if the value of the field is `OUTPUT`"]
660 #[inline]
661 pub fn is_output(&self) -> bool {
662 *self == LBCLR::OUTPUT
663 }
664}
665#[doc = "Possible values of the field `LBDIE`"]
666#[derive(Clone, Copy, Debug, PartialEq)]
667pub enum LBDIER {
668 #[doc = "Interrupt is inhibited"]
669 DISABLED,
670 #[doc = "An interrupt is generated whenever LBDF=1 in the ISR register"]
671 ENABLED,
672}
673impl LBDIER {
674 #[doc = r" Returns `true` if the bit is clear (0)"]
675 #[inline]
676 pub fn bit_is_clear(&self) -> bool {
677 !self.bit()
678 }
679 #[doc = r" Returns `true` if the bit is set (1)"]
680 #[inline]
681 pub fn bit_is_set(&self) -> bool {
682 self.bit()
683 }
684 #[doc = r" Value of the field as raw bits"]
685 #[inline]
686 pub fn bit(&self) -> bool {
687 match *self {
688 LBDIER::DISABLED => false,
689 LBDIER::ENABLED => true,
690 }
691 }
692 #[allow(missing_docs)]
693 #[doc(hidden)]
694 #[inline]
695 pub fn _from(value: bool) -> LBDIER {
696 match value {
697 false => LBDIER::DISABLED,
698 true => LBDIER::ENABLED,
699 }
700 }
701 #[doc = "Checks if the value of the field is `DISABLED`"]
702 #[inline]
703 pub fn is_disabled(&self) -> bool {
704 *self == LBDIER::DISABLED
705 }
706 #[doc = "Checks if the value of the field is `ENABLED`"]
707 #[inline]
708 pub fn is_enabled(&self) -> bool {
709 *self == LBDIER::ENABLED
710 }
711}
712#[doc = "Possible values of the field `LBDL`"]
713#[derive(Clone, Copy, Debug, PartialEq)]
714pub enum LBDLR {
715 #[doc = "10-bit break detection"]
716 BIT10,
717 #[doc = "11-bit break detection"]
718 BIT11,
719}
720impl LBDLR {
721 #[doc = r" Returns `true` if the bit is clear (0)"]
722 #[inline]
723 pub fn bit_is_clear(&self) -> bool {
724 !self.bit()
725 }
726 #[doc = r" Returns `true` if the bit is set (1)"]
727 #[inline]
728 pub fn bit_is_set(&self) -> bool {
729 self.bit()
730 }
731 #[doc = r" Value of the field as raw bits"]
732 #[inline]
733 pub fn bit(&self) -> bool {
734 match *self {
735 LBDLR::BIT10 => false,
736 LBDLR::BIT11 => true,
737 }
738 }
739 #[allow(missing_docs)]
740 #[doc(hidden)]
741 #[inline]
742 pub fn _from(value: bool) -> LBDLR {
743 match value {
744 false => LBDLR::BIT10,
745 true => LBDLR::BIT11,
746 }
747 }
748 #[doc = "Checks if the value of the field is `BIT10`"]
749 #[inline]
750 pub fn is_bit10(&self) -> bool {
751 *self == LBDLR::BIT10
752 }
753 #[doc = "Checks if the value of the field is `BIT11`"]
754 #[inline]
755 pub fn is_bit11(&self) -> bool {
756 *self == LBDLR::BIT11
757 }
758}
759#[doc = "Possible values of the field `ADDM7`"]
760#[derive(Clone, Copy, Debug, PartialEq)]
761pub enum ADDM7R {
762 #[doc = "4-bit address detection"]
763 BIT4,
764 #[doc = "7-bit address detection"]
765 BIT7,
766}
767impl ADDM7R {
768 #[doc = r" Returns `true` if the bit is clear (0)"]
769 #[inline]
770 pub fn bit_is_clear(&self) -> bool {
771 !self.bit()
772 }
773 #[doc = r" Returns `true` if the bit is set (1)"]
774 #[inline]
775 pub fn bit_is_set(&self) -> bool {
776 self.bit()
777 }
778 #[doc = r" Value of the field as raw bits"]
779 #[inline]
780 pub fn bit(&self) -> bool {
781 match *self {
782 ADDM7R::BIT4 => false,
783 ADDM7R::BIT7 => true,
784 }
785 }
786 #[allow(missing_docs)]
787 #[doc(hidden)]
788 #[inline]
789 pub fn _from(value: bool) -> ADDM7R {
790 match value {
791 false => ADDM7R::BIT4,
792 true => ADDM7R::BIT7,
793 }
794 }
795 #[doc = "Checks if the value of the field is `BIT4`"]
796 #[inline]
797 pub fn is_bit4(&self) -> bool {
798 *self == ADDM7R::BIT4
799 }
800 #[doc = "Checks if the value of the field is `BIT7`"]
801 #[inline]
802 pub fn is_bit7(&self) -> bool {
803 *self == ADDM7R::BIT7
804 }
805}
806#[doc = r" Value of the field"]
807pub struct ADDR {
808 bits: u8,
809}
810impl ADDR {
811 #[doc = r" Value of the field as raw bits"]
812 #[inline]
813 pub fn bits(&self) -> u8 {
814 self.bits
815 }
816}
817#[doc = "Possible values of the field `ABRMOD`"]
818#[derive(Clone, Copy, Debug, PartialEq)]
819pub enum ABRMODR {
820 #[doc = "Measurement of the start bit is used to detect the baud rate"]
821 START,
822 #[doc = "Falling edge to falling edge measurement"]
823 EDGE,
824 #[doc = "0x7F frame detection"]
825 FRAME7F,
826 #[doc = "0x55 frame detection"]
827 FRAME55,
828}
829impl ABRMODR {
830 #[doc = r" Value of the field as raw bits"]
831 #[inline]
832 pub fn bits(&self) -> u8 {
833 match *self {
834 ABRMODR::START => 0,
835 ABRMODR::EDGE => 1,
836 ABRMODR::FRAME7F => 2,
837 ABRMODR::FRAME55 => 3,
838 }
839 }
840 #[allow(missing_docs)]
841 #[doc(hidden)]
842 #[inline]
843 pub fn _from(value: u8) -> ABRMODR {
844 match value {
845 0 => ABRMODR::START,
846 1 => ABRMODR::EDGE,
847 2 => ABRMODR::FRAME7F,
848 3 => ABRMODR::FRAME55,
849 _ => unreachable!(),
850 }
851 }
852 #[doc = "Checks if the value of the field is `START`"]
853 #[inline]
854 pub fn is_start(&self) -> bool {
855 *self == ABRMODR::START
856 }
857 #[doc = "Checks if the value of the field is `EDGE`"]
858 #[inline]
859 pub fn is_edge(&self) -> bool {
860 *self == ABRMODR::EDGE
861 }
862 #[doc = "Checks if the value of the field is `FRAME7F`"]
863 #[inline]
864 pub fn is_frame7f(&self) -> bool {
865 *self == ABRMODR::FRAME7F
866 }
867 #[doc = "Checks if the value of the field is `FRAME55`"]
868 #[inline]
869 pub fn is_frame55(&self) -> bool {
870 *self == ABRMODR::FRAME55
871 }
872}
873#[doc = "Values that can be written to the field `RTOEN`"]
874pub enum RTOENW {
875 #[doc = "Receiver timeout feature disabled"]
876 DISABLED,
877 #[doc = "Receiver timeout feature enabled"]
878 ENABLED,
879}
880impl RTOENW {
881 #[allow(missing_docs)]
882 #[doc(hidden)]
883 #[inline]
884 pub fn _bits(&self) -> bool {
885 match *self {
886 RTOENW::DISABLED => false,
887 RTOENW::ENABLED => true,
888 }
889 }
890}
891#[doc = r" Proxy"]
892pub struct _RTOENW<'a> {
893 w: &'a mut W,
894}
895impl<'a> _RTOENW<'a> {
896 #[doc = r" Writes `variant` to the field"]
897 #[inline]
898 pub fn variant(self, variant: RTOENW) -> &'a mut W {
899 {
900 self.bit(variant._bits())
901 }
902 }
903 #[doc = "Receiver timeout feature disabled"]
904 #[inline]
905 pub fn disabled(self) -> &'a mut W {
906 self.variant(RTOENW::DISABLED)
907 }
908 #[doc = "Receiver timeout feature enabled"]
909 #[inline]
910 pub fn enabled(self) -> &'a mut W {
911 self.variant(RTOENW::ENABLED)
912 }
913 #[doc = r" Sets the field bit"]
914 pub fn set_bit(self) -> &'a mut W {
915 self.bit(true)
916 }
917 #[doc = r" Clears the field bit"]
918 pub fn clear_bit(self) -> &'a mut W {
919 self.bit(false)
920 }
921 #[doc = r" Writes raw bits to the field"]
922 #[inline]
923 pub fn bit(self, value: bool) -> &'a mut W {
924 const MASK: bool = true;
925 const OFFSET: u8 = 23;
926 self.w.bits &= !((MASK as u32) << OFFSET);
927 self.w.bits |= ((value & MASK) as u32) << OFFSET;
928 self.w
929 }
930}
931#[doc = "Values that can be written to the field `ABREN`"]
932pub enum ABRENW {
933 #[doc = "Auto baud rate detection is disabled"]
934 DISABLED,
935 #[doc = "Auto baud rate detection is enabled"]
936 ENABLED,
937}
938impl ABRENW {
939 #[allow(missing_docs)]
940 #[doc(hidden)]
941 #[inline]
942 pub fn _bits(&self) -> bool {
943 match *self {
944 ABRENW::DISABLED => false,
945 ABRENW::ENABLED => true,
946 }
947 }
948}
949#[doc = r" Proxy"]
950pub struct _ABRENW<'a> {
951 w: &'a mut W,
952}
953impl<'a> _ABRENW<'a> {
954 #[doc = r" Writes `variant` to the field"]
955 #[inline]
956 pub fn variant(self, variant: ABRENW) -> &'a mut W {
957 {
958 self.bit(variant._bits())
959 }
960 }
961 #[doc = "Auto baud rate detection is disabled"]
962 #[inline]
963 pub fn disabled(self) -> &'a mut W {
964 self.variant(ABRENW::DISABLED)
965 }
966 #[doc = "Auto baud rate detection is enabled"]
967 #[inline]
968 pub fn enabled(self) -> &'a mut W {
969 self.variant(ABRENW::ENABLED)
970 }
971 #[doc = r" Sets the field bit"]
972 pub fn set_bit(self) -> &'a mut W {
973 self.bit(true)
974 }
975 #[doc = r" Clears the field bit"]
976 pub fn clear_bit(self) -> &'a mut W {
977 self.bit(false)
978 }
979 #[doc = r" Writes raw bits to the field"]
980 #[inline]
981 pub fn bit(self, value: bool) -> &'a mut W {
982 const MASK: bool = true;
983 const OFFSET: u8 = 20;
984 self.w.bits &= !((MASK as u32) << OFFSET);
985 self.w.bits |= ((value & MASK) as u32) << OFFSET;
986 self.w
987 }
988}
989#[doc = "Values that can be written to the field `MSBFIRST`"]
990pub enum MSBFIRSTW {
991 #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
992 LSB,
993 #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
994 MSB,
995}
996impl MSBFIRSTW {
997 #[allow(missing_docs)]
998 #[doc(hidden)]
999 #[inline]
1000 pub fn _bits(&self) -> bool {
1001 match *self {
1002 MSBFIRSTW::LSB => false,
1003 MSBFIRSTW::MSB => true,
1004 }
1005 }
1006}
1007#[doc = r" Proxy"]
1008pub struct _MSBFIRSTW<'a> {
1009 w: &'a mut W,
1010}
1011impl<'a> _MSBFIRSTW<'a> {
1012 #[doc = r" Writes `variant` to the field"]
1013 #[inline]
1014 pub fn variant(self, variant: MSBFIRSTW) -> &'a mut W {
1015 {
1016 self.bit(variant._bits())
1017 }
1018 }
1019 #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
1020 #[inline]
1021 pub fn lsb(self) -> &'a mut W {
1022 self.variant(MSBFIRSTW::LSB)
1023 }
1024 #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
1025 #[inline]
1026 pub fn msb(self) -> &'a mut W {
1027 self.variant(MSBFIRSTW::MSB)
1028 }
1029 #[doc = r" Sets the field bit"]
1030 pub fn set_bit(self) -> &'a mut W {
1031 self.bit(true)
1032 }
1033 #[doc = r" Clears the field bit"]
1034 pub fn clear_bit(self) -> &'a mut W {
1035 self.bit(false)
1036 }
1037 #[doc = r" Writes raw bits to the field"]
1038 #[inline]
1039 pub fn bit(self, value: bool) -> &'a mut W {
1040 const MASK: bool = true;
1041 const OFFSET: u8 = 19;
1042 self.w.bits &= !((MASK as u32) << OFFSET);
1043 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1044 self.w
1045 }
1046}
1047#[doc = "Values that can be written to the field `DATAINV`"]
1048pub enum DATAINVW {
1049 #[doc = "Logical data from the data register are send/received in positive/direct logic"]
1050 POSITIVE,
1051 #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
1052 NEGATIVE,
1053}
1054impl DATAINVW {
1055 #[allow(missing_docs)]
1056 #[doc(hidden)]
1057 #[inline]
1058 pub fn _bits(&self) -> bool {
1059 match *self {
1060 DATAINVW::POSITIVE => false,
1061 DATAINVW::NEGATIVE => true,
1062 }
1063 }
1064}
1065#[doc = r" Proxy"]
1066pub struct _DATAINVW<'a> {
1067 w: &'a mut W,
1068}
1069impl<'a> _DATAINVW<'a> {
1070 #[doc = r" Writes `variant` to the field"]
1071 #[inline]
1072 pub fn variant(self, variant: DATAINVW) -> &'a mut W {
1073 {
1074 self.bit(variant._bits())
1075 }
1076 }
1077 #[doc = "Logical data from the data register are send/received in positive/direct logic"]
1078 #[inline]
1079 pub fn positive(self) -> &'a mut W {
1080 self.variant(DATAINVW::POSITIVE)
1081 }
1082 #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
1083 #[inline]
1084 pub fn negative(self) -> &'a mut W {
1085 self.variant(DATAINVW::NEGATIVE)
1086 }
1087 #[doc = r" Sets the field bit"]
1088 pub fn set_bit(self) -> &'a mut W {
1089 self.bit(true)
1090 }
1091 #[doc = r" Clears the field bit"]
1092 pub fn clear_bit(self) -> &'a mut W {
1093 self.bit(false)
1094 }
1095 #[doc = r" Writes raw bits to the field"]
1096 #[inline]
1097 pub fn bit(self, value: bool) -> &'a mut W {
1098 const MASK: bool = true;
1099 const OFFSET: u8 = 18;
1100 self.w.bits &= !((MASK as u32) << OFFSET);
1101 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1102 self.w
1103 }
1104}
1105#[doc = "Values that can be written to the field `TXINV`"]
1106pub enum TXINVW {
1107 #[doc = "TX pin signal works using the standard logic levels"]
1108 STANDARD,
1109 #[doc = "TX pin signal values are inverted"]
1110 INVERTED,
1111}
1112impl TXINVW {
1113 #[allow(missing_docs)]
1114 #[doc(hidden)]
1115 #[inline]
1116 pub fn _bits(&self) -> bool {
1117 match *self {
1118 TXINVW::STANDARD => false,
1119 TXINVW::INVERTED => true,
1120 }
1121 }
1122}
1123#[doc = r" Proxy"]
1124pub struct _TXINVW<'a> {
1125 w: &'a mut W,
1126}
1127impl<'a> _TXINVW<'a> {
1128 #[doc = r" Writes `variant` to the field"]
1129 #[inline]
1130 pub fn variant(self, variant: TXINVW) -> &'a mut W {
1131 {
1132 self.bit(variant._bits())
1133 }
1134 }
1135 #[doc = "TX pin signal works using the standard logic levels"]
1136 #[inline]
1137 pub fn standard(self) -> &'a mut W {
1138 self.variant(TXINVW::STANDARD)
1139 }
1140 #[doc = "TX pin signal values are inverted"]
1141 #[inline]
1142 pub fn inverted(self) -> &'a mut W {
1143 self.variant(TXINVW::INVERTED)
1144 }
1145 #[doc = r" Sets the field bit"]
1146 pub fn set_bit(self) -> &'a mut W {
1147 self.bit(true)
1148 }
1149 #[doc = r" Clears the field bit"]
1150 pub fn clear_bit(self) -> &'a mut W {
1151 self.bit(false)
1152 }
1153 #[doc = r" Writes raw bits to the field"]
1154 #[inline]
1155 pub fn bit(self, value: bool) -> &'a mut W {
1156 const MASK: bool = true;
1157 const OFFSET: u8 = 17;
1158 self.w.bits &= !((MASK as u32) << OFFSET);
1159 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1160 self.w
1161 }
1162}
1163#[doc = "Values that can be written to the field `RXINV`"]
1164pub enum RXINVW {
1165 #[doc = "RX pin signal works using the standard logic levels"]
1166 STANDARD,
1167 #[doc = "RX pin signal values are inverted"]
1168 INVERTED,
1169}
1170impl RXINVW {
1171 #[allow(missing_docs)]
1172 #[doc(hidden)]
1173 #[inline]
1174 pub fn _bits(&self) -> bool {
1175 match *self {
1176 RXINVW::STANDARD => false,
1177 RXINVW::INVERTED => true,
1178 }
1179 }
1180}
1181#[doc = r" Proxy"]
1182pub struct _RXINVW<'a> {
1183 w: &'a mut W,
1184}
1185impl<'a> _RXINVW<'a> {
1186 #[doc = r" Writes `variant` to the field"]
1187 #[inline]
1188 pub fn variant(self, variant: RXINVW) -> &'a mut W {
1189 {
1190 self.bit(variant._bits())
1191 }
1192 }
1193 #[doc = "RX pin signal works using the standard logic levels"]
1194 #[inline]
1195 pub fn standard(self) -> &'a mut W {
1196 self.variant(RXINVW::STANDARD)
1197 }
1198 #[doc = "RX pin signal values are inverted"]
1199 #[inline]
1200 pub fn inverted(self) -> &'a mut W {
1201 self.variant(RXINVW::INVERTED)
1202 }
1203 #[doc = r" Sets the field bit"]
1204 pub fn set_bit(self) -> &'a mut W {
1205 self.bit(true)
1206 }
1207 #[doc = r" Clears the field bit"]
1208 pub fn clear_bit(self) -> &'a mut W {
1209 self.bit(false)
1210 }
1211 #[doc = r" Writes raw bits to the field"]
1212 #[inline]
1213 pub fn bit(self, value: bool) -> &'a mut W {
1214 const MASK: bool = true;
1215 const OFFSET: u8 = 16;
1216 self.w.bits &= !((MASK as u32) << OFFSET);
1217 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1218 self.w
1219 }
1220}
1221#[doc = "Values that can be written to the field `SWAP`"]
1222pub enum SWAPW {
1223 #[doc = "TX/RX pins are used as defined in standard pinout"]
1224 STANDARD,
1225 #[doc = "The TX and RX pins functions are swapped"]
1226 SWAPPED,
1227}
1228impl SWAPW {
1229 #[allow(missing_docs)]
1230 #[doc(hidden)]
1231 #[inline]
1232 pub fn _bits(&self) -> bool {
1233 match *self {
1234 SWAPW::STANDARD => false,
1235 SWAPW::SWAPPED => true,
1236 }
1237 }
1238}
1239#[doc = r" Proxy"]
1240pub struct _SWAPW<'a> {
1241 w: &'a mut W,
1242}
1243impl<'a> _SWAPW<'a> {
1244 #[doc = r" Writes `variant` to the field"]
1245 #[inline]
1246 pub fn variant(self, variant: SWAPW) -> &'a mut W {
1247 {
1248 self.bit(variant._bits())
1249 }
1250 }
1251 #[doc = "TX/RX pins are used as defined in standard pinout"]
1252 #[inline]
1253 pub fn standard(self) -> &'a mut W {
1254 self.variant(SWAPW::STANDARD)
1255 }
1256 #[doc = "The TX and RX pins functions are swapped"]
1257 #[inline]
1258 pub fn swapped(self) -> &'a mut W {
1259 self.variant(SWAPW::SWAPPED)
1260 }
1261 #[doc = r" Sets the field bit"]
1262 pub fn set_bit(self) -> &'a mut W {
1263 self.bit(true)
1264 }
1265 #[doc = r" Clears the field bit"]
1266 pub fn clear_bit(self) -> &'a mut W {
1267 self.bit(false)
1268 }
1269 #[doc = r" Writes raw bits to the field"]
1270 #[inline]
1271 pub fn bit(self, value: bool) -> &'a mut W {
1272 const MASK: bool = true;
1273 const OFFSET: u8 = 15;
1274 self.w.bits &= !((MASK as u32) << OFFSET);
1275 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1276 self.w
1277 }
1278}
1279#[doc = "Values that can be written to the field `LINEN`"]
1280pub enum LINENW {
1281 #[doc = "LIN mode disabled"]
1282 DISABLED,
1283 #[doc = "LIN mode enabled"]
1284 ENABLED,
1285}
1286impl LINENW {
1287 #[allow(missing_docs)]
1288 #[doc(hidden)]
1289 #[inline]
1290 pub fn _bits(&self) -> bool {
1291 match *self {
1292 LINENW::DISABLED => false,
1293 LINENW::ENABLED => true,
1294 }
1295 }
1296}
1297#[doc = r" Proxy"]
1298pub struct _LINENW<'a> {
1299 w: &'a mut W,
1300}
1301impl<'a> _LINENW<'a> {
1302 #[doc = r" Writes `variant` to the field"]
1303 #[inline]
1304 pub fn variant(self, variant: LINENW) -> &'a mut W {
1305 {
1306 self.bit(variant._bits())
1307 }
1308 }
1309 #[doc = "LIN mode disabled"]
1310 #[inline]
1311 pub fn disabled(self) -> &'a mut W {
1312 self.variant(LINENW::DISABLED)
1313 }
1314 #[doc = "LIN mode enabled"]
1315 #[inline]
1316 pub fn enabled(self) -> &'a mut W {
1317 self.variant(LINENW::ENABLED)
1318 }
1319 #[doc = r" Sets the field bit"]
1320 pub fn set_bit(self) -> &'a mut W {
1321 self.bit(true)
1322 }
1323 #[doc = r" Clears the field bit"]
1324 pub fn clear_bit(self) -> &'a mut W {
1325 self.bit(false)
1326 }
1327 #[doc = r" Writes raw bits to the field"]
1328 #[inline]
1329 pub fn bit(self, value: bool) -> &'a mut W {
1330 const MASK: bool = true;
1331 const OFFSET: u8 = 14;
1332 self.w.bits &= !((MASK as u32) << OFFSET);
1333 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1334 self.w
1335 }
1336}
1337#[doc = "Values that can be written to the field `STOP`"]
1338pub enum STOPW {
1339 #[doc = "1 stop bit"]
1340 STOP1,
1341 #[doc = "0.5 stop bit"]
1342 STOP0P5,
1343 #[doc = "2 stop bit"]
1344 STOP2,
1345 #[doc = "1.5 stop bit"]
1346 STOP1P5,
1347}
1348impl STOPW {
1349 #[allow(missing_docs)]
1350 #[doc(hidden)]
1351 #[inline]
1352 pub fn _bits(&self) -> u8 {
1353 match *self {
1354 STOPW::STOP1 => 0,
1355 STOPW::STOP0P5 => 1,
1356 STOPW::STOP2 => 2,
1357 STOPW::STOP1P5 => 3,
1358 }
1359 }
1360}
1361#[doc = r" Proxy"]
1362pub struct _STOPW<'a> {
1363 w: &'a mut W,
1364}
1365impl<'a> _STOPW<'a> {
1366 #[doc = r" Writes `variant` to the field"]
1367 #[inline]
1368 pub fn variant(self, variant: STOPW) -> &'a mut W {
1369 {
1370 self.bits(variant._bits())
1371 }
1372 }
1373 #[doc = "1 stop bit"]
1374 #[inline]
1375 pub fn stop1(self) -> &'a mut W {
1376 self.variant(STOPW::STOP1)
1377 }
1378 #[doc = "0.5 stop bit"]
1379 #[inline]
1380 pub fn stop0p5(self) -> &'a mut W {
1381 self.variant(STOPW::STOP0P5)
1382 }
1383 #[doc = "2 stop bit"]
1384 #[inline]
1385 pub fn stop2(self) -> &'a mut W {
1386 self.variant(STOPW::STOP2)
1387 }
1388 #[doc = "1.5 stop bit"]
1389 #[inline]
1390 pub fn stop1p5(self) -> &'a mut W {
1391 self.variant(STOPW::STOP1P5)
1392 }
1393 #[doc = r" Writes raw bits to the field"]
1394 #[inline]
1395 pub fn bits(self, value: u8) -> &'a mut W {
1396 const MASK: u8 = 3;
1397 const OFFSET: u8 = 12;
1398 self.w.bits &= !((MASK as u32) << OFFSET);
1399 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1400 self.w
1401 }
1402}
1403#[doc = "Values that can be written to the field `CLKEN`"]
1404pub enum CLKENW {
1405 #[doc = "CK pin disabled"]
1406 DISABLED,
1407 #[doc = "CK pin enabled"]
1408 ENABLED,
1409}
1410impl CLKENW {
1411 #[allow(missing_docs)]
1412 #[doc(hidden)]
1413 #[inline]
1414 pub fn _bits(&self) -> bool {
1415 match *self {
1416 CLKENW::DISABLED => false,
1417 CLKENW::ENABLED => true,
1418 }
1419 }
1420}
1421#[doc = r" Proxy"]
1422pub struct _CLKENW<'a> {
1423 w: &'a mut W,
1424}
1425impl<'a> _CLKENW<'a> {
1426 #[doc = r" Writes `variant` to the field"]
1427 #[inline]
1428 pub fn variant(self, variant: CLKENW) -> &'a mut W {
1429 {
1430 self.bit(variant._bits())
1431 }
1432 }
1433 #[doc = "CK pin disabled"]
1434 #[inline]
1435 pub fn disabled(self) -> &'a mut W {
1436 self.variant(CLKENW::DISABLED)
1437 }
1438 #[doc = "CK pin enabled"]
1439 #[inline]
1440 pub fn enabled(self) -> &'a mut W {
1441 self.variant(CLKENW::ENABLED)
1442 }
1443 #[doc = r" Sets the field bit"]
1444 pub fn set_bit(self) -> &'a mut W {
1445 self.bit(true)
1446 }
1447 #[doc = r" Clears the field bit"]
1448 pub fn clear_bit(self) -> &'a mut W {
1449 self.bit(false)
1450 }
1451 #[doc = r" Writes raw bits to the field"]
1452 #[inline]
1453 pub fn bit(self, value: bool) -> &'a mut W {
1454 const MASK: bool = true;
1455 const OFFSET: u8 = 11;
1456 self.w.bits &= !((MASK as u32) << OFFSET);
1457 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1458 self.w
1459 }
1460}
1461#[doc = "Values that can be written to the field `CPOL`"]
1462pub enum CPOLW {
1463 #[doc = "Steady low value on CK pin outside transmission window"]
1464 LOW,
1465 #[doc = "Steady high value on CK pin outside transmission window"]
1466 HIGH,
1467}
1468impl CPOLW {
1469 #[allow(missing_docs)]
1470 #[doc(hidden)]
1471 #[inline]
1472 pub fn _bits(&self) -> bool {
1473 match *self {
1474 CPOLW::LOW => false,
1475 CPOLW::HIGH => true,
1476 }
1477 }
1478}
1479#[doc = r" Proxy"]
1480pub struct _CPOLW<'a> {
1481 w: &'a mut W,
1482}
1483impl<'a> _CPOLW<'a> {
1484 #[doc = r" Writes `variant` to the field"]
1485 #[inline]
1486 pub fn variant(self, variant: CPOLW) -> &'a mut W {
1487 {
1488 self.bit(variant._bits())
1489 }
1490 }
1491 #[doc = "Steady low value on CK pin outside transmission window"]
1492 #[inline]
1493 pub fn low(self) -> &'a mut W {
1494 self.variant(CPOLW::LOW)
1495 }
1496 #[doc = "Steady high value on CK pin outside transmission window"]
1497 #[inline]
1498 pub fn high(self) -> &'a mut W {
1499 self.variant(CPOLW::HIGH)
1500 }
1501 #[doc = r" Sets the field bit"]
1502 pub fn set_bit(self) -> &'a mut W {
1503 self.bit(true)
1504 }
1505 #[doc = r" Clears the field bit"]
1506 pub fn clear_bit(self) -> &'a mut W {
1507 self.bit(false)
1508 }
1509 #[doc = r" Writes raw bits to the field"]
1510 #[inline]
1511 pub fn bit(self, value: bool) -> &'a mut W {
1512 const MASK: bool = true;
1513 const OFFSET: u8 = 10;
1514 self.w.bits &= !((MASK as u32) << OFFSET);
1515 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1516 self.w
1517 }
1518}
1519#[doc = "Values that can be written to the field `CPHA`"]
1520pub enum CPHAW {
1521 #[doc = "The first clock transition is the first data capture edge"]
1522 FIRST,
1523 #[doc = "The second clock transition is the first data capture edge"]
1524 SECOND,
1525}
1526impl CPHAW {
1527 #[allow(missing_docs)]
1528 #[doc(hidden)]
1529 #[inline]
1530 pub fn _bits(&self) -> bool {
1531 match *self {
1532 CPHAW::FIRST => false,
1533 CPHAW::SECOND => true,
1534 }
1535 }
1536}
1537#[doc = r" Proxy"]
1538pub struct _CPHAW<'a> {
1539 w: &'a mut W,
1540}
1541impl<'a> _CPHAW<'a> {
1542 #[doc = r" Writes `variant` to the field"]
1543 #[inline]
1544 pub fn variant(self, variant: CPHAW) -> &'a mut W {
1545 {
1546 self.bit(variant._bits())
1547 }
1548 }
1549 #[doc = "The first clock transition is the first data capture edge"]
1550 #[inline]
1551 pub fn first(self) -> &'a mut W {
1552 self.variant(CPHAW::FIRST)
1553 }
1554 #[doc = "The second clock transition is the first data capture edge"]
1555 #[inline]
1556 pub fn second(self) -> &'a mut W {
1557 self.variant(CPHAW::SECOND)
1558 }
1559 #[doc = r" Sets the field bit"]
1560 pub fn set_bit(self) -> &'a mut W {
1561 self.bit(true)
1562 }
1563 #[doc = r" Clears the field bit"]
1564 pub fn clear_bit(self) -> &'a mut W {
1565 self.bit(false)
1566 }
1567 #[doc = r" Writes raw bits to the field"]
1568 #[inline]
1569 pub fn bit(self, value: bool) -> &'a mut W {
1570 const MASK: bool = true;
1571 const OFFSET: u8 = 9;
1572 self.w.bits &= !((MASK as u32) << OFFSET);
1573 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1574 self.w
1575 }
1576}
1577#[doc = "Values that can be written to the field `LBCL`"]
1578pub enum LBCLW {
1579 #[doc = "The clock pulse of the last data bit is not output to the CK pin"]
1580 NOTOUTPUT,
1581 #[doc = "The clock pulse of the last data bit is output to the CK pin"]
1582 OUTPUT,
1583}
1584impl LBCLW {
1585 #[allow(missing_docs)]
1586 #[doc(hidden)]
1587 #[inline]
1588 pub fn _bits(&self) -> bool {
1589 match *self {
1590 LBCLW::NOTOUTPUT => false,
1591 LBCLW::OUTPUT => true,
1592 }
1593 }
1594}
1595#[doc = r" Proxy"]
1596pub struct _LBCLW<'a> {
1597 w: &'a mut W,
1598}
1599impl<'a> _LBCLW<'a> {
1600 #[doc = r" Writes `variant` to the field"]
1601 #[inline]
1602 pub fn variant(self, variant: LBCLW) -> &'a mut W {
1603 {
1604 self.bit(variant._bits())
1605 }
1606 }
1607 #[doc = "The clock pulse of the last data bit is not output to the CK pin"]
1608 #[inline]
1609 pub fn not_output(self) -> &'a mut W {
1610 self.variant(LBCLW::NOTOUTPUT)
1611 }
1612 #[doc = "The clock pulse of the last data bit is output to the CK pin"]
1613 #[inline]
1614 pub fn output(self) -> &'a mut W {
1615 self.variant(LBCLW::OUTPUT)
1616 }
1617 #[doc = r" Sets the field bit"]
1618 pub fn set_bit(self) -> &'a mut W {
1619 self.bit(true)
1620 }
1621 #[doc = r" Clears the field bit"]
1622 pub fn clear_bit(self) -> &'a mut W {
1623 self.bit(false)
1624 }
1625 #[doc = r" Writes raw bits to the field"]
1626 #[inline]
1627 pub fn bit(self, value: bool) -> &'a mut W {
1628 const MASK: bool = true;
1629 const OFFSET: u8 = 8;
1630 self.w.bits &= !((MASK as u32) << OFFSET);
1631 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1632 self.w
1633 }
1634}
1635#[doc = "Values that can be written to the field `LBDIE`"]
1636pub enum LBDIEW {
1637 #[doc = "Interrupt is inhibited"]
1638 DISABLED,
1639 #[doc = "An interrupt is generated whenever LBDF=1 in the ISR register"]
1640 ENABLED,
1641}
1642impl LBDIEW {
1643 #[allow(missing_docs)]
1644 #[doc(hidden)]
1645 #[inline]
1646 pub fn _bits(&self) -> bool {
1647 match *self {
1648 LBDIEW::DISABLED => false,
1649 LBDIEW::ENABLED => true,
1650 }
1651 }
1652}
1653#[doc = r" Proxy"]
1654pub struct _LBDIEW<'a> {
1655 w: &'a mut W,
1656}
1657impl<'a> _LBDIEW<'a> {
1658 #[doc = r" Writes `variant` to the field"]
1659 #[inline]
1660 pub fn variant(self, variant: LBDIEW) -> &'a mut W {
1661 {
1662 self.bit(variant._bits())
1663 }
1664 }
1665 #[doc = "Interrupt is inhibited"]
1666 #[inline]
1667 pub fn disabled(self) -> &'a mut W {
1668 self.variant(LBDIEW::DISABLED)
1669 }
1670 #[doc = "An interrupt is generated whenever LBDF=1 in the ISR register"]
1671 #[inline]
1672 pub fn enabled(self) -> &'a mut W {
1673 self.variant(LBDIEW::ENABLED)
1674 }
1675 #[doc = r" Sets the field bit"]
1676 pub fn set_bit(self) -> &'a mut W {
1677 self.bit(true)
1678 }
1679 #[doc = r" Clears the field bit"]
1680 pub fn clear_bit(self) -> &'a mut W {
1681 self.bit(false)
1682 }
1683 #[doc = r" Writes raw bits to the field"]
1684 #[inline]
1685 pub fn bit(self, value: bool) -> &'a mut W {
1686 const MASK: bool = true;
1687 const OFFSET: u8 = 6;
1688 self.w.bits &= !((MASK as u32) << OFFSET);
1689 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1690 self.w
1691 }
1692}
1693#[doc = "Values that can be written to the field `LBDL`"]
1694pub enum LBDLW {
1695 #[doc = "10-bit break detection"]
1696 BIT10,
1697 #[doc = "11-bit break detection"]
1698 BIT11,
1699}
1700impl LBDLW {
1701 #[allow(missing_docs)]
1702 #[doc(hidden)]
1703 #[inline]
1704 pub fn _bits(&self) -> bool {
1705 match *self {
1706 LBDLW::BIT10 => false,
1707 LBDLW::BIT11 => true,
1708 }
1709 }
1710}
1711#[doc = r" Proxy"]
1712pub struct _LBDLW<'a> {
1713 w: &'a mut W,
1714}
1715impl<'a> _LBDLW<'a> {
1716 #[doc = r" Writes `variant` to the field"]
1717 #[inline]
1718 pub fn variant(self, variant: LBDLW) -> &'a mut W {
1719 {
1720 self.bit(variant._bits())
1721 }
1722 }
1723 #[doc = "10-bit break detection"]
1724 #[inline]
1725 pub fn bit10(self) -> &'a mut W {
1726 self.variant(LBDLW::BIT10)
1727 }
1728 #[doc = "11-bit break detection"]
1729 #[inline]
1730 pub fn bit11(self) -> &'a mut W {
1731 self.variant(LBDLW::BIT11)
1732 }
1733 #[doc = r" Sets the field bit"]
1734 pub fn set_bit(self) -> &'a mut W {
1735 self.bit(true)
1736 }
1737 #[doc = r" Clears the field bit"]
1738 pub fn clear_bit(self) -> &'a mut W {
1739 self.bit(false)
1740 }
1741 #[doc = r" Writes raw bits to the field"]
1742 #[inline]
1743 pub fn bit(self, value: bool) -> &'a mut W {
1744 const MASK: bool = true;
1745 const OFFSET: u8 = 5;
1746 self.w.bits &= !((MASK as u32) << OFFSET);
1747 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1748 self.w
1749 }
1750}
1751#[doc = "Values that can be written to the field `ADDM7`"]
1752pub enum ADDM7W {
1753 #[doc = "4-bit address detection"]
1754 BIT4,
1755 #[doc = "7-bit address detection"]
1756 BIT7,
1757}
1758impl ADDM7W {
1759 #[allow(missing_docs)]
1760 #[doc(hidden)]
1761 #[inline]
1762 pub fn _bits(&self) -> bool {
1763 match *self {
1764 ADDM7W::BIT4 => false,
1765 ADDM7W::BIT7 => true,
1766 }
1767 }
1768}
1769#[doc = r" Proxy"]
1770pub struct _ADDM7W<'a> {
1771 w: &'a mut W,
1772}
1773impl<'a> _ADDM7W<'a> {
1774 #[doc = r" Writes `variant` to the field"]
1775 #[inline]
1776 pub fn variant(self, variant: ADDM7W) -> &'a mut W {
1777 {
1778 self.bit(variant._bits())
1779 }
1780 }
1781 #[doc = "4-bit address detection"]
1782 #[inline]
1783 pub fn bit4(self) -> &'a mut W {
1784 self.variant(ADDM7W::BIT4)
1785 }
1786 #[doc = "7-bit address detection"]
1787 #[inline]
1788 pub fn bit7(self) -> &'a mut W {
1789 self.variant(ADDM7W::BIT7)
1790 }
1791 #[doc = r" Sets the field bit"]
1792 pub fn set_bit(self) -> &'a mut W {
1793 self.bit(true)
1794 }
1795 #[doc = r" Clears the field bit"]
1796 pub fn clear_bit(self) -> &'a mut W {
1797 self.bit(false)
1798 }
1799 #[doc = r" Writes raw bits to the field"]
1800 #[inline]
1801 pub fn bit(self, value: bool) -> &'a mut W {
1802 const MASK: bool = true;
1803 const OFFSET: u8 = 4;
1804 self.w.bits &= !((MASK as u32) << OFFSET);
1805 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1806 self.w
1807 }
1808}
1809#[doc = r" Proxy"]
1810pub struct _ADDW<'a> {
1811 w: &'a mut W,
1812}
1813impl<'a> _ADDW<'a> {
1814 #[doc = r" Writes raw bits to the field"]
1815 #[inline]
1816 pub fn bits(self, value: u8) -> &'a mut W {
1817 const MASK: u8 = 255;
1818 const OFFSET: u8 = 24;
1819 self.w.bits &= !((MASK as u32) << OFFSET);
1820 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1821 self.w
1822 }
1823}
1824#[doc = "Values that can be written to the field `ABRMOD`"]
1825pub enum ABRMODW {
1826 #[doc = "Measurement of the start bit is used to detect the baud rate"]
1827 START,
1828 #[doc = "Falling edge to falling edge measurement"]
1829 EDGE,
1830 #[doc = "0x7F frame detection"]
1831 FRAME7F,
1832 #[doc = "0x55 frame detection"]
1833 FRAME55,
1834}
1835impl ABRMODW {
1836 #[allow(missing_docs)]
1837 #[doc(hidden)]
1838 #[inline]
1839 pub fn _bits(&self) -> u8 {
1840 match *self {
1841 ABRMODW::START => 0,
1842 ABRMODW::EDGE => 1,
1843 ABRMODW::FRAME7F => 2,
1844 ABRMODW::FRAME55 => 3,
1845 }
1846 }
1847}
1848#[doc = r" Proxy"]
1849pub struct _ABRMODW<'a> {
1850 w: &'a mut W,
1851}
1852impl<'a> _ABRMODW<'a> {
1853 #[doc = r" Writes `variant` to the field"]
1854 #[inline]
1855 pub fn variant(self, variant: ABRMODW) -> &'a mut W {
1856 {
1857 self.bits(variant._bits())
1858 }
1859 }
1860 #[doc = "Measurement of the start bit is used to detect the baud rate"]
1861 #[inline]
1862 pub fn start(self) -> &'a mut W {
1863 self.variant(ABRMODW::START)
1864 }
1865 #[doc = "Falling edge to falling edge measurement"]
1866 #[inline]
1867 pub fn edge(self) -> &'a mut W {
1868 self.variant(ABRMODW::EDGE)
1869 }
1870 #[doc = "0x7F frame detection"]
1871 #[inline]
1872 pub fn frame7f(self) -> &'a mut W {
1873 self.variant(ABRMODW::FRAME7F)
1874 }
1875 #[doc = "0x55 frame detection"]
1876 #[inline]
1877 pub fn frame55(self) -> &'a mut W {
1878 self.variant(ABRMODW::FRAME55)
1879 }
1880 #[doc = r" Writes raw bits to the field"]
1881 #[inline]
1882 pub fn bits(self, value: u8) -> &'a mut W {
1883 const MASK: u8 = 3;
1884 const OFFSET: u8 = 21;
1885 self.w.bits &= !((MASK as u32) << OFFSET);
1886 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1887 self.w
1888 }
1889}
1890impl R {
1891 #[doc = r" Value of the register as raw bits"]
1892 #[inline]
1893 pub fn bits(&self) -> u32 {
1894 self.bits
1895 }
1896 #[doc = "Bit 23 - Receiver timeout enable"]
1897 #[inline]
1898 pub fn rtoen(&self) -> RTOENR {
1899 RTOENR::_from({
1900 const MASK: bool = true;
1901 const OFFSET: u8 = 23;
1902 ((self.bits >> OFFSET) & MASK as u32) != 0
1903 })
1904 }
1905 #[doc = "Bit 20 - Auto baud rate enable"]
1906 #[inline]
1907 pub fn abren(&self) -> ABRENR {
1908 ABRENR::_from({
1909 const MASK: bool = true;
1910 const OFFSET: u8 = 20;
1911 ((self.bits >> OFFSET) & MASK as u32) != 0
1912 })
1913 }
1914 #[doc = "Bit 19 - Most significant bit first"]
1915 #[inline]
1916 pub fn msbfirst(&self) -> MSBFIRSTR {
1917 MSBFIRSTR::_from({
1918 const MASK: bool = true;
1919 const OFFSET: u8 = 19;
1920 ((self.bits >> OFFSET) & MASK as u32) != 0
1921 })
1922 }
1923 #[doc = "Bit 18 - Binary data inversion"]
1924 #[inline]
1925 pub fn datainv(&self) -> DATAINVR {
1926 DATAINVR::_from({
1927 const MASK: bool = true;
1928 const OFFSET: u8 = 18;
1929 ((self.bits >> OFFSET) & MASK as u32) != 0
1930 })
1931 }
1932 #[doc = "Bit 17 - TX pin active level inversion"]
1933 #[inline]
1934 pub fn txinv(&self) -> TXINVR {
1935 TXINVR::_from({
1936 const MASK: bool = true;
1937 const OFFSET: u8 = 17;
1938 ((self.bits >> OFFSET) & MASK as u32) != 0
1939 })
1940 }
1941 #[doc = "Bit 16 - RX pin active level inversion"]
1942 #[inline]
1943 pub fn rxinv(&self) -> RXINVR {
1944 RXINVR::_from({
1945 const MASK: bool = true;
1946 const OFFSET: u8 = 16;
1947 ((self.bits >> OFFSET) & MASK as u32) != 0
1948 })
1949 }
1950 #[doc = "Bit 15 - Swap TX/RX pins"]
1951 #[inline]
1952 pub fn swap(&self) -> SWAPR {
1953 SWAPR::_from({
1954 const MASK: bool = true;
1955 const OFFSET: u8 = 15;
1956 ((self.bits >> OFFSET) & MASK as u32) != 0
1957 })
1958 }
1959 #[doc = "Bit 14 - LIN mode enable"]
1960 #[inline]
1961 pub fn linen(&self) -> LINENR {
1962 LINENR::_from({
1963 const MASK: bool = true;
1964 const OFFSET: u8 = 14;
1965 ((self.bits >> OFFSET) & MASK as u32) != 0
1966 })
1967 }
1968 #[doc = "Bits 12:13 - STOP bits"]
1969 #[inline]
1970 pub fn stop(&self) -> STOPR {
1971 STOPR::_from({
1972 const MASK: u8 = 3;
1973 const OFFSET: u8 = 12;
1974 ((self.bits >> OFFSET) & MASK as u32) as u8
1975 })
1976 }
1977 #[doc = "Bit 11 - Clock enable"]
1978 #[inline]
1979 pub fn clken(&self) -> CLKENR {
1980 CLKENR::_from({
1981 const MASK: bool = true;
1982 const OFFSET: u8 = 11;
1983 ((self.bits >> OFFSET) & MASK as u32) != 0
1984 })
1985 }
1986 #[doc = "Bit 10 - Clock polarity"]
1987 #[inline]
1988 pub fn cpol(&self) -> CPOLR {
1989 CPOLR::_from({
1990 const MASK: bool = true;
1991 const OFFSET: u8 = 10;
1992 ((self.bits >> OFFSET) & MASK as u32) != 0
1993 })
1994 }
1995 #[doc = "Bit 9 - Clock phase"]
1996 #[inline]
1997 pub fn cpha(&self) -> CPHAR {
1998 CPHAR::_from({
1999 const MASK: bool = true;
2000 const OFFSET: u8 = 9;
2001 ((self.bits >> OFFSET) & MASK as u32) != 0
2002 })
2003 }
2004 #[doc = "Bit 8 - Last bit clock pulse"]
2005 #[inline]
2006 pub fn lbcl(&self) -> LBCLR {
2007 LBCLR::_from({
2008 const MASK: bool = true;
2009 const OFFSET: u8 = 8;
2010 ((self.bits >> OFFSET) & MASK as u32) != 0
2011 })
2012 }
2013 #[doc = "Bit 6 - LIN break detection interrupt enable"]
2014 #[inline]
2015 pub fn lbdie(&self) -> LBDIER {
2016 LBDIER::_from({
2017 const MASK: bool = true;
2018 const OFFSET: u8 = 6;
2019 ((self.bits >> OFFSET) & MASK as u32) != 0
2020 })
2021 }
2022 #[doc = "Bit 5 - LIN break detection length"]
2023 #[inline]
2024 pub fn lbdl(&self) -> LBDLR {
2025 LBDLR::_from({
2026 const MASK: bool = true;
2027 const OFFSET: u8 = 5;
2028 ((self.bits >> OFFSET) & MASK as u32) != 0
2029 })
2030 }
2031 #[doc = "Bit 4 - 7-bit Address Detection/4-bit Address Detection"]
2032 #[inline]
2033 pub fn addm7(&self) -> ADDM7R {
2034 ADDM7R::_from({
2035 const MASK: bool = true;
2036 const OFFSET: u8 = 4;
2037 ((self.bits >> OFFSET) & MASK as u32) != 0
2038 })
2039 }
2040 #[doc = "Bits 24:31 - Address of the USART node"]
2041 #[inline]
2042 pub fn add(&self) -> ADDR {
2043 let bits = {
2044 const MASK: u8 = 255;
2045 const OFFSET: u8 = 24;
2046 ((self.bits >> OFFSET) & MASK as u32) as u8
2047 };
2048 ADDR { bits }
2049 }
2050 #[doc = "Bits 21:22 - Auto baud rate mode"]
2051 #[inline]
2052 pub fn abrmod(&self) -> ABRMODR {
2053 ABRMODR::_from({
2054 const MASK: u8 = 3;
2055 const OFFSET: u8 = 21;
2056 ((self.bits >> OFFSET) & MASK as u32) as u8
2057 })
2058 }
2059}
2060impl W {
2061 #[doc = r" Reset value of the register"]
2062 #[inline]
2063 pub fn reset_value() -> W {
2064 W { bits: 0 }
2065 }
2066 #[doc = r" Writes raw bits to the register"]
2067 #[inline]
2068 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2069 self.bits = bits;
2070 self
2071 }
2072 #[doc = "Bit 23 - Receiver timeout enable"]
2073 #[inline]
2074 pub fn rtoen(&mut self) -> _RTOENW {
2075 _RTOENW { w: self }
2076 }
2077 #[doc = "Bit 20 - Auto baud rate enable"]
2078 #[inline]
2079 pub fn abren(&mut self) -> _ABRENW {
2080 _ABRENW { w: self }
2081 }
2082 #[doc = "Bit 19 - Most significant bit first"]
2083 #[inline]
2084 pub fn msbfirst(&mut self) -> _MSBFIRSTW {
2085 _MSBFIRSTW { w: self }
2086 }
2087 #[doc = "Bit 18 - Binary data inversion"]
2088 #[inline]
2089 pub fn datainv(&mut self) -> _DATAINVW {
2090 _DATAINVW { w: self }
2091 }
2092 #[doc = "Bit 17 - TX pin active level inversion"]
2093 #[inline]
2094 pub fn txinv(&mut self) -> _TXINVW {
2095 _TXINVW { w: self }
2096 }
2097 #[doc = "Bit 16 - RX pin active level inversion"]
2098 #[inline]
2099 pub fn rxinv(&mut self) -> _RXINVW {
2100 _RXINVW { w: self }
2101 }
2102 #[doc = "Bit 15 - Swap TX/RX pins"]
2103 #[inline]
2104 pub fn swap(&mut self) -> _SWAPW {
2105 _SWAPW { w: self }
2106 }
2107 #[doc = "Bit 14 - LIN mode enable"]
2108 #[inline]
2109 pub fn linen(&mut self) -> _LINENW {
2110 _LINENW { w: self }
2111 }
2112 #[doc = "Bits 12:13 - STOP bits"]
2113 #[inline]
2114 pub fn stop(&mut self) -> _STOPW {
2115 _STOPW { w: self }
2116 }
2117 #[doc = "Bit 11 - Clock enable"]
2118 #[inline]
2119 pub fn clken(&mut self) -> _CLKENW {
2120 _CLKENW { w: self }
2121 }
2122 #[doc = "Bit 10 - Clock polarity"]
2123 #[inline]
2124 pub fn cpol(&mut self) -> _CPOLW {
2125 _CPOLW { w: self }
2126 }
2127 #[doc = "Bit 9 - Clock phase"]
2128 #[inline]
2129 pub fn cpha(&mut self) -> _CPHAW {
2130 _CPHAW { w: self }
2131 }
2132 #[doc = "Bit 8 - Last bit clock pulse"]
2133 #[inline]
2134 pub fn lbcl(&mut self) -> _LBCLW {
2135 _LBCLW { w: self }
2136 }
2137 #[doc = "Bit 6 - LIN break detection interrupt enable"]
2138 #[inline]
2139 pub fn lbdie(&mut self) -> _LBDIEW {
2140 _LBDIEW { w: self }
2141 }
2142 #[doc = "Bit 5 - LIN break detection length"]
2143 #[inline]
2144 pub fn lbdl(&mut self) -> _LBDLW {
2145 _LBDLW { w: self }
2146 }
2147 #[doc = "Bit 4 - 7-bit Address Detection/4-bit Address Detection"]
2148 #[inline]
2149 pub fn addm7(&mut self) -> _ADDM7W {
2150 _ADDM7W { w: self }
2151 }
2152 #[doc = "Bits 24:31 - Address of the USART node"]
2153 #[inline]
2154 pub fn add(&mut self) -> _ADDW {
2155 _ADDW { w: self }
2156 }
2157 #[doc = "Bits 21:22 - Auto baud rate mode"]
2158 #[inline]
2159 pub fn abrmod(&mut self) -> _ABRMODW {
2160 _ABRMODW { w: self }
2161 }
2162}