stm32l4/stm32l4x5/tim16/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Update interrupt flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIFR {
11    ///0: No update occurred
12    NoUpdateOccurred = 0,
13    ///1: Update interrupt pending
14    UpdatePending = 1,
15}
16impl From<UIFR> for bool {
17    #[inline(always)]
18    fn from(variant: UIFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIF` reader - Update interrupt flag
23pub type UIF_R = crate::BitReader<UIFR>;
24impl UIF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIFR {
28        match self.bits {
29            false => UIFR::NoUpdateOccurred,
30            true => UIFR::UpdatePending,
31        }
32    }
33    ///No update occurred
34    #[inline(always)]
35    pub fn is_no_update_occurred(&self) -> bool {
36        *self == UIFR::NoUpdateOccurred
37    }
38    ///Update interrupt pending
39    #[inline(always)]
40    pub fn is_update_pending(&self) -> bool {
41        *self == UIFR::UpdatePending
42    }
43}
44/**Update interrupt flag
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum UIFW {
50    ///0: Clear flag
51    Clear = 0,
52}
53impl From<UIFW> for bool {
54    #[inline(always)]
55    fn from(variant: UIFW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `UIF` writer - Update interrupt flag
60pub type UIF_W<'a, REG> = crate::BitWriter0C<'a, REG, UIFW>;
61impl<'a, REG> UIF_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(UIFW::Clear)
69    }
70}
71/**Capture/compare %s interrupt flag
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum CC1IFR {
77    ///0: No campture/compare has been detected
78    NoMatch = 0,
79    ///1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
80    Match = 1,
81}
82impl From<CC1IFR> for bool {
83    #[inline(always)]
84    fn from(variant: CC1IFR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `CCIF(1-1)` reader - Capture/compare %s interrupt flag
89pub type CCIF_R = crate::BitReader<CC1IFR>;
90impl CCIF_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> CC1IFR {
94        match self.bits {
95            false => CC1IFR::NoMatch,
96            true => CC1IFR::Match,
97        }
98    }
99    ///No campture/compare has been detected
100    #[inline(always)]
101    pub fn is_no_match(&self) -> bool {
102        *self == CC1IFR::NoMatch
103    }
104    ///If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
105    #[inline(always)]
106    pub fn is_match(&self) -> bool {
107        *self == CC1IFR::Match
108    }
109}
110/**Capture/compare %s interrupt flag
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CC1IFW {
116    ///0: Clear flag
117    Clear = 0,
118}
119impl From<CC1IFW> for bool {
120    #[inline(always)]
121    fn from(variant: CC1IFW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `CCIF(1-1)` writer - Capture/compare %s interrupt flag
126pub type CCIF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1IFW>;
127impl<'a, REG> CCIF_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Clear flag
132    #[inline(always)]
133    pub fn clear(self) -> &'a mut crate::W<REG> {
134        self.variant(CC1IFW::Clear)
135    }
136}
137/**COM interrupt flag
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum COMIFR {
143    ///0: No COM event occurred
144    NoCom = 0,
145    ///1: COM interrupt pending
146    Com = 1,
147}
148impl From<COMIFR> for bool {
149    #[inline(always)]
150    fn from(variant: COMIFR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `COMIF` reader - COM interrupt flag
155pub type COMIF_R = crate::BitReader<COMIFR>;
156impl COMIF_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> COMIFR {
160        match self.bits {
161            false => COMIFR::NoCom,
162            true => COMIFR::Com,
163        }
164    }
165    ///No COM event occurred
166    #[inline(always)]
167    pub fn is_no_com(&self) -> bool {
168        *self == COMIFR::NoCom
169    }
170    ///COM interrupt pending
171    #[inline(always)]
172    pub fn is_com(&self) -> bool {
173        *self == COMIFR::Com
174    }
175}
176/**COM interrupt flag
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum COMIFW {
182    ///0: Clear flag
183    Clear = 0,
184}
185impl From<COMIFW> for bool {
186    #[inline(always)]
187    fn from(variant: COMIFW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `COMIF` writer - COM interrupt flag
192pub type COMIF_W<'a, REG> = crate::BitWriter0C<'a, REG, COMIFW>;
193impl<'a, REG> COMIF_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Clear flag
198    #[inline(always)]
199    pub fn clear(self) -> &'a mut crate::W<REG> {
200        self.variant(COMIFW::Clear)
201    }
202}
203/**Break interrupt flag
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum BIFR {
209    ///0: No break event occurred
210    NoTrigger = 0,
211    ///1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
212    Trigger = 1,
213}
214impl From<BIFR> for bool {
215    #[inline(always)]
216    fn from(variant: BIFR) -> Self {
217        variant as u8 != 0
218    }
219}
220///Field `BIF` reader - Break interrupt flag
221pub type BIF_R = crate::BitReader<BIFR>;
222impl BIF_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub const fn variant(&self) -> BIFR {
226        match self.bits {
227            false => BIFR::NoTrigger,
228            true => BIFR::Trigger,
229        }
230    }
231    ///No break event occurred
232    #[inline(always)]
233    pub fn is_no_trigger(&self) -> bool {
234        *self == BIFR::NoTrigger
235    }
236    ///An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
237    #[inline(always)]
238    pub fn is_trigger(&self) -> bool {
239        *self == BIFR::Trigger
240    }
241}
242/**Break interrupt flag
243
244Value on reset: 0*/
245#[cfg_attr(feature = "defmt", derive(defmt::Format))]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum BIFW {
248    ///0: Clear flag
249    Clear = 0,
250}
251impl From<BIFW> for bool {
252    #[inline(always)]
253    fn from(variant: BIFW) -> Self {
254        variant as u8 != 0
255    }
256}
257///Field `BIF` writer - Break interrupt flag
258pub type BIF_W<'a, REG> = crate::BitWriter0C<'a, REG, BIFW>;
259impl<'a, REG> BIF_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    ///Clear flag
264    #[inline(always)]
265    pub fn clear(self) -> &'a mut crate::W<REG> {
266        self.variant(BIFW::Clear)
267    }
268}
269/**Capture/Compare %s overcapture flag
270
271Value on reset: 0*/
272#[cfg_attr(feature = "defmt", derive(defmt::Format))]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum CC1OFR {
275    ///0: No overcapture has been detected
276    NoOvercapture = 0,
277    ///1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
278    Overcapture = 1,
279}
280impl From<CC1OFR> for bool {
281    #[inline(always)]
282    fn from(variant: CC1OFR) -> Self {
283        variant as u8 != 0
284    }
285}
286///Field `CCOF(1-1)` reader - Capture/Compare %s overcapture flag
287pub type CCOF_R = crate::BitReader<CC1OFR>;
288impl CCOF_R {
289    ///Get enumerated values variant
290    #[inline(always)]
291    pub const fn variant(&self) -> CC1OFR {
292        match self.bits {
293            false => CC1OFR::NoOvercapture,
294            true => CC1OFR::Overcapture,
295        }
296    }
297    ///No overcapture has been detected
298    #[inline(always)]
299    pub fn is_no_overcapture(&self) -> bool {
300        *self == CC1OFR::NoOvercapture
301    }
302    ///The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
303    #[inline(always)]
304    pub fn is_overcapture(&self) -> bool {
305        *self == CC1OFR::Overcapture
306    }
307}
308/**Capture/Compare %s overcapture flag
309
310Value on reset: 0*/
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum CC1OFW {
314    ///0: Clear flag
315    Clear = 0,
316}
317impl From<CC1OFW> for bool {
318    #[inline(always)]
319    fn from(variant: CC1OFW) -> Self {
320        variant as u8 != 0
321    }
322}
323///Field `CCOF(1-1)` writer - Capture/Compare %s overcapture flag
324pub type CCOF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1OFW>;
325impl<'a, REG> CCOF_W<'a, REG>
326where
327    REG: crate::Writable + crate::RegisterSpec,
328{
329    ///Clear flag
330    #[inline(always)]
331    pub fn clear(self) -> &'a mut crate::W<REG> {
332        self.variant(CC1OFW::Clear)
333    }
334}
335impl R {
336    ///Bit 0 - Update interrupt flag
337    #[inline(always)]
338    pub fn uif(&self) -> UIF_R {
339        UIF_R::new((self.bits & 1) != 0)
340    }
341    ///Capture/compare (1-1) interrupt flag
342    ///
343    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
344    #[inline(always)]
345    pub fn ccif(&self, n: u8) -> CCIF_R {
346        #[allow(clippy::no_effect)]
347        [(); 1][n as usize];
348        CCIF_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0)
349    }
350    ///Iterator for array of:
351    ///Capture/compare (1-1) interrupt flag
352    #[inline(always)]
353    pub fn ccif_iter(&self) -> impl Iterator<Item = CCIF_R> + '_ {
354        (0..1).map(move |n| CCIF_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0))
355    }
356    ///Bit 1 - Capture/compare 1 interrupt flag
357    #[inline(always)]
358    pub fn cc1if(&self) -> CCIF_R {
359        CCIF_R::new(((self.bits >> 1) & 1) != 0)
360    }
361    ///Bit 5 - COM interrupt flag
362    #[inline(always)]
363    pub fn comif(&self) -> COMIF_R {
364        COMIF_R::new(((self.bits >> 5) & 1) != 0)
365    }
366    ///Bit 7 - Break interrupt flag
367    #[inline(always)]
368    pub fn bif(&self) -> BIF_R {
369        BIF_R::new(((self.bits >> 7) & 1) != 0)
370    }
371    ///Capture/Compare (1-1) overcapture flag
372    ///
373    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
374    #[inline(always)]
375    pub fn ccof(&self, n: u8) -> CCOF_R {
376        #[allow(clippy::no_effect)]
377        [(); 1][n as usize];
378        CCOF_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0)
379    }
380    ///Iterator for array of:
381    ///Capture/Compare (1-1) overcapture flag
382    #[inline(always)]
383    pub fn ccof_iter(&self) -> impl Iterator<Item = CCOF_R> + '_ {
384        (0..1).map(move |n| CCOF_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0))
385    }
386    ///Bit 9 - Capture/Compare 1 overcapture flag
387    #[inline(always)]
388    pub fn cc1of(&self) -> CCOF_R {
389        CCOF_R::new(((self.bits >> 9) & 1) != 0)
390    }
391}
392impl core::fmt::Debug for R {
393    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
394        f.debug_struct("SR")
395            .field("cc1of", &self.cc1of())
396            .field("bif", &self.bif())
397            .field("comif", &self.comif())
398            .field("cc1if", &self.cc1if())
399            .field("uif", &self.uif())
400            .finish()
401    }
402}
403impl W {
404    ///Bit 0 - Update interrupt flag
405    #[inline(always)]
406    pub fn uif(&mut self) -> UIF_W<SRrs> {
407        UIF_W::new(self, 0)
408    }
409    ///Capture/compare (1-1) interrupt flag
410    ///
411    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
412    #[inline(always)]
413    pub fn ccif(&mut self, n: u8) -> CCIF_W<SRrs> {
414        #[allow(clippy::no_effect)]
415        [(); 1][n as usize];
416        CCIF_W::new(self, n * 0 + 1)
417    }
418    ///Bit 1 - Capture/compare 1 interrupt flag
419    #[inline(always)]
420    pub fn cc1if(&mut self) -> CCIF_W<SRrs> {
421        CCIF_W::new(self, 1)
422    }
423    ///Bit 5 - COM interrupt flag
424    #[inline(always)]
425    pub fn comif(&mut self) -> COMIF_W<SRrs> {
426        COMIF_W::new(self, 5)
427    }
428    ///Bit 7 - Break interrupt flag
429    #[inline(always)]
430    pub fn bif(&mut self) -> BIF_W<SRrs> {
431        BIF_W::new(self, 7)
432    }
433    ///Capture/Compare (1-1) overcapture flag
434    ///
435    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
436    #[inline(always)]
437    pub fn ccof(&mut self, n: u8) -> CCOF_W<SRrs> {
438        #[allow(clippy::no_effect)]
439        [(); 1][n as usize];
440        CCOF_W::new(self, n * 0 + 9)
441    }
442    ///Bit 9 - Capture/Compare 1 overcapture flag
443    #[inline(always)]
444    pub fn cc1of(&mut self) -> CCOF_W<SRrs> {
445        CCOF_W::new(self, 9)
446    }
447}
448/**status register
449
450You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
451
452See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#TIM16:SR)*/
453pub struct SRrs;
454impl crate::RegisterSpec for SRrs {
455    type Ux = u32;
456}
457///`read()` method returns [`sr::R`](R) reader structure
458impl crate::Readable for SRrs {}
459///`write(|w| ..)` method takes [`sr::W`](W) writer structure
460impl crate::Writable for SRrs {
461    type Safety = crate::Unsafe;
462    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x02a3;
463}
464///`reset()` method sets SR to value 0
465impl crate::Resettable for SRrs {}
stm32l4/stm32l4x5/tim16/sr.rs

stm32l4/stm32l4x5/tim16/
sr.rs
