stm32l4/stm32l4x5/dfsdm.rs
1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5 ch: [CH; 8],
6 flt: [FLT; 4],
7}
8impl RegisterBlock {
9 ///0x00..0x100 - DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers
10 #[inline(always)]
11 pub const fn ch(&self, n: usize) -> &CH {
12 &self.ch[n]
13 }
14 ///Iterator for array of:
15 ///0x00..0x100 - DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers
16 #[inline(always)]
17 pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
18 self.ch.iter()
19 }
20 ///0x100..0x300 - Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR
21 #[inline(always)]
22 pub const fn flt(&self, n: usize) -> &FLT {
23 &self.flt[n]
24 }
25 ///Iterator for array of:
26 ///0x100..0x300 - Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR
27 #[inline(always)]
28 pub fn flt_iter(&self) -> impl Iterator<Item = &FLT> {
29 self.flt.iter()
30 }
31}
32///DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers
33pub use self::ch::CH;
34///Cluster
35///DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers
36pub mod ch;
37///Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR
38pub use self::flt::FLT;
39///Cluster
40///Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR
41pub mod flt;