stm32l4 0.16.0

/*!Peripheral access API for STM32L4X3 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))

You can find an overview of the generated API [here].

API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.

[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
    fn WWDG();
    fn PVD();
    fn TAMP_STAMP();
    fn RTC_WKUP();
    fn FLASH();
    fn RCC();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2();
    fn EXTI3();
    fn EXTI4();
    fn DMA1_CH1();
    fn DMA1_CH2();
    fn DMA1_CH3();
    fn DMA1_CH4();
    fn DMA1_CH5();
    fn DMA1_CH6();
    fn DMA1_CH7();
    fn ADC1();
    fn CAN1_TX();
    fn CAN1_RX0();
    fn CAN1_RX1();
    fn CAN1_SCE();
    fn EXTI9_5();
    fn TIM15();
    fn TIM16();
    fn TIM1_CC();
    fn TIM2();
    fn I2C1_EV();
    fn I2C1_ER();
    fn I2C2_EV();
    fn I2C2_ER();
    fn SPI1();
    fn SPI2();
    fn USART1();
    fn USART2();
    fn USART3();
    fn EXTI15_10();
    fn RTC_ALARM();
    fn ADC3();
    fn SDMMC();
    fn SPI3();
    fn TIM6_DAC();
    fn TIM7();
    fn DMA2_CH1();
    fn DMA2_CH2();
    fn DMA2_CH3();
    fn DMA2_CH4();
    fn DMA2_CH5();
    fn COMP();
    fn LPTIM1();
    fn LPTIM2();
    fn USB_FS();
    fn DMA2_CH6();
    fn DMA2_CH7();
    fn I2C3_EV();
    fn I2C3_ER();
    fn SAI1();
    fn SWPMI1();
    fn TSC();
    fn LCD();
    fn RNG();
    fn CRS();
    fn FPU();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 82] = [
    Vector { _handler: WWDG },
    Vector { _handler: PVD },
    Vector {
        _handler: TAMP_STAMP,
    },
    Vector { _handler: RTC_WKUP },
    Vector { _handler: FLASH },
    Vector { _handler: RCC },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector { _handler: EXTI2 },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector { _handler: DMA1_CH1 },
    Vector { _handler: DMA1_CH2 },
    Vector { _handler: DMA1_CH3 },
    Vector { _handler: DMA1_CH4 },
    Vector { _handler: DMA1_CH5 },
    Vector { _handler: DMA1_CH6 },
    Vector { _handler: DMA1_CH7 },
    Vector { _handler: ADC1 },
    Vector { _handler: CAN1_TX },
    Vector { _handler: CAN1_RX0 },
    Vector { _handler: CAN1_RX1 },
    Vector { _handler: CAN1_SCE },
    Vector { _handler: EXTI9_5 },
    Vector { _handler: TIM15 },
    Vector { _handler: TIM16 },
    Vector { _reserved: 0 },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: I2C1_EV },
    Vector { _handler: I2C1_ER },
    Vector { _handler: I2C2_EV },
    Vector { _handler: I2C2_ER },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: USART1 },
    Vector { _handler: USART2 },
    Vector { _handler: USART3 },
    Vector {
        _handler: EXTI15_10,
    },
    Vector {
        _handler: RTC_ALARM,
    },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: ADC3 },
    Vector { _reserved: 0 },
    Vector { _handler: SDMMC },
    Vector { _reserved: 0 },
    Vector { _handler: SPI3 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: TIM6_DAC },
    Vector { _handler: TIM7 },
    Vector { _handler: DMA2_CH1 },
    Vector { _handler: DMA2_CH2 },
    Vector { _handler: DMA2_CH3 },
    Vector { _handler: DMA2_CH4 },
    Vector { _handler: DMA2_CH5 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: COMP },
    Vector { _handler: LPTIM1 },
    Vector { _handler: LPTIM2 },
    Vector { _handler: USB_FS },
    Vector { _handler: DMA2_CH6 },
    Vector { _handler: DMA2_CH7 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: I2C3_EV },
    Vector { _handler: I2C3_ER },
    Vector { _handler: SAI1 },
    Vector { _reserved: 0 },
    Vector { _handler: SWPMI1 },
    Vector { _handler: TSC },
    Vector { _handler: LCD },
    Vector { _handler: RNG },
    Vector { _handler: CRS },
    Vector { _handler: FPU },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///0 - Window Watchdog interrupt
    WWDG = 0,
    ///1 - PVD through EXTI line detection
    PVD = 1,
    ///2 - Tamper and TimeStamp interrupts
    TAMP_STAMP = 2,
    ///3 - RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts
    RTC_WKUP = 3,
    ///4 - Flash global interrupt
    FLASH = 4,
    ///5 - RCC global interrupt
    RCC = 5,
    ///6 - EXTI Line 0 interrupt
    EXTI0 = 6,
    ///7 - EXTI Line 1 interrupt
    EXTI1 = 7,
    ///8 - EXTI Line 2 interrupt
    EXTI2 = 8,
    ///9 - EXTI Line 3 interrupt
    EXTI3 = 9,
    ///10 - EXTI Line4 interrupt
    EXTI4 = 10,
    ///11 - DMA1 Channel1 global interrupt
    DMA1_CH1 = 11,
    ///12 - DMA1 Channel2 global interrupt
    DMA1_CH2 = 12,
    ///13 - DMA1 Channel3 interrupt
    DMA1_CH3 = 13,
    ///14 - DMA1 Channel4 interrupt
    DMA1_CH4 = 14,
    ///15 - DMA1 Channel5 interrupt
    DMA1_CH5 = 15,
    ///16 - DMA1 Channel6 interrupt
    DMA1_CH6 = 16,
    ///17 - DMA1 Channel 7 interrupt
    DMA1_CH7 = 17,
    ///18 - ADC1 and ADC2 global interrupt
    ADC1 = 18,
    ///19 - CAN1 TX interrupts
    CAN1_TX = 19,
    ///20 - CAN1 RX0 interrupts
    CAN1_RX0 = 20,
    ///21 - CAN1 RX1 interrupts
    CAN1_RX1 = 21,
    ///22 - CAN1 SCE interrupt
    CAN1_SCE = 22,
    ///23 - EXTI Line5 to Line9 interrupts
    EXTI9_5 = 23,
    ///24 - Timer 15 global interrupt
    TIM15 = 24,
    ///25 - Timer 16 global interrupt
    TIM16 = 25,
    ///27 - TIM1 Capture Compare interrupt
    TIM1_CC = 27,
    ///28 - TIM2 global interrupt
    TIM2 = 28,
    ///31 - I2C1 event interrupt
    I2C1_EV = 31,
    ///32 - I2C1 error interrupt
    I2C1_ER = 32,
    ///33 - I2C2 event interrupt
    I2C2_EV = 33,
    ///34 - I2C2 error interrupt
    I2C2_ER = 34,
    ///35 - SPI1 global interrupt
    SPI1 = 35,
    ///36 - SPI2 global interrupt
    SPI2 = 36,
    ///37 - USART1 global interrupt
    USART1 = 37,
    ///38 - USART2 global interrupt
    USART2 = 38,
    ///39 - USART3 global interrupt
    USART3 = 39,
    ///40 - EXTI Lines 10 to 15 interrupts
    EXTI15_10 = 40,
    ///41 - RTC alarms through EXTI line 18 interrupts
    RTC_ALARM = 41,
    ///47 - ADC3 global Interrupt
    ADC3 = 47,
    ///49 - SDMMC global Interrupt
    SDMMC = 49,
    ///51 - SPI3 global Interrupt
    SPI3 = 51,
    ///54 - TIM6 global and DAC1 and 2 underrun error interrupts
    TIM6_DAC = 54,
    ///55 - TIM7 global interrupt
    TIM7 = 55,
    ///56 - DMA2 Channel 1 global Interrupt
    DMA2_CH1 = 56,
    ///57 - DMA2 Channel 2 global Interrupt
    DMA2_CH2 = 57,
    ///58 - DMA2 Channel 3 global Interrupt
    DMA2_CH3 = 58,
    ///59 - DMA2 Channel 4 global Interrupt
    DMA2_CH4 = 59,
    ///60 - DMA2 Channel 5 global Interrupt
    DMA2_CH5 = 60,
    ///64 - COMP1 and COMP2 interrupts
    COMP = 64,
    ///65 - LP TIM1 interrupt
    LPTIM1 = 65,
    ///66 - LP TIM2 interrupt
    LPTIM2 = 66,
    ///67 - USB event interrupt through EXTI
    USB_FS = 67,
    ///68 - DMA2 Channel 6 global Interrupt
    DMA2_CH6 = 68,
    ///69 - DMA2 Channel 7 global Interrupt
    DMA2_CH7 = 69,
    ///72 - I2C3 event interrupt
    I2C3_EV = 72,
    ///73 - I2C3 error interrupt
    I2C3_ER = 73,
    ///74 - SAI1 global interrupt
    SAI1 = 74,
    ///76 - SWPMI1 global interrupt
    SWPMI1 = 76,
    ///77 - TSC global interrupt
    TSC = 77,
    ///78 - LCD global interrupt
    LCD = 78,
    ///79 - RNG global interrupt
    RNG = 79,
    ///80 - CRS global interrupt
    CRS = 80,
    ///81 - Floating point unit interrupt
    FPU = 81,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#DAC)
pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for DAC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC").finish()
    }
}
///Digital-to-analog converter
pub mod dac;
///Direct memory access controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#DMA1)
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA1").finish()
    }
}
///Direct memory access controller
pub mod dma1;
///Direct memory access controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#DMA1)
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA2").finish()
    }
}
///Direct memory access controller
pub use self::dma1 as dma2;
///Cyclic redundancy check calculation unit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#CRC)
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC").finish()
    }
}
///Cyclic redundancy check calculation unit
pub mod crc;
///Liquid crystal display controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#LCD)
pub type LCD = crate::Periph<lcd::RegisterBlock, 0x4000_2400>;
impl core::fmt::Debug for LCD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LCD").finish()
    }
}
///Liquid crystal display controller
pub mod lcd;
///Touch sensing controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TSC)
pub type TSC = crate::Periph<tsc::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for TSC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TSC").finish()
    }
}
///Touch sensing controller
pub mod tsc;
///Independent watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#IWDG)
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG").finish()
    }
}
///Independent watchdog
pub mod iwdg;
///System window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#WWDG)
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WWDG").finish()
    }
}
///System window watchdog
pub mod wwdg;
///Comparator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#COMP)
pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0200>;
impl core::fmt::Debug for COMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("COMP").finish()
    }
}
///Comparator
pub mod comp;
///Firewall
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#FIREWALL)
pub type FIREWALL = crate::Periph<firewall::RegisterBlock, 0x4001_1c00>;
impl core::fmt::Debug for FIREWALL {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FIREWALL").finish()
    }
}
///Firewall
pub mod firewall;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#I2C1)
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
///Inter-integrated circuit
pub mod i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#I2C1)
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#I2C1)
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c3;
///Flash
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#FLASH)
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for FLASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FLASH").finish()
    }
}
///Flash
pub mod flash;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#RCC)
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RCC").finish()
    }
}
///Reset and clock control
pub mod rcc;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#PWR)
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWR").finish()
    }
}
///Power control
pub mod pwr;
///System configuration controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SYSCFG)
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCFG").finish()
    }
}
///System configuration controller
pub mod syscfg;
///Random number generator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#RNG)
pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
impl core::fmt::Debug for RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG").finish()
    }
}
///Random number generator
pub mod rng;
///Advanced encryption standard hardware accelerator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#AES)
pub type AES = crate::Periph<aes::RegisterBlock, 0x5006_0000>;
impl core::fmt::Debug for AES {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AES").finish()
    }
}
///Advanced encryption standard hardware accelerator
pub mod aes;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#ADC1)
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5004_0000>;
impl core::fmt::Debug for ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc1;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#ADC1)
pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5004_0100>;
impl core::fmt::Debug for ADC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC2").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc2;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#ADC1)
pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x5004_0200>;
impl core::fmt::Debug for ADC3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC3").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc3;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#ADC123_Common)
pub type ADC123_COMMON = crate::Periph<adc123_common::RegisterBlock, 0x5004_0300>;
impl core::fmt::Debug for ADC123_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC123_COMMON").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc123_common;
///ADC common registers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#ADC_Common)
pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x5004_0300>;
impl core::fmt::Debug for ADC_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC_COMMON").finish()
    }
}
///ADC common registers
pub mod adc_common;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#GPIOA)
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOA").finish()
    }
}
///General-purpose I/Os
pub mod gpioa;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#GPIOB)
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
impl core::fmt::Debug for GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOB").finish()
    }
}
///General-purpose I/Os
pub mod gpiob;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#GPIOC)
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
impl core::fmt::Debug for GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOC").finish()
    }
}
///General-purpose I/Os
pub mod gpioc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#GPIOC)
pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
impl core::fmt::Debug for GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOD").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiod;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#GPIOC)
pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
impl core::fmt::Debug for GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOE").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpioe;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#GPIOC)
pub type GPIOH = crate::Periph<gpioc::RegisterBlock, 0x4800_1c00>;
impl core::fmt::Debug for GPIOH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOH").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpioh;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SAI1)
pub type SAI1 = crate::Periph<sai1::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for SAI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI1").finish()
    }
}
///Serial audio interface
pub mod sai1;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TIM2)
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM2").finish()
    }
}
///General-purpose-timers
pub mod tim2;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TIM15)
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM15").finish()
    }
}
///General purpose timers
pub mod tim15;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TIM16)
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM16").finish()
    }
}
///General purpose timers
pub mod tim16;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TIM1)
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM1").finish()
    }
}
///Advanced-timers
pub mod tim1;
///Basic-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TIM6)
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM6").finish()
    }
}
///Basic-timers
pub mod tim6;
///Basic-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#TIM6)
pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM7").finish()
    }
}
///Basic-timers
pub use self::tim6 as tim7;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#LPTIM1)
pub type LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x4000_7c00>;
impl core::fmt::Debug for LPTIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM1").finish()
    }
}
///Low power timer
pub mod lptim1;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#LPTIM1)
pub type LPTIM2 = crate::Periph<lptim1::RegisterBlock, 0x4000_9400>;
impl core::fmt::Debug for LPTIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM2").finish()
    }
}
///Low power timer
pub use self::lptim1 as lptim2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#USART1)
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#USART1)
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#USART1)
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#LPUART1)
pub type LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for LPUART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPUART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod lpuart1;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SPI1)
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub mod spi1;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SPI1)
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi2;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SPI1)
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi3;
///Secure digital input/output interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SDMMC)
pub type SDMMC = crate::Periph<sdmmc::RegisterBlock, 0x4001_2800>;
impl core::fmt::Debug for SDMMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDMMC").finish()
    }
}
///Secure digital input/output interface
pub mod sdmmc;
///External interrupt/event controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#EXTI)
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTI").finish()
    }
}
///External interrupt/event controller
pub mod exti;
///Voltage reference buffer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#VREFBUF)
pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x4001_0030>;
impl core::fmt::Debug for VREFBUF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("VREFBUF").finish()
    }
}
///Voltage reference buffer
pub mod vrefbuf;
///Controller area network
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#CAN1)
pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for CAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CAN1").finish()
    }
}
///Controller area network
pub mod can1;
///Real-time clock
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#RTC)
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC").finish()
    }
}
///Real-time clock
pub mod rtc;
///Single Wire Protocol Master Interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#SWPMI1)
pub type SWPMI1 = crate::Periph<swpmi1::RegisterBlock, 0x4000_8800>;
impl core::fmt::Debug for SWPMI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SWPMI1").finish()
    }
}
///Single Wire Protocol Master Interface
pub mod swpmi1;
///Operational amplifiers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#OPAMP)
pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for OPAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPAMP").finish()
    }
}
///Operational amplifiers
pub mod opamp;
///Clock recovery system
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#CRS)
pub type CRS = crate::Periph<crs::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for CRS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRS").finish()
    }
}
///Clock recovery system
pub mod crs;
///Universal serial bus full-speed device interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#USB)
pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_6800>;
impl core::fmt::Debug for USB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB").finish()
    }
}
///Universal serial bus full-speed device interface
pub mod usb;
///MCU debug component
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x3.html#DBGMCU)
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for DBGMCU {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DBGMCU").finish()
    }
}
///MCU debug component
pub mod dbgmcu;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///DAC
    pub DAC: DAC,
    ///DMA1
    pub DMA1: DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///CRC
    pub CRC: CRC,
    ///LCD
    pub LCD: LCD,
    ///TSC
    pub TSC: TSC,
    ///IWDG
    pub IWDG: IWDG,
    ///WWDG
    pub WWDG: WWDG,
    ///COMP
    pub COMP: COMP,
    ///FIREWALL
    pub FIREWALL: FIREWALL,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C2
    pub I2C2: I2C2,
    ///I2C3
    pub I2C3: I2C3,
    ///FLASH
    pub FLASH: FLASH,
    ///RCC
    pub RCC: RCC,
    ///PWR
    pub PWR: PWR,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///RNG
    pub RNG: RNG,
    ///AES
    pub AES: AES,
    ///ADC1
    pub ADC1: ADC1,
    ///ADC2
    pub ADC2: ADC2,
    ///ADC3
    pub ADC3: ADC3,
    ///ADC123_Common
    pub ADC123_COMMON: ADC123_COMMON,
    ///ADC_Common
    pub ADC_COMMON: ADC_COMMON,
    ///GPIOA
    pub GPIOA: GPIOA,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOH
    pub GPIOH: GPIOH,
    ///SAI1
    pub SAI1: SAI1,
    ///TIM2
    pub TIM2: TIM2,
    ///TIM15
    pub TIM15: TIM15,
    ///TIM16
    pub TIM16: TIM16,
    ///TIM1
    pub TIM1: TIM1,
    ///TIM6
    pub TIM6: TIM6,
    ///TIM7
    pub TIM7: TIM7,
    ///LPTIM1
    pub LPTIM1: LPTIM1,
    ///LPTIM2
    pub LPTIM2: LPTIM2,
    ///USART1
    pub USART1: USART1,
    ///USART2
    pub USART2: USART2,
    ///USART3
    pub USART3: USART3,
    ///LPUART1
    pub LPUART1: LPUART1,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI2
    pub SPI2: SPI2,
    ///SPI3
    pub SPI3: SPI3,
    ///SDMMC
    pub SDMMC: SDMMC,
    ///EXTI
    pub EXTI: EXTI,
    ///VREFBUF
    pub VREFBUF: VREFBUF,
    ///CAN1
    pub CAN1: CAN1,
    ///RTC
    pub RTC: RTC,
    ///SWPMI1
    pub SWPMI1: SWPMI1,
    ///OPAMP
    pub OPAMP: OPAMP,
    ///CRS
    pub CRS: CRS,
    ///USB
    pub USB: USB,
    ///DBGMCU
    pub DBGMCU: DBGMCU,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            DAC: DAC::steal(),
            DMA1: DMA1::steal(),
            DMA2: DMA2::steal(),
            CRC: CRC::steal(),
            LCD: LCD::steal(),
            TSC: TSC::steal(),
            IWDG: IWDG::steal(),
            WWDG: WWDG::steal(),
            COMP: COMP::steal(),
            FIREWALL: FIREWALL::steal(),
            I2C1: I2C1::steal(),
            I2C2: I2C2::steal(),
            I2C3: I2C3::steal(),
            FLASH: FLASH::steal(),
            RCC: RCC::steal(),
            PWR: PWR::steal(),
            SYSCFG: SYSCFG::steal(),
            RNG: RNG::steal(),
            AES: AES::steal(),
            ADC1: ADC1::steal(),
            ADC2: ADC2::steal(),
            ADC3: ADC3::steal(),
            ADC123_COMMON: ADC123_COMMON::steal(),
            ADC_COMMON: ADC_COMMON::steal(),
            GPIOA: GPIOA::steal(),
            GPIOB: GPIOB::steal(),
            GPIOC: GPIOC::steal(),
            GPIOD: GPIOD::steal(),
            GPIOE: GPIOE::steal(),
            GPIOH: GPIOH::steal(),
            SAI1: SAI1::steal(),
            TIM2: TIM2::steal(),
            TIM15: TIM15::steal(),
            TIM16: TIM16::steal(),
            TIM1: TIM1::steal(),
            TIM6: TIM6::steal(),
            TIM7: TIM7::steal(),
            LPTIM1: LPTIM1::steal(),
            LPTIM2: LPTIM2::steal(),
            USART1: USART1::steal(),
            USART2: USART2::steal(),
            USART3: USART3::steal(),
            LPUART1: LPUART1::steal(),
            SPI1: SPI1::steal(),
            SPI2: SPI2::steal(),
            SPI3: SPI3::steal(),
            SDMMC: SDMMC::steal(),
            EXTI: EXTI::steal(),
            VREFBUF: VREFBUF::steal(),
            CAN1: CAN1::steal(),
            RTC: RTC::steal(),
            SWPMI1: SWPMI1::steal(),
            OPAMP: OPAMP::steal(),
            CRS: CRS::steal(),
            USB: USB::steal(),
            DBGMCU: DBGMCU::steal(),
        }
    }
}