RegisterBlock

stm32l4_hal::stm32::dfsdm

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 100 fields
    pub chcfg0r1: CHCFG0R1,
    pub chcfg0r2: CHCFG0R2,
    pub awscd0r: AWSCD0R,
    pub chwdat0r: CHWDAT0R,
    pub chdatin0r: CHDATIN0R,
    pub chcfg1r1: CHCFG1R1,
    pub chcfg1r2: CHCFG1R2,
    pub awscd1r: AWSCD1R,
    pub chwdat1r: CHWDAT1R,
    pub chdatin1r: CHDATIN1R,
    pub chcfg2r1: CHCFG2R1,
    pub chcfg2r2: CHCFG2R2,
    pub awscd2r: AWSCD2R,
    pub chwdat2r: CHWDAT2R,
    pub chdatin2r: CHDATIN2R,
    pub chcfg3r1: CHCFG3R1,
    pub chcfg3r2: CHCFG3R2,
    pub awscd3r: AWSCD3R,
    pub chwdat3r: CHWDAT3R,
    pub chdatin3r: CHDATIN3R,
    pub chcfg4r1: CHCFG4R1,
    pub chcfg4r2: CHCFG4R2,
    pub awscd4r: AWSCD4R,
    pub chwdat4r: CHWDAT4R,
    pub chdatin4r: CHDATIN4R,
    pub chcfg5r1: CHCFG5R1,
    pub chcfg5r2: CHCFG5R2,
    pub awscd5r: AWSCD5R,
    pub chwdat5r: CHWDAT5R,
    pub chdatin5r: CHDATIN5R,
    pub chcfg6r1: CHCFG6R1,
    pub chcfg6r2: CHCFG6R2,
    pub awscd6r: AWSCD6R,
    pub chwdat6r: CHWDAT6R,
    pub chdatin6r: CHDATIN6R,
    pub chcfg7r1: CHCFG7R1,
    pub chcfg7r2: CHCFG7R2,
    pub awscd7r: AWSCD7R,
    pub chwdat7r: CHWDAT7R,
    pub chdatin7r: CHDATIN7R,
    pub dfsdm0_cr1: DFSDM0_CR1,
    pub dfsdm0_cr2: DFSDM0_CR2,
    pub dfsdm0_isr: DFSDM0_ISR,
    pub dfsdm0_icr: DFSDM0_ICR,
    pub dfsdm0_jchgr: DFSDM0_JCHGR,
    pub dfsdm0_fcr: DFSDM0_FCR,
    pub dfsdm0_jdatar: DFSDM0_JDATAR,
    pub dfsdm0_rdatar: DFSDM0_RDATAR,
    pub dfsdm0_awhtr: DFSDM0_AWHTR,
    pub dfsdm0_awltr: DFSDM0_AWLTR,
    pub dfsdm0_awsr: DFSDM0_AWSR,
    pub dfsdm0_awcfr: DFSDM0_AWCFR,
    pub dfsdm0_exmax: DFSDM0_EXMAX,
    pub dfsdm0_exmin: DFSDM0_EXMIN,
    pub dfsdm0_cnvtimr: DFSDM0_CNVTIMR,
    pub dfsdm1_cr1: DFSDM1_CR1,
    pub dfsdm1_cr2: DFSDM1_CR2,
    pub dfsdm1_isr: DFSDM1_ISR,
    pub dfsdm1_icr: DFSDM1_ICR,
    pub dfsdm1_jchgr: DFSDM1_JCHGR,
    pub dfsdm1_fcr: DFSDM1_FCR,
    pub dfsdm1_jdatar: DFSDM1_JDATAR,
    pub dfsdm1_rdatar: DFSDM1_RDATAR,
    pub dfsdm1_awhtr: DFSDM1_AWHTR,
    pub dfsdm1_awltr: DFSDM1_AWLTR,
    pub dfsdm1_awsr: DFSDM1_AWSR,
    pub dfsdm1_awcfr: DFSDM1_AWCFR,
    pub dfsdm1_exmax: DFSDM1_EXMAX,
    pub dfsdm1_exmin: DFSDM1_EXMIN,
    pub dfsdm1_cnvtimr: DFSDM1_CNVTIMR,
    pub dfsdm2_cr1: DFSDM2_CR1,
    pub dfsdm2_cr2: DFSDM2_CR2,
    pub dfsdm2_isr: DFSDM2_ISR,
    pub dfsdm2_icr: DFSDM2_ICR,
    pub dfsdm2_jchgr: DFSDM2_JCHGR,
    pub dfsdm2_fcr: DFSDM2_FCR,
    pub dfsdm2_jdatar: DFSDM2_JDATAR,
    pub dfsdm2_rdatar: DFSDM2_RDATAR,
    pub dfsdm2_awhtr: DFSDM2_AWHTR,
    pub dfsdm2_awltr: DFSDM2_AWLTR,
    pub dfsdm2_awsr: DFSDM2_AWSR,
    pub dfsdm2_awcfr: DFSDM2_AWCFR,
    pub dfsdm2_exmax: DFSDM2_EXMAX,
    pub dfsdm2_exmin: DFSDM2_EXMIN,
    pub dfsdm2_cnvtimr: DFSDM2_CNVTIMR,
    pub dfsdm3_cr1: DFSDM3_CR1,
    pub dfsdm3_cr2: DFSDM3_CR2,
    pub dfsdm3_isr: DFSDM3_ISR,
    pub dfsdm3_icr: DFSDM3_ICR,
    pub dfsdm3_jchgr: DFSDM3_JCHGR,
    pub dfsdm3_fcr: DFSDM3_FCR,
    pub dfsdm3_jdatar: DFSDM3_JDATAR,
    pub dfsdm3_rdatar: DFSDM3_RDATAR,
    pub dfsdm3_awhtr: DFSDM3_AWHTR,
    pub dfsdm3_awltr: DFSDM3_AWLTR,
    pub dfsdm3_awsr: DFSDM3_AWSR,
    pub dfsdm3_awcfr: DFSDM3_AWCFR,
    pub dfsdm3_exmax: DFSDM3_EXMAX,
    pub dfsdm3_exmin: DFSDM3_EXMIN,
    pub dfsdm3_cnvtimr: DFSDM3_CNVTIMR,
    /* private fields */

}
Expand description

Register block

Fields§

§chcfg0r1: CHCFG0R1

0x00 - channel configuration y register

§chcfg0r2: CHCFG0R2

0x04 - channel configuration y register

§awscd0r: AWSCD0R

0x08 - analog watchdog and short-circuit detector register

§chwdat0r: CHWDAT0R

0x0c - channel watchdog filter data register

§chdatin0r: CHDATIN0R

0x10 - channel data input register

§chcfg1r1: CHCFG1R1

0x20 - CHCFG1R1

§chcfg1r2: CHCFG1R2

0x24 - CHCFG1R2

§awscd1r: AWSCD1R

0x28 - AWSCD1R

§chwdat1r: CHWDAT1R

0x2c - CHWDAT1R

§chdatin1r: CHDATIN1R

0x30 - CHDATIN1R

§chcfg2r1: CHCFG2R1

0x40 - CHCFG2R1

§chcfg2r2: CHCFG2R2

0x44 - CHCFG2R2

§awscd2r: AWSCD2R

0x48 - AWSCD2R

§chwdat2r: CHWDAT2R

0x4c - CHWDAT2R

§chdatin2r: CHDATIN2R

0x50 - CHDATIN2R

§chcfg3r1: CHCFG3R1

0x60 - CHCFG3R1

§chcfg3r2: CHCFG3R2

0x64 - CHCFG3R2

§awscd3r: AWSCD3R

0x68 - AWSCD3R

§chwdat3r: CHWDAT3R

0x6c - CHWDAT3R

§chdatin3r: CHDATIN3R

0x70 - CHDATIN3R

§chcfg4r1: CHCFG4R1

0x80 - CHCFG4R1

§chcfg4r2: CHCFG4R2

0x84 - CHCFG4R2

§awscd4r: AWSCD4R

0x88 - AWSCD4R

§chwdat4r: CHWDAT4R

0x8c - CHWDAT4R

§chdatin4r: CHDATIN4R

0x90 - CHDATIN4R

§chcfg5r1: CHCFG5R1

0xa0 - CHCFG5R1

§chcfg5r2: CHCFG5R2

0xa4 - CHCFG5R2

§awscd5r: AWSCD5R

0xa8 - AWSCD5R

§chwdat5r: CHWDAT5R

0xac - CHWDAT5R

§chdatin5r: CHDATIN5R

0xb0 - CHDATIN5R

§chcfg6r1: CHCFG6R1

0xc0 - CHCFG6R1

§chcfg6r2: CHCFG6R2

0xc4 - CHCFG6R2

§awscd6r: AWSCD6R

0xc8 - AWSCD6R

§chwdat6r: CHWDAT6R

0xcc - CHWDAT6R

§chdatin6r: CHDATIN6R

0xd0 - CHDATIN6R

§chcfg7r1: CHCFG7R1

0xe0 - CHCFG7R1

§chcfg7r2: CHCFG7R2

0xe4 - CHCFG7R2

§awscd7r: AWSCD7R

0xe8 - AWSCD7R

§chwdat7r: CHWDAT7R

0xec - CHWDAT7R

§chdatin7r: CHDATIN7R

0xf0 - CHDATIN7R

§dfsdm0_cr1: DFSDM0_CR1

0x100 - control register 1

§dfsdm0_cr2: DFSDM0_CR2

0x104 - control register 2

§dfsdm0_isr: DFSDM0_ISR

0x108 - interrupt and status register

§dfsdm0_icr: DFSDM0_ICR

0x10c - interrupt flag clear register

§dfsdm0_jchgr: DFSDM0_JCHGR

0x110 - injected channel group selection register

§dfsdm0_fcr: DFSDM0_FCR

0x114 - filter control register

§dfsdm0_jdatar: DFSDM0_JDATAR

0x118 - data register for injected group

§dfsdm0_rdatar: DFSDM0_RDATAR

0x11c - data register for the regular channel

§dfsdm0_awhtr: DFSDM0_AWHTR

0x120 - analog watchdog high threshold register

§dfsdm0_awltr: DFSDM0_AWLTR

0x124 - analog watchdog low threshold register

§dfsdm0_awsr: DFSDM0_AWSR

0x128 - analog watchdog status register

§dfsdm0_awcfr: DFSDM0_AWCFR

0x12c - analog watchdog clear flag register

§dfsdm0_exmax: DFSDM0_EXMAX

0x130 - Extremes detector maximum register

§dfsdm0_exmin: DFSDM0_EXMIN

0x134 - Extremes detector minimum register

§dfsdm0_cnvtimr: DFSDM0_CNVTIMR

0x138 - conversion timer register

§dfsdm1_cr1: DFSDM1_CR1

0x200 - control register 1

§dfsdm1_cr2: DFSDM1_CR2

0x204 - control register 2

§dfsdm1_isr: DFSDM1_ISR

0x208 - interrupt and status register

§dfsdm1_icr: DFSDM1_ICR

0x20c - interrupt flag clear register

§dfsdm1_jchgr: DFSDM1_JCHGR

0x210 - injected channel group selection register

§dfsdm1_fcr: DFSDM1_FCR

0x214 - filter control register

§dfsdm1_jdatar: DFSDM1_JDATAR

0x218 - data register for injected group

§dfsdm1_rdatar: DFSDM1_RDATAR

0x21c - data register for the regular channel

§dfsdm1_awhtr: DFSDM1_AWHTR

0x220 - analog watchdog high threshold register

§dfsdm1_awltr: DFSDM1_AWLTR

0x224 - analog watchdog low threshold register

§dfsdm1_awsr: DFSDM1_AWSR

0x228 - analog watchdog status register

§dfsdm1_awcfr: DFSDM1_AWCFR

0x22c - analog watchdog clear flag register

§dfsdm1_exmax: DFSDM1_EXMAX

0x230 - Extremes detector maximum register

§dfsdm1_exmin: DFSDM1_EXMIN

0x234 - Extremes detector minimum register

§dfsdm1_cnvtimr: DFSDM1_CNVTIMR

0x238 - conversion timer register

§dfsdm2_cr1: DFSDM2_CR1

0x300 - control register 1

§dfsdm2_cr2: DFSDM2_CR2

0x304 - control register 2

§dfsdm2_isr: DFSDM2_ISR

0x308 - interrupt and status register

§dfsdm2_icr: DFSDM2_ICR

0x30c - interrupt flag clear register

§dfsdm2_jchgr: DFSDM2_JCHGR

0x310 - injected channel group selection register

§dfsdm2_fcr: DFSDM2_FCR

0x314 - filter control register

§dfsdm2_jdatar: DFSDM2_JDATAR

0x318 - data register for injected group

§dfsdm2_rdatar: DFSDM2_RDATAR

0x31c - data register for the regular channel

§dfsdm2_awhtr: DFSDM2_AWHTR

0x320 - analog watchdog high threshold register

§dfsdm2_awltr: DFSDM2_AWLTR

0x324 - analog watchdog low threshold register

§dfsdm2_awsr: DFSDM2_AWSR

0x328 - analog watchdog status register

§dfsdm2_awcfr: DFSDM2_AWCFR

0x32c - analog watchdog clear flag register

§dfsdm2_exmax: DFSDM2_EXMAX

0x330 - Extremes detector maximum register

§dfsdm2_exmin: DFSDM2_EXMIN

0x334 - Extremes detector minimum register

§dfsdm2_cnvtimr: DFSDM2_CNVTIMR

0x338 - conversion timer register

§dfsdm3_cr1: DFSDM3_CR1

0x400 - control register 1

§dfsdm3_cr2: DFSDM3_CR2

0x404 - control register 2

§dfsdm3_isr: DFSDM3_ISR

0x408 - interrupt and status register

§dfsdm3_icr: DFSDM3_ICR

0x40c - interrupt flag clear register

§dfsdm3_jchgr: DFSDM3_JCHGR

0x410 - injected channel group selection register

§dfsdm3_fcr: DFSDM3_FCR

0x414 - filter control register

§dfsdm3_jdatar: DFSDM3_JDATAR

0x418 - data register for injected group

§dfsdm3_rdatar: DFSDM3_RDATAR

0x41c - data register for the regular channel

§dfsdm3_awhtr: DFSDM3_AWHTR

0x420 - analog watchdog high threshold register

§dfsdm3_awltr: DFSDM3_AWLTR

0x424 - analog watchdog low threshold register

§dfsdm3_awsr: DFSDM3_AWSR

0x428 - analog watchdog status register

§dfsdm3_awcfr: DFSDM3_AWCFR

0x42c - analog watchdog clear flag register

§dfsdm3_exmax: DFSDM3_EXMAX

0x430 - Extremes detector maximum register

§dfsdm3_exmin: DFSDM3_EXMIN

0x434 - Extremes detector minimum register

§dfsdm3_cnvtimr: DFSDM3_CNVTIMR

0x438 - conversion timer register

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