stm32l4_hal/
pwr.rs

1//! Power management
2
3use crate::rcc::{APB1R1};
4use crate::stm32::{pwr, PWR};
5
6
7pub struct Pwr {
8    pub cr1: CR1,
9    pub cr2: CR2,
10    pub cr3: CR3,
11    pub cr4: CR4,
12}
13
14/// Extension trait that constrains the `PWR` peripheral
15pub trait PwrExt {
16    /// Constrains the `PWR` peripheral so it plays nicely with the other abstractions
17    fn constrain(self, _: &mut APB1R1) -> Pwr;
18}
19
20impl PwrExt for PWR {
21    fn constrain(self, apb1r1: &mut APB1R1) -> Pwr {
22        // Enable the peripheral clock
23        apb1r1.enr().modify(|_, w| w.pwren().set_bit());
24        Pwr {
25            cr1: CR1 { _0: () },
26            cr2: CR2 { _0: () },
27            cr3: CR3 { _0: () },
28            cr4: CR4 { _0: () },
29        }
30    }
31}
32
33/// CR1
34pub struct CR1 {
35    _0: (),
36}
37
38impl CR1 {
39    // TODO remove `allow`
40    #[allow(dead_code)]
41    pub(crate) fn reg(&mut self) -> &pwr::CR1 {
42        // NOTE(unsafe) this proxy grants exclusive access to this register
43        unsafe { &(*PWR::ptr()).cr1 }
44    }
45}
46/// CR2
47pub struct CR2 {
48    _0: (),
49}
50
51impl CR2 {
52    // TODO remove `allow`
53    #[allow(dead_code)]
54    pub(crate) fn reg(&mut self) -> &pwr::CR2 {
55        // NOTE(unsafe) this proxy grants exclusive access to this register
56        unsafe { &(*PWR::ptr()).cr2 }
57    }
58}
59/// CR3
60pub struct CR3 {
61    _0: (),
62}
63
64impl CR3 {
65    // TODO remove `allow`
66    #[allow(dead_code)]
67    pub(crate) fn reg(&mut self) -> &pwr::CR3 {
68        // NOTE(unsafe) this proxy grants exclusive access to this register
69        unsafe { &(*PWR::ptr()).cr3 }
70    }
71}
72/// CR4
73pub struct CR4 {
74    _0: (),
75}
76
77impl CR4 {
78    // TODO remove `allow`
79    #[allow(dead_code)]
80    pub(crate) fn reg(&mut self) -> &pwr::CR4 {
81        // NOTE(unsafe) this proxy grants exclusive access to this register
82        unsafe { &(*PWR::ptr()).cr4 }
83    }
84}
stm32l4_hal/pwr.rs

stm32l4_hal/
pwr.rs
