[−][src]Struct stm32l1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

Writes raw bits to the register

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaouten(&mut self) -> DMAOUTEN_W`[src]

Bit 12 - Enable DMA management of data output phase

`pub fn dmainen(&mut self) -> DMAINEN_W`[src]

Bit 11 - Enable DMA management of data input phase

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 10 - Error interrupt enable

`pub fn ccfie(&mut self) -> CCFIE_W`[src]

Bit 9 - CCF flag interrupt enable

`pub fn errc(&mut self) -> ERRC_W`[src]

Bit 8 - Error clear

`pub fn ccfc(&mut self) -> CCFC_W`[src]

Bit 7 - Computation Complete Flag Clear

`pub fn chmod(&mut self) -> CHMOD_W`[src]

Bits 5:6 - AES chaining mode

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 3:4 - AES operating mode

`pub fn datatype(&mut self) -> DATATYPE_W`[src]

Bits 1:2 - Data type selection

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - AES enable

`impl W<u32, Reg<u32, _DINR>>`[src]

`pub fn dinr(&mut self) -> DINR_W`[src]

Bits 0:31 - Data input

`impl W<u32, Reg<u32, _KEYR0>>`[src]

`pub fn keyr0(&mut self) -> KEYR0_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR1>>`[src]

`pub fn keyr1(&mut self) -> KEYR1_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR2>>`[src]

`pub fn keyr2(&mut self) -> KEYR2_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR3>>`[src]

`pub fn keyr3(&mut self) -> KEYR3_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _IVR0>>`[src]

`pub fn ivr0(&mut self) -> IVR0_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR1>>`[src]

`pub fn ivr1(&mut self) -> IVR1_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR2>>`[src]

`pub fn ivr2(&mut self) -> IVR2_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR3>>`[src]

`pub fn ivr3(&mut self) -> IVR3_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn tsusp(&mut self) -> TSUSP_W`[src]

Bit 31 - Suspend Timer Mode

`pub fn caie(&mut self) -> CAIE_W`[src]

Bit 29 - Channel Acquisition Interrupt Enable / Clear

`pub fn rch13(&mut self) -> RCH13_W`[src]

Bit 28 - Select GPIO port PC3 as re-routed ADC input channel CH13.

`pub fn fch8(&mut self) -> FCH8_W`[src]

Bit 27 - Select GPIO port PB0 as fast ADC input channel CH8.

`pub fn fch3(&mut self) -> FCH3_W`[src]

Bit 26 - Select GPIO port PA3 as fast ADC input channel CH3.

`pub fn outsel(&mut self) -> OUTSEL_W`[src]

Bits 21:23 - Comparator 2 output selection

`pub fn insel(&mut self) -> INSEL_W`[src]

Bits 18:20 - Inverted input selection

`pub fn wndwe(&mut self) -> WNDWE_W`[src]

Bit 17 - Window mode enable

`pub fn vrefouten(&mut self) -> VREFOUTEN_W`[src]

Bit 16 - VREFINT output enable

`pub fn speed(&mut self) -> SPEED_W`[src]

Bit 12 - Comparator 2 speed mode

`pub fn sw1(&mut self) -> SW1_W`[src]

Bit 5 - SW1 analog switch enable

`pub fn cmp1en(&mut self) -> CMP1EN_W`[src]

Bit 4 - Comparator 1 enable

`pub fn pd400k(&mut self) -> PD400K_W`[src]

Bit 3 - 400 kO pull-down resistor

`pub fn pd10k(&mut self) -> PD10K_W`[src]

Bit 2 - 10 kO pull-down resistor

`pub fn pu400k(&mut self) -> PU400K_W`[src]

Bit 1 - 400 kO pull-up resistor

`pub fn pu10k(&mut self) -> PU10K_W`[src]

Bit 0 - 10 kO pull-up resistor

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:31 - Data Register

`impl W<u32, Reg<u32, _IDR>>`[src]

`pub fn idr(&mut self) -> IDR_W`[src]

Bits 0:6 - Independent data register

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 0 - RESET

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W`[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

`pub fn dmaen2(&mut self) -> DMAEN2_W`[src]

Bit 28 - DAC channel2 DMA enable

`pub fn mamp2(&mut self) -> MAMP2_W`[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

`pub fn wave2(&mut self) -> WAVE2_W`[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

`pub fn tsel2(&mut self) -> TSEL2_W`[src]

Bits 19:21 - DAC channel2 trigger selection

`pub fn ten2(&mut self) -> TEN2_W`[src]

Bit 18 - DAC channel2 trigger enable

`pub fn boff2(&mut self) -> BOFF2_W`[src]

Bit 17 - DAC channel2 output buffer disable

`pub fn en2(&mut self) -> EN2_W`[src]

Bit 16 - DAC channel2 enable

`pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W`[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

`pub fn dmaen1(&mut self) -> DMAEN1_W`[src]

Bit 12 - DAC channel1 DMA enable

`pub fn mamp1(&mut self) -> MAMP1_W`[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

`pub fn wave1(&mut self) -> WAVE1_W`[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

`pub fn tsel1(&mut self) -> TSEL1_W`[src]

Bits 3:5 - DAC channel1 trigger selection

`pub fn ten1(&mut self) -> TEN1_W`[src]

Bit 2 - DAC channel1 trigger enable

`pub fn boff1(&mut self) -> BOFF1_W`[src]

Bit 1 - DAC channel1 output buffer disable

`pub fn en1(&mut self) -> EN1_W`[src]

Bit 0 - DAC channel1 enable

`impl W<u32, Reg<u32, _SWTRIGR>>`[src]

`pub fn swtrig2(&mut self) -> SWTRIG2_W`[src]

Bit 1 - DAC channel2 software trigger

`pub fn swtrig1(&mut self) -> SWTRIG1_W`[src]

Bit 0 - DAC channel1 software trigger

`impl W<u32, Reg<u32, _DHR12R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12L1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12R2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12L2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8R2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12RD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12LD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8RD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn dmaudr2(&mut self) -> DMAUDR2_W`[src]

Bit 29 - DAC channel2 DMA underrun flag

`pub fn dmaudr1(&mut self) -> DMAUDR1_W`[src]

Bit 13 - DAC channel1 DMA underrun flag

`impl W<u32, Reg<u32, _IFCR>>`[src]

`pub fn cteif7(&mut self) -> CTEIF7_W`[src]

Bit 27 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif7(&mut self) -> CHTIF7_W`[src]

Bit 26 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif7(&mut self) -> CTCIF7_W`[src]

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif7(&mut self) -> CGIF7_W`[src]

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif6(&mut self) -> CTEIF6_W`[src]

Bit 23 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif6(&mut self) -> CHTIF6_W`[src]

Bit 22 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif6(&mut self) -> CTCIF6_W`[src]

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif6(&mut self) -> CGIF6_W`[src]

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif5(&mut self) -> CTEIF5_W`[src]

Bit 19 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif5(&mut self) -> CHTIF5_W`[src]

Bit 18 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif5(&mut self) -> CTCIF5_W`[src]

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif5(&mut self) -> CGIF5_W`[src]

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif4(&mut self) -> CTEIF4_W`[src]

Bit 15 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif4(&mut self) -> CHTIF4_W`[src]

Bit 14 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif4(&mut self) -> CTCIF4_W`[src]

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif4(&mut self) -> CGIF4_W`[src]

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif3(&mut self) -> CTEIF3_W`[src]

Bit 11 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif3(&mut self) -> CHTIF3_W`[src]

Bit 10 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif3(&mut self) -> CTCIF3_W`[src]

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif3(&mut self) -> CGIF3_W`[src]

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif2(&mut self) -> CTEIF2_W`[src]

Bit 7 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif2(&mut self) -> CHTIF2_W`[src]

Bit 6 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif2(&mut self) -> CTCIF2_W`[src]

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif2(&mut self) -> CGIF2_W`[src]

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif1(&mut self) -> CTEIF1_W`[src]

Bit 3 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif1(&mut self) -> CHTIF1_W`[src]

Bit 2 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif1(&mut self) -> CTCIF1_W`[src]

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif1(&mut self) -> CGIF1_W`[src]

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

`impl W<u32, Reg<u32, _CCR1>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR1>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR1>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR1>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR2>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR2>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR2>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR2>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR3>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR3>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR3>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR3>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR4>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR4>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR4>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR4>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR5>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR5>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR5>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR5>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR6>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR6>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR6>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR6>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR7>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR7>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR7>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR7>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _IMR>>`[src]

`pub fn mr0(&mut self) -> MR0_W`[src]

Bit 0 - Interrupt mask on line x

`pub fn mr1(&mut self) -> MR1_W`[src]

Bit 1 - Interrupt mask on line x

`pub fn mr2(&mut self) -> MR2_W`[src]

Bit 2 - Interrupt mask on line x

`pub fn mr3(&mut self) -> MR3_W`[src]

Bit 3 - Interrupt mask on line x

`pub fn mr4(&mut self) -> MR4_W`[src]

Bit 4 - Interrupt mask on line x

`pub fn mr5(&mut self) -> MR5_W`[src]

Bit 5 - Interrupt mask on line x

`pub fn mr6(&mut self) -> MR6_W`[src]

Bit 6 - Interrupt mask on line x

`pub fn mr7(&mut self) -> MR7_W`[src]

Bit 7 - Interrupt mask on line x

`pub fn mr8(&mut self) -> MR8_W`[src]

Bit 8 - Interrupt mask on line x

`pub fn mr9(&mut self) -> MR9_W`[src]

Bit 9 - Interrupt mask on line x

`pub fn mr10(&mut self) -> MR10_W`[src]

Bit 10 - Interrupt mask on line x

`pub fn mr11(&mut self) -> MR11_W`[src]

Bit 11 - Interrupt mask on line x

`pub fn mr12(&mut self) -> MR12_W`[src]

Bit 12 - Interrupt mask on line x

`pub fn mr13(&mut self) -> MR13_W`[src]

Bit 13 - Interrupt mask on line x

`pub fn mr14(&mut self) -> MR14_W`[src]

Bit 14 - Interrupt mask on line x

`pub fn mr15(&mut self) -> MR15_W`[src]

Bit 15 - Interrupt mask on line x

`pub fn mr16(&mut self) -> MR16_W`[src]

Bit 16 - Interrupt mask on line x

`pub fn mr17(&mut self) -> MR17_W`[src]

Bit 17 - Interrupt mask on line x

`pub fn mr18(&mut self) -> MR18_W`[src]

Bit 18 - Interrupt mask on line x

`pub fn mr19(&mut self) -> MR19_W`[src]

Bit 19 - Interrupt mask on line x

`pub fn mr20(&mut self) -> MR20_W`[src]

Bit 20 - Interrupt mask on line x

`pub fn mr21(&mut self) -> MR21_W`[src]

Bit 21 - Interrupt mask on line x

`pub fn mr22(&mut self) -> MR22_W`[src]

Bit 22 - Interrupt mask on line x

`impl W<u32, Reg<u32, _EMR>>`[src]

`pub fn mr0(&mut self) -> MR0_W`[src]

Bit 0 - Event mask on line x

`pub fn mr1(&mut self) -> MR1_W`[src]

Bit 1 - Event mask on line x

`pub fn mr2(&mut self) -> MR2_W`[src]

Bit 2 - Event mask on line x

`pub fn mr3(&mut self) -> MR3_W`[src]

Bit 3 - Event mask on line x

`pub fn mr4(&mut self) -> MR4_W`[src]

Bit 4 - Event mask on line x

`pub fn mr5(&mut self) -> MR5_W`[src]

Bit 5 - Event mask on line x

`pub fn mr6(&mut self) -> MR6_W`[src]

Bit 6 - Event mask on line x

`pub fn mr7(&mut self) -> MR7_W`[src]

Bit 7 - Event mask on line x

`pub fn mr8(&mut self) -> MR8_W`[src]

Bit 8 - Event mask on line x

`pub fn mr9(&mut self) -> MR9_W`[src]

Bit 9 - Event mask on line x

`pub fn mr10(&mut self) -> MR10_W`[src]

Bit 10 - Event mask on line x

`pub fn mr11(&mut self) -> MR11_W`[src]

Bit 11 - Event mask on line x

`pub fn mr12(&mut self) -> MR12_W`[src]

Bit 12 - Event mask on line x

`pub fn mr13(&mut self) -> MR13_W`[src]

Bit 13 - Event mask on line x

`pub fn mr14(&mut self) -> MR14_W`[src]

Bit 14 - Event mask on line x

`pub fn mr15(&mut self) -> MR15_W`[src]

Bit 15 - Event mask on line x

`pub fn mr16(&mut self) -> MR16_W`[src]

Bit 16 - Event mask on line x

`pub fn mr17(&mut self) -> MR17_W`[src]

Bit 17 - Event mask on line x

`pub fn mr18(&mut self) -> MR18_W`[src]

Bit 18 - Event mask on line x

`pub fn mr19(&mut self) -> MR19_W`[src]

Bit 19 - Event mask on line x

`pub fn mr20(&mut self) -> MR20_W`[src]

Bit 20 - Event mask on line x

`pub fn mr21(&mut self) -> MR21_W`[src]

Bit 21 - Event mask on line x

`pub fn mr22(&mut self) -> MR22_W`[src]

Bit 22 - Event mask on line x

`impl W<u32, Reg<u32, _RTSR>>`[src]

`pub fn tr0(&mut self) -> TR0_W`[src]

Bit 0 - Rising edge trigger event configuration bit of line x

`pub fn tr1(&mut self) -> TR1_W`[src]

Bit 1 - Rising edge trigger event configuration bit of line x

`pub fn tr2(&mut self) -> TR2_W`[src]

Bit 2 - Rising edge trigger event configuration bit of line x

`pub fn tr3(&mut self) -> TR3_W`[src]

Bit 3 - Rising edge trigger event configuration bit of line x

`pub fn tr4(&mut self) -> TR4_W`[src]

Bit 4 - Rising edge trigger event configuration bit of line x

`pub fn tr5(&mut self) -> TR5_W`[src]

Bit 5 - Rising edge trigger event configuration bit of line x

`pub fn tr6(&mut self) -> TR6_W`[src]

Bit 6 - Rising edge trigger event configuration bit of line x

`pub fn tr7(&mut self) -> TR7_W`[src]

Bit 7 - Rising edge trigger event configuration bit of line x

`pub fn tr8(&mut self) -> TR8_W`[src]

Bit 8 - Rising edge trigger event configuration bit of line x

`pub fn tr9(&mut self) -> TR9_W`[src]

Bit 9 - Rising edge trigger event configuration bit of line x

`pub fn tr10(&mut self) -> TR10_W`[src]

Bit 10 - Rising edge trigger event configuration bit of line x

`pub fn tr11(&mut self) -> TR11_W`[src]

Bit 11 - Rising edge trigger event configuration bit of line x

`pub fn tr12(&mut self) -> TR12_W`[src]

Bit 12 - Rising edge trigger event configuration bit of line x

`pub fn tr13(&mut self) -> TR13_W`[src]

Bit 13 - Rising edge trigger event configuration bit of line x

`pub fn tr14(&mut self) -> TR14_W`[src]

Bit 14 - Rising edge trigger event configuration bit of line x

`pub fn tr15(&mut self) -> TR15_W`[src]

Bit 15 - Rising edge trigger event configuration bit of line x

`pub fn tr16(&mut self) -> TR16_W`[src]

Bit 16 - Rising edge trigger event configuration bit of line x

`pub fn tr17(&mut self) -> TR17_W`[src]

Bit 17 - Rising edge trigger event configuration bit of line x

`pub fn tr18(&mut self) -> TR18_W`[src]

Bit 18 - Rising edge trigger event configuration bit of line x

`pub fn tr19(&mut self) -> TR19_W`[src]

Bit 19 - Rising edge trigger event configuration bit of line x

`pub fn tr20(&mut self) -> TR20_W`[src]

Bit 20 - Rising edge trigger event configuration bit of line x

`pub fn tr21(&mut self) -> TR21_W`[src]

Bit 21 - Rising edge trigger event configuration bit of line x

`pub fn tr22(&mut self) -> TR22_W`[src]

Bit 22 - Rising edge trigger event configuration bit of line x

`impl W<u32, Reg<u32, _FTSR>>`[src]

`pub fn tr0(&mut self) -> TR0_W`[src]

Bit 0 - Falling edge trigger event configuration bit of line x

`pub fn tr1(&mut self) -> TR1_W`[src]

Bit 1 - Falling edge trigger event configuration bit of line x

`pub fn tr2(&mut self) -> TR2_W`[src]

Bit 2 - Falling edge trigger event configuration bit of line x

`pub fn tr3(&mut self) -> TR3_W`[src]

Bit 3 - Falling edge trigger event configuration bit of line x

`pub fn tr4(&mut self) -> TR4_W`[src]

Bit 4 - Falling edge trigger event configuration bit of line x

`pub fn tr5(&mut self) -> TR5_W`[src]

Bit 5 - Falling edge trigger event configuration bit of line x

`pub fn tr6(&mut self) -> TR6_W`[src]

Bit 6 - Falling edge trigger event configuration bit of line x

`pub fn tr7(&mut self) -> TR7_W`[src]

Bit 7 - Falling edge trigger event configuration bit of line x

`pub fn tr8(&mut self) -> TR8_W`[src]

Bit 8 - Falling edge trigger event configuration bit of line x

`pub fn tr9(&mut self) -> TR9_W`[src]

Bit 9 - Falling edge trigger event configuration bit of line x

`pub fn tr10(&mut self) -> TR10_W`[src]

Bit 10 - Falling edge trigger event configuration bit of line x

`pub fn tr11(&mut self) -> TR11_W`[src]

Bit 11 - Falling edge trigger event configuration bit of line x

`pub fn tr12(&mut self) -> TR12_W`[src]

Bit 12 - Falling edge trigger event configuration bit of line x

`pub fn tr13(&mut self) -> TR13_W`[src]

Bit 13 - Falling edge trigger event configuration bit of line x

`pub fn tr14(&mut self) -> TR14_W`[src]

Bit 14 - Falling edge trigger event configuration bit of line x

`pub fn tr15(&mut self) -> TR15_W`[src]

Bit 15 - Falling edge trigger event configuration bit of line x

`pub fn tr16(&mut self) -> TR16_W`[src]

Bit 16 - Falling edge trigger event configuration bit of line x

`pub fn tr17(&mut self) -> TR17_W`[src]

Bit 17 - Falling edge trigger event configuration bit of line x

`pub fn tr18(&mut self) -> TR18_W`[src]

Bit 18 - Falling edge trigger event configuration bit of line x

`pub fn tr19(&mut self) -> TR19_W`[src]

Bit 19 - Falling edge trigger event configuration bit of line x

`pub fn tr20(&mut self) -> TR20_W`[src]

Bit 20 - Falling edge trigger event configuration bit of line x

`pub fn tr21(&mut self) -> TR21_W`[src]

Bit 21 - Falling edge trigger event configuration bit of line x

`pub fn tr22(&mut self) -> TR22_W`[src]

Bit 22 - Falling edge trigger event configuration bit of line x

`impl W<u32, Reg<u32, _SWIER>>`[src]

`pub fn swier0(&mut self) -> SWIER0_W`[src]

Bit 0 - Software interrupt on line x

`pub fn swier1(&mut self) -> SWIER1_W`[src]

Bit 1 - Software interrupt on line x

`pub fn swier2(&mut self) -> SWIER2_W`[src]

Bit 2 - Software interrupt on line x

`pub fn swier3(&mut self) -> SWIER3_W`[src]

Bit 3 - Software interrupt on line x

`pub fn swier4(&mut self) -> SWIER4_W`[src]

Bit 4 - Software interrupt on line x

`pub fn swier5(&mut self) -> SWIER5_W`[src]

Bit 5 - Software interrupt on line x

`pub fn swier6(&mut self) -> SWIER6_W`[src]

Bit 6 - Software interrupt on line x

`pub fn swier7(&mut self) -> SWIER7_W`[src]

Bit 7 - Software interrupt on line x

`pub fn swier8(&mut self) -> SWIER8_W`[src]

Bit 8 - Software interrupt on line x

`pub fn swier9(&mut self) -> SWIER9_W`[src]

Bit 9 - Software interrupt on line x

`pub fn swier10(&mut self) -> SWIER10_W`[src]

Bit 10 - Software interrupt on line x

`pub fn swier11(&mut self) -> SWIER11_W`[src]

Bit 11 - Software interrupt on line x

`pub fn swier12(&mut self) -> SWIER12_W`[src]

Bit 12 - Software interrupt on line x

`pub fn swier13(&mut self) -> SWIER13_W`[src]

Bit 13 - Software interrupt on line x

`pub fn swier14(&mut self) -> SWIER14_W`[src]

Bit 14 - Software interrupt on line x

`pub fn swier15(&mut self) -> SWIER15_W`[src]

Bit 15 - Software interrupt on line x

`pub fn swier16(&mut self) -> SWIER16_W`[src]

Bit 16 - Software interrupt on line x

`pub fn swier17(&mut self) -> SWIER17_W`[src]

Bit 17 - Software interrupt on line x

`pub fn swier18(&mut self) -> SWIER18_W`[src]

Bit 18 - Software interrupt on line x

`pub fn swier19(&mut self) -> SWIER19_W`[src]

Bit 19 - Software interrupt on line x

`pub fn swier20(&mut self) -> SWIER20_W`[src]

Bit 20 - Software interrupt on line x

`pub fn swier21(&mut self) -> SWIER21_W`[src]

Bit 21 - Software interrupt on line x

`pub fn swier22(&mut self) -> SWIER22_W`[src]

Bit 22 - Software interrupt on line x

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn pr0(&mut self) -> PR0_W`[src]

Bit 0 - Pending bit

`pub fn pr1(&mut self) -> PR1_W`[src]

Bit 1 - Pending bit

`pub fn pr2(&mut self) -> PR2_W`[src]

Bit 2 - Pending bit

`pub fn pr3(&mut self) -> PR3_W`[src]

Bit 3 - Pending bit

`pub fn pr4(&mut self) -> PR4_W`[src]

Bit 4 - Pending bit

`pub fn pr5(&mut self) -> PR5_W`[src]

Bit 5 - Pending bit

`pub fn pr6(&mut self) -> PR6_W`[src]

Bit 6 - Pending bit

`pub fn pr7(&mut self) -> PR7_W`[src]

Bit 7 - Pending bit

`pub fn pr8(&mut self) -> PR8_W`[src]

Bit 8 - Pending bit

`pub fn pr9(&mut self) -> PR9_W`[src]

Bit 9 - Pending bit

`pub fn pr10(&mut self) -> PR10_W`[src]

Bit 10 - Pending bit

`pub fn pr11(&mut self) -> PR11_W`[src]

Bit 11 - Pending bit

`pub fn pr12(&mut self) -> PR12_W`[src]

Bit 12 - Pending bit

`pub fn pr13(&mut self) -> PR13_W`[src]

Bit 13 - Pending bit

`pub fn pr14(&mut self) -> PR14_W`[src]

Bit 14 - Pending bit

`pub fn pr15(&mut self) -> PR15_W`[src]

Bit 15 - Pending bit

`pub fn pr16(&mut self) -> PR16_W`[src]

Bit 16 - Pending bit

`pub fn pr17(&mut self) -> PR17_W`[src]

Bit 17 - Pending bit

`pub fn pr18(&mut self) -> PR18_W`[src]

Bit 18 - Pending bit

`pub fn pr19(&mut self) -> PR19_W`[src]

Bit 19 - Pending bit

`pub fn pr20(&mut self) -> PR20_W`[src]

Bit 20 - Pending bit

`pub fn pr21(&mut self) -> PR21_W`[src]

Bit 21 - Pending bit

`pub fn pr22(&mut self) -> PR22_W`[src]

Bit 22 - Pending bit

`impl W<u32, Reg<u32, _ACR>>`[src]

`pub fn latency(&mut self) -> LATENCY_W`[src]

Bit 0 - Latency

`pub fn prften(&mut self) -> PRFTEN_W`[src]

Bit 1 - Prefetch enable

`pub fn acc64(&mut self) -> ACC64_W`[src]

Bit 2 - 64-bit access

`pub fn sleep_pd(&mut self) -> SLEEP_PD_W`[src]

Bit 3 - Flash mode during Sleep

`pub fn run_pd(&mut self) -> RUN_PD_W`[src]

Bit 4 - Flash mode during Run

`impl W<u32, Reg<u32, _PECR>>`[src]

`pub fn pelock(&mut self) -> PELOCK_W`[src]

Bit 0 - FLASH_PECR and data EEPROM lock

`pub fn prglock(&mut self) -> PRGLOCK_W`[src]

Bit 1 - Program memory lock

`pub fn optlock(&mut self) -> OPTLOCK_W`[src]

Bit 2 - Option bytes block lock

`pub fn prog(&mut self) -> PROG_W`[src]

Bit 3 - Program memory selection

`pub fn data(&mut self) -> DATA_W`[src]

Bit 4 - Data EEPROM selection

`pub fn ftdw(&mut self) -> FTDW_W`[src]

Bit 8 - Fixed time data write for Byte, Half Word and Word programming

`pub fn erase(&mut self) -> ERASE_W`[src]

Bit 9 - Page or Double Word erase mode

`pub fn fprg(&mut self) -> FPRG_W`[src]

Bit 10 - Half Page/Double Word programming mode

`pub fn parallelbank(&mut self) -> PARALLELBANK_W`[src]

Bit 15 - Parallel bank mode

`pub fn eopie(&mut self) -> EOPIE_W`[src]

Bit 16 - End of programming interrupt enable

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 17 - Error interrupt enable

`pub fn obl_launch(&mut self) -> OBL_LAUNCH_W`[src]

Bit 18 - Launch the option byte loading

`impl W<u32, Reg<u32, _PDKEYR>>`[src]

`pub fn pdkeyr(&mut self) -> PDKEYR_W`[src]

Bits 0:31 - RUN_PD in FLASH_ACR key

`impl W<u32, Reg<u32, _PEKEYR>>`[src]

`pub fn pekeyr(&mut self) -> PEKEYR_W`[src]

Bits 0:31 - FLASH_PEC and data EEPROM key

`impl W<u32, Reg<u32, _PRGKEYR>>`[src]

`pub fn prgkeyr(&mut self) -> PRGKEYR_W`[src]

Bits 0:31 - Program memory key

`impl W<u32, Reg<u32, _OPTKEYR>>`[src]

`pub fn optkeyr(&mut self) -> OPTKEYR_W`[src]

Bits 0:31 - Option byte key

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn wrperr(&mut self) -> WRPERR_W`[src]

Bit 8 - Write protected error

`pub fn pgaerr(&mut self) -> PGAERR_W`[src]

Bit 9 - Programming alignment error

`pub fn sizerr(&mut self) -> SIZERR_W`[src]

Bit 10 - Size error

`pub fn optverr(&mut self) -> OPTVERR_W`[src]

Bit 11 - Option validity error

`pub fn optverrusr(&mut self) -> OPTVERRUSR_W`[src]

Bit 12 - Option UserValidity Error

`impl W<u32, Reg<u32, _WRPR1>>`[src]

`pub fn wrp1(&mut self) -> WRP1_W`[src]

Bits 0:31 - Write protection

`impl W<u32, Reg<u32, _WRPR2>>`[src]

`pub fn wrp2(&mut self) -> WRP2_W`[src]

Bits 0:31 - WRP2

`impl W<u32, Reg<u32, _WRPR3>>`[src]

`pub fn wrp3(&mut self) -> WRP3_W`[src]

Bits 0:31 - WRP3

`impl W<u32, Reg<u32, _BCR1>>`[src]

`pub fn cburstrw(&mut self) -> CBURSTRW_W`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&mut self) -> ASYNCWAIT_W`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&mut self) -> EXTMOD_W`[src]

Bit 14 - EXTMOD

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 13 - WAITEN

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 12 - WREN

`pub fn waitcfg(&mut self) -> WAITCFG_W`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&mut self) -> WRAPMOD_W`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&mut self) -> WAITPOL_W`[src]

Bit 9 - WAITPOL

`pub fn bursten(&mut self) -> BURSTEN_W`[src]

Bit 8 - BURSTEN

`pub fn faccen(&mut self) -> FACCEN_W`[src]

Bit 6 - FACCEN

`pub fn mwid(&mut self) -> MWID_W`[src]

Bits 4:5 - MWID

`pub fn mtyp(&mut self) -> MTYP_W`[src]

Bits 2:3 - MTYP

`pub fn muxen(&mut self) -> MUXEN_W`[src]

Bit 1 - MUXEN

`pub fn mbken(&mut self) -> MBKEN_W`[src]

Bit 0 - MBKEN

`pub fn cpsize(&mut self) -> CPSIZE_W`[src]

Bits 16:18 - CRAM page size

`impl W<u32, Reg<u32, _BTR>>`[src]

`pub fn accmod(&mut self) -> ACCMOD_W`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&mut self) -> DATLAT_W`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 20:23 - CLKDIV

`pub fn busturn(&mut self) -> BUSTURN_W`[src]

Bits 16:19 - BUSTURN

`pub fn datast(&mut self) -> DATAST_W`[src]

Bits 8:15 - DATAST

`pub fn addhld(&mut self) -> ADDHLD_W`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&mut self) -> ADDSET_W`[src]

Bits 0:3 - ADDSET

`impl W<u32, Reg<u32, _BCR>>`[src]

`pub fn cburstrw(&mut self) -> CBURSTRW_W`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&mut self) -> ASYNCWAIT_W`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&mut self) -> EXTMOD_W`[src]

Bit 14 - EXTMOD

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 13 - WAITEN

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 12 - WREN

`pub fn waitcfg(&mut self) -> WAITCFG_W`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&mut self) -> WRAPMOD_W`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&mut self) -> WAITPOL_W`[src]

Bit 9 - WAITPOL

`pub fn bursten(&mut self) -> BURSTEN_W`[src]

Bit 8 - BURSTEN

`pub fn faccen(&mut self) -> FACCEN_W`[src]

Bit 6 - FACCEN

`pub fn mwid(&mut self) -> MWID_W`[src]

Bits 4:5 - MWID

`pub fn mtyp(&mut self) -> MTYP_W`[src]

Bits 2:3 - MTYP

`pub fn muxen(&mut self) -> MUXEN_W`[src]

Bit 1 - MUXEN

`pub fn mbken(&mut self) -> MBKEN_W`[src]

Bit 0 - MBKEN

`pub fn cpsize(&mut self) -> CPSIZE_W`[src]

Bits 16:18 - CRAM page size

`impl W<u32, Reg<u32, _BWTR>>`[src]

`pub fn accmod(&mut self) -> ACCMOD_W`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&mut self) -> DATLAT_W`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 20:23 - CLKDIV

`pub fn datast(&mut self) -> DATAST_W`[src]

Bits 8:15 - DATAST

`pub fn addhld(&mut self) -> ADDHLD_W`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&mut self) -> ADDSET_W`[src]

Bits 0:3 - ADDSET

`pub fn busturn(&mut self) -> BUSTURN_W`[src]

Bits 16:19 - Bus turnaround phase duration

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn swrst(&mut self) -> SWRST_W`[src]

Bit 15 - Software reset

`pub fn alert(&mut self) -> ALERT_W`[src]

Bit 13 - SMBus alert

`pub fn pec(&mut self) -> PEC_W`[src]

Bit 12 - Packet error checking

`pub fn pos(&mut self) -> POS_W`[src]

Bit 11 - Acknowledge/PEC Position (for data reception)

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 10 - Acknowledge enable

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 9 - Stop generation

`pub fn start(&mut self) -> START_W`[src]

Bit 8 - Start generation

`pub fn nostretch(&mut self) -> NOSTRETCH_W`[src]

Bit 7 - Clock stretching disable (Slave mode)

`pub fn engc(&mut self) -> ENGC_W`[src]

Bit 6 - General call enable

`pub fn enpec(&mut self) -> ENPEC_W`[src]

Bit 5 - PEC enable

`pub fn enarp(&mut self) -> ENARP_W`[src]

Bit 4 - ARP enable

`pub fn smbtype(&mut self) -> SMBTYPE_W`[src]

Bit 3 - SMBus type

`pub fn smbus(&mut self) -> SMBUS_W`[src]

Bit 1 - SMBus mode

`pub fn pe(&mut self) -> PE_W`[src]

Bit 0 - Peripheral enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn last(&mut self) -> LAST_W`[src]

Bit 12 - DMA last transfer

`pub fn dmaen(&mut self) -> DMAEN_W`[src]

Bit 11 - DMA requests enable

`pub fn itbufen(&mut self) -> ITBUFEN_W`[src]

Bit 10 - Buffer interrupt enable

`pub fn itevten(&mut self) -> ITEVTEN_W`[src]

Bit 9 - Event interrupt enable

`pub fn iterren(&mut self) -> ITERREN_W`[src]

Bit 8 - Error interrupt enable

`pub fn freq(&mut self) -> FREQ_W`[src]

Bits 0:5 - Peripheral clock frequency

`impl W<u32, Reg<u32, _OAR1>>`[src]

`pub fn addmode(&mut self) -> ADDMODE_W`[src]

Bit 15 - ADDMODE

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:9 - Interface address

`impl W<u32, Reg<u32, _OAR2>>`[src]

`pub fn add2(&mut self) -> ADD2_W`[src]

Bits 1:7 - Interface address

`pub fn endual(&mut self) -> ENDUAL_W`[src]

Bit 0 - Dual addressing mode enable

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:7 - -bit data register

`impl W<u32, Reg<u32, _SR1>>`[src]

`pub fn smbalert(&mut self) -> SMBALERT_W`[src]

Bit 15 - SMBus alert

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 14 - Timeout or Tlow error

`pub fn pecerr(&mut self) -> PECERR_W`[src]

Bit 12 - PEC Error in reception

`pub fn ovr(&mut self) -> OVR_W`[src]

Bit 11 - Overrun/Underrun

`pub fn af(&mut self) -> AF_W`[src]

Bit 10 - Acknowledge failure

`pub fn arlo(&mut self) -> ARLO_W`[src]

Bit 9 - Arbitration lost (master mode)

`pub fn berr(&mut self) -> BERR_W`[src]

Bit 8 - Bus error

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn f_s(&mut self) -> F_S_W`[src]

Bit 15 - I2C master mode selection

`pub fn duty(&mut self) -> DUTY_W`[src]

Bit 14 - Fast mode duty cycle

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

`impl W<u32, Reg<u32, _TRISE>>`[src]

`pub fn trise(&mut self) -> TRISE_W`[src]

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

`impl W<u32, Reg<u32, _KR>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:15 - Key value (write only, read 0000h)

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn pr(&mut self) -> PR_W`[src]

Bits 0:2 - Prescaler divider

`impl W<u32, Reg<u32, _RLR>>`[src]

`pub fn rl(&mut self) -> RL_W`[src]

Bits 0:11 - Watchdog counter reload value

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn mux_seg(&mut self) -> MUX_SEG_W`[src]

Bit 7 - Mux segment enable

`pub fn bias(&mut self) -> BIAS_W`[src]

Bits 5:6 - Bias selector

`pub fn duty(&mut self) -> DUTY_W`[src]

Bits 2:4 - Duty selection

`pub fn vsel(&mut self) -> VSEL_W`[src]

Bit 1 - Voltage source selection

`pub fn lcden(&mut self) -> LCDEN_W`[src]

Bit 0 - LCD controller enable

`impl W<u32, Reg<u32, _FCR>>`[src]

`pub fn ps(&mut self) -> PS_W`[src]

Bits 22:25 - PS 16-bit prescaler

`pub fn div(&mut self) -> DIV_W`[src]

Bits 18:21 - DIV clock divider

`pub fn blink(&mut self) -> BLINK_W`[src]

Bits 16:17 - Blink mode selection

`pub fn blinkf(&mut self) -> BLINKF_W`[src]

Bits 13:15 - Blink frequency selection

`pub fn cc(&mut self) -> CC_W`[src]

Bits 10:12 - Contrast control

`pub fn dead(&mut self) -> DEAD_W`[src]

Bits 7:9 - Dead time duration

`pub fn pon(&mut self) -> PON_W`[src]

Bits 4:6 - Pulse ON duration

`pub fn uddie(&mut self) -> UDDIE_W`[src]

Bit 3 - Update display done interrupt enable

`pub fn sofie(&mut self) -> SOFIE_W`[src]

Bit 1 - Start of frame interrupt enable

`pub fn hd(&mut self) -> HD_W`[src]

Bit 0 - High drive enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn udr(&mut self) -> UDR_W`[src]

Bit 2 - Update display request

`impl W<u32, Reg<u32, _CLR>>`[src]

`pub fn uddc(&mut self) -> UDDC_W`[src]

Bit 3 - Update display done clear

`pub fn sofc(&mut self) -> SOFC_W`[src]

Bit 1 - Start of frame flag clear

`impl W<u32, Reg<u32, _RAM_COM0>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM1>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM2>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM3>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM4>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM5>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM6>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM7>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn opa3calout(&mut self) -> OPA3CALOUT_W`[src]

Bit 31 - OPAMP3 calibration output

`pub fn opa2calout(&mut self) -> OPA2CALOUT_W`[src]

Bit 30 - OPAMP2 calibration output

`pub fn opa1calout(&mut self) -> OPA1CALOUT_W`[src]

Bit 29 - OPAMP1 calibration output

`pub fn aop_range(&mut self) -> AOP_RANGE_W`[src]

Bit 28 - Power range selection

`pub fn s7sel2(&mut self) -> S7SEL2_W`[src]

Bit 27 - Switch 7 for OPAMP2 enable

`pub fn anawsel3(&mut self) -> ANAWSEL3_W`[src]

Bit 26 - Switch SanA enable for OPAMP3

`pub fn anawsel2(&mut self) -> ANAWSEL2_W`[src]

Bit 25 - Switch SanA enable for OPAMP2

`pub fn anawsel1(&mut self) -> ANAWSEL1_W`[src]

Bit 24 - Switch SanA enable for OPAMP1

`pub fn opa3lpm(&mut self) -> OPA3LPM_W`[src]

Bit 23 - OPAMP3 low power mode

`pub fn opa3cal_h(&mut self) -> OPA3CAL_H_W`[src]

Bit 22 - OPAMP3 offset calibration for N differential pair

`pub fn opa3cal_l(&mut self) -> OPA3CAL_L_W`[src]

Bit 21 - OPAMP3 offset Calibration for P differential pair

`pub fn s6sel3(&mut self) -> S6SEL3_W`[src]

Bit 20 - Switch 6 for OPAMP3 enable

`pub fn s5sel3(&mut self) -> S5SEL3_W`[src]

Bit 19 - Switch 5 for OPAMP3 enable

`pub fn s4sel3(&mut self) -> S4SEL3_W`[src]

Bit 18 - Switch 4 for OPAMP3 enable

`pub fn s3sel3(&mut self) -> S3SEL3_W`[src]

Bit 17 - Switch 3 for OPAMP3 Enable

`pub fn opa3pd(&mut self) -> OPA3PD_W`[src]

Bit 16 - OPAMP3 power down

`pub fn opa2lpm(&mut self) -> OPA2LPM_W`[src]

Bit 15 - OPAMP2 low power mode

`pub fn opa2cal_h(&mut self) -> OPA2CAL_H_W`[src]

Bit 14 - OPAMP2 offset calibration for N differential pair

`pub fn opa2cal_l(&mut self) -> OPA2CAL_L_W`[src]

Bit 13 - OPAMP2 offset Calibration for P differential pair

`pub fn s6sel2(&mut self) -> S6SEL2_W`[src]

Bit 12 - Switch 6 for OPAMP2 enable

`pub fn s5sel2(&mut self) -> S5SEL2_W`[src]

Bit 11 - Switch 5 for OPAMP2 enable

`pub fn s4sel2(&mut self) -> S4SEL2_W`[src]

Bit 10 - Switch 4 for OPAMP2 enable

`pub fn s3sel2(&mut self) -> S3SEL2_W`[src]

Bit 9 - Switch 3 for OPAMP2 enable

`pub fn opa2pd(&mut self) -> OPA2PD_W`[src]

Bit 8 - OPAMP2 power down

`pub fn opa1lpm(&mut self) -> OPA1LPM_W`[src]

Bit 7 - OPAMP1 low power mode

`pub fn opa1cal_h(&mut self) -> OPA1CAL_H_W`[src]

Bit 6 - OPAMP1 offset calibration for N differential pair

`pub fn opa1cal_l(&mut self) -> OPA1CAL_L_W`[src]

Bit 5 - OPAMP1 offset calibration for P differential pair

`pub fn s6sel1(&mut self) -> S6SEL1_W`[src]

Bit 4 - Switch 6 for OPAMP1 enable

`pub fn s5sel1(&mut self) -> S5SEL1_W`[src]

Bit 3 - Switch 5 for OPAMP1 enable

`pub fn s4sel1(&mut self) -> S4SEL1_W`[src]

Bit 2 - Switch 4 for OPAMP1 enable

`pub fn s3sel1(&mut self) -> S3SEL1_W`[src]

Bit 1 - Switch 3 for OPAMP1 enable

`pub fn opa1pd(&mut self) -> OPA1PD_W`[src]

Bit 0 - OPAMP1 power down

`impl W<u32, Reg<u32, _OTR>>`[src]

`pub fn ot_user(&mut self) -> OT_USER_W`[src]

Bit 31 - Select user or factory trimming value

`pub fn ao3_opt_offset_trim(&mut self) -> AO3_OPT_OFFSET_TRIM_W`[src]

Bits 20:29 - OPAMP3, 10-bit offset trim value for normal mode

`pub fn ao2_opt_offset_trim(&mut self) -> AO2_OPT_OFFSET_TRIM_W`[src]

Bits 10:19 - OPAMP2, 10-bit offset trim value for normal mode

`pub fn ao1_opt_offset_trim(&mut self) -> AO1_OPT_OFFSET_TRIM_W`[src]

Bits 0:9 - OPAMP1, 10-bit offset trim value for normal mode

`impl W<u32, Reg<u32, _LPOTR>>`[src]

`pub fn ao3_opt_offset_trim_lp(&mut self) -> AO3_OPT_OFFSET_TRIM_LP_W`[src]

Bits 20:29 - OPAMP3, 10-bit offset trim value for low power mode

`pub fn ao2_opt_offset_trim_lp(&mut self) -> AO2_OPT_OFFSET_TRIM_LP_W`[src]

Bits 10:19 - OPAMP2, 10-bit offset trim value for low power mode

`pub fn ao1_opt_offset_trim_lp(&mut self) -> AO1_OPT_OFFSET_TRIM_LP_W`[src]

Bits 0:9 - OPAMP1, 10-bit offset trim value for low power mode

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn lprun(&mut self) -> LPRUN_W`[src]

Bit 14 - Low power run mode

`pub fn vos(&mut self) -> VOS_W`[src]

Bits 11:12 - Voltage scaling range selection

`pub fn fwu(&mut self) -> FWU_W`[src]

Bit 10 - Fast wakeup

`pub fn ulp(&mut self) -> ULP_W`[src]

Bit 9 - Ultralow power mode

`pub fn dbp(&mut self) -> DBP_W`[src]

Bit 8 - Disable backup domain write protection

`pub fn pls(&mut self) -> PLS_W`[src]

Bits 5:7 - PVD level selection

`pub fn pvde(&mut self) -> PVDE_W`[src]

Bit 4 - Power voltage detector enable

`pub fn csbf(&mut self) -> CSBF_W`[src]

Bit 3 - Clear standby flag

`pub fn cwuf(&mut self) -> CWUF_W`[src]

Bit 2 - Clear wakeup flag

`pub fn pdds(&mut self) -> PDDS_W`[src]

Bit 1 - Power down deepsleep

`pub fn lpsdsr(&mut self) -> LPSDSR_W`[src]

Bit 0 - Low-power deep sleep

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn ewup3(&mut self) -> EWUP3_W`[src]

Bit 10 - Enable WKUP pin 3

`pub fn ewup2(&mut self) -> EWUP2_W`[src]

Bit 9 - Enable WKUP pin 2

`pub fn ewup1(&mut self) -> EWUP1_W`[src]

Bit 8 - Enable WKUP pin 1

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn csson(&mut self) -> CSSON_W`[src]

Bit 28 - Clock security system enable

`pub fn pllon(&mut self) -> PLLON_W`[src]

Bit 24 - PLL enable

`pub fn hsebyp(&mut self) -> HSEBYP_W`[src]

Bit 18 - HSE clock bypass

`pub fn hseon(&mut self) -> HSEON_W`[src]

Bit 16 - HSE clock enable

`pub fn msion(&mut self) -> MSION_W`[src]

Bit 8 - MSI clock enable

`pub fn hsion(&mut self) -> HSION_W`[src]

Bit 0 - Internal high-speed clock enable

`pub fn rtcpre(&mut self) -> RTCPRE_W`[src]

Bits 29:30 - TC/LCD prescaler

`impl W<u32, Reg<u32, _ICSCR>>`[src]

`pub fn msitrim(&mut self) -> MSITRIM_W`[src]

Bits 24:31 - MSI clock trimming

`pub fn msirange(&mut self) -> MSIRANGE_W`[src]

Bits 13:15 - MSI clock ranges

`pub fn hsitrim(&mut self) -> HSITRIM_W`[src]

Bits 8:12 - High speed internal clock trimming

`impl W<u32, Reg<u32, _CFGR>>`[src]

`pub fn mcopre(&mut self) -> MCOPRE_W`[src]

Bits 28:30 - Microcontroller clock output prescaler

`pub fn mcosel(&mut self) -> MCOSEL_W`[src]

Bits 24:26 - Microcontroller clock output selection

`pub fn plldiv(&mut self) -> PLLDIV_W`[src]

Bits 22:23 - PLL output division

`pub fn pllmul(&mut self) -> PLLMUL_W`[src]

Bits 18:21 - PLL multiplication factor

`pub fn pllsrc(&mut self) -> PLLSRC_W`[src]

Bit 16 - PLL entry clock source

`pub fn ppre2(&mut self) -> PPRE2_W`[src]

Bits 11:13 - APB high-speed prescaler (APB2)

`pub fn ppre1(&mut self) -> PPRE1_W`[src]

Bits 8:10 - APB low-speed prescaler (APB1)

`pub fn hpre(&mut self) -> HPRE_W`[src]

Bits 4:7 - AHB prescaler

`pub fn sw(&mut self) -> SW_W`[src]

Bits 0:1 - System clock switch

`impl W<u32, Reg<u32, _CIR>>`[src]

`pub fn cssc(&mut self) -> CSSC_W`[src]

Bit 23 - Clock security system interrupt clear

`pub fn msirdyc(&mut self) -> MSIRDYC_W`[src]

Bit 21 - MSI ready interrupt clear

`pub fn pllrdyc(&mut self) -> PLLRDYC_W`[src]

Bit 20 - PLL ready interrupt clear

`pub fn hserdyc(&mut self) -> HSERDYC_W`[src]

Bit 19 - HSE ready interrupt clear

`pub fn hsirdyc(&mut self) -> HSIRDYC_W`[src]

Bit 18 - HSI ready interrupt clear

`pub fn lserdyc(&mut self) -> LSERDYC_W`[src]

Bit 17 - LSE ready interrupt clear

`pub fn lsirdyc(&mut self) -> LSIRDYC_W`[src]

Bit 16 - LSI ready interrupt clear

`pub fn msirdyie(&mut self) -> MSIRDYIE_W`[src]

Bit 13 - MSI ready interrupt enable

`pub fn pllrdyie(&mut self) -> PLLRDYIE_W`[src]

Bit 12 - PLL ready interrupt enable

`pub fn hserdyie(&mut self) -> HSERDYIE_W`[src]

Bit 11 - HSE ready interrupt enable

`pub fn hsirdyie(&mut self) -> HSIRDYIE_W`[src]

Bit 10 - HSI ready interrupt enable

`pub fn lserdyie(&mut self) -> LSERDYIE_W`[src]

Bit 9 - LSE ready interrupt enable

`pub fn lsirdyie(&mut self) -> LSIRDYIE_W`[src]

Bit 8 - LSI ready interrupt enable

`pub fn lsecssc(&mut self) -> LSECSSC_W`[src]

Bit 22 - LSE Clock security system interrupt clear

`pub fn lsecssf(&mut self) -> LSECSSF_W`[src]

Bit 6 - LSE Clock security system interrupt flag

`pub fn lsecssie(&mut self) -> LSECSSIE_W`[src]

Bit 14 - LSE clock security system interrupt enable

`impl W<u32, Reg<u32, _AHBRSTR>>`[src]

`pub fn fsmcrst(&mut self) -> FSMCRST_W`[src]

Bit 30 - FSMC reset

`pub fn dma2rst(&mut self) -> DMA2RST_W`[src]

Bit 25 - DMA2 reset

`pub fn dma1rst(&mut self) -> DMA1RST_W`[src]

Bit 24 - DMA1 reset

`pub fn flitfrst(&mut self) -> FLITFRST_W`[src]

Bit 15 - FLITF reset

`pub fn crcrst(&mut self) -> CRCRST_W`[src]

Bit 12 - CRC reset

`pub fn gpiogrst(&mut self) -> GPIOGRST_W`[src]

Bit 7 - IO port G reset

`pub fn gpiofrst(&mut self) -> GPIOFRST_W`[src]

Bit 6 - IO port F reset

`pub fn gpiohrst(&mut self) -> GPIOHRST_W`[src]

Bit 5 - IO port H reset

`pub fn gpioerst(&mut self) -> GPIOERST_W`[src]

Bit 4 - IO port E reset

`pub fn gpiodrst(&mut self) -> GPIODRST_W`[src]

Bit 3 - IO port D reset

`pub fn gpiocrst(&mut self) -> GPIOCRST_W`[src]

Bit 2 - IO port C reset

`pub fn gpiobrst(&mut self) -> GPIOBRST_W`[src]

Bit 1 - IO port B reset

`pub fn gpioarst(&mut self) -> GPIOARST_W`[src]

Bit 0 - IO port A reset

`impl W<u32, Reg<u32, _APB2RSTR>>`[src]

`pub fn usart1rst(&mut self) -> USART1RST_W`[src]

Bit 14 - USART1RST

`pub fn spi1rst(&mut self) -> SPI1RST_W`[src]

Bit 12 - SPI1RST

`pub fn sdiorst(&mut self) -> SDIORST_W`[src]

Bit 11 - SDIORST

`pub fn adc1rst(&mut self) -> ADC1RST_W`[src]

Bit 9 - ADC1RST

`pub fn tm11rst(&mut self) -> TM11RST_W`[src]

Bit 4 - TM11RST

`pub fn tm10rst(&mut self) -> TM10RST_W`[src]

Bit 3 - TM10RST

`pub fn tim9rst(&mut self) -> TIM9RST_W`[src]

Bit 2 - TIM9RST

`pub fn syscfgrst(&mut self) -> SYSCFGRST_W`[src]

Bit 0 - SYSCFGRST

`impl W<u32, Reg<u32, _APB1RSTR>>`[src]

`pub fn comprst(&mut self) -> COMPRST_W`[src]

Bit 31 - COMP interface reset

`pub fn dacrst(&mut self) -> DACRST_W`[src]

Bit 29 - DAC interface reset

`pub fn pwrrst(&mut self) -> PWRRST_W`[src]

Bit 28 - Power interface reset

`pub fn usbrst(&mut self) -> USBRST_W`[src]

Bit 23 - USB reset

`pub fn i2c2rst(&mut self) -> I2C2RST_W`[src]

Bit 22 - I2C 2 reset

`pub fn i2c1rst(&mut self) -> I2C1RST_W`[src]

Bit 21 - I2C 1 reset

`pub fn uart5rst(&mut self) -> UART5RST_W`[src]

Bit 20 - UART 5 reset

`pub fn uart4rst(&mut self) -> UART4RST_W`[src]

Bit 19 - UART 4 reset

`pub fn usart3rst(&mut self) -> USART3RST_W`[src]

Bit 18 - USART 3 reset

`pub fn usart2rst(&mut self) -> USART2RST_W`[src]

Bit 17 - USART 2 reset

`pub fn spi3rst(&mut self) -> SPI3RST_W`[src]

Bit 15 - SPI 3 reset

`pub fn spi2rst(&mut self) -> SPI2RST_W`[src]

Bit 14 - SPI 2 reset

`pub fn wwdrst(&mut self) -> WWDRST_W`[src]

Bit 11 - Window watchdog reset

`pub fn lcdrst(&mut self) -> LCDRST_W`[src]

Bit 9 - LCD reset

`pub fn tim7rst(&mut self) -> TIM7RST_W`[src]

Bit 5 - Timer 7 reset

`pub fn tim6rst(&mut self) -> TIM6RST_W`[src]

Bit 4 - Timer 6reset

`pub fn tim5rst(&mut self) -> TIM5RST_W`[src]

Bit 3 - Timer 5 reset

`pub fn tim4rst(&mut self) -> TIM4RST_W`[src]

Bit 2 - Timer 4 reset

`pub fn tim3rst(&mut self) -> TIM3RST_W`[src]

Bit 1 - Timer 3 reset

`pub fn tim2rst(&mut self) -> TIM2RST_W`[src]

Bit 0 - Timer 2 reset

`impl W<u32, Reg<u32, _AHBENR>>`[src]

`pub fn fsmcen(&mut self) -> FSMCEN_W`[src]

Bit 30 - FSMCEN

`pub fn dma2en(&mut self) -> DMA2EN_W`[src]

Bit 25 - DMA2 clock enable

`pub fn dma1en(&mut self) -> DMA1EN_W`[src]

Bit 24 - DMA1 clock enable

`pub fn flitfen(&mut self) -> FLITFEN_W`[src]

Bit 15 - FLITF clock enable

`pub fn crcen(&mut self) -> CRCEN_W`[src]

Bit 12 - CRC clock enable

`pub fn gpiopgen(&mut self) -> GPIOPGEN_W`[src]

Bit 7 - IO port G clock enable

`pub fn gpiopfen(&mut self) -> GPIOPFEN_W`[src]

Bit 6 - IO port F clock enable

`pub fn gpiophen(&mut self) -> GPIOPHEN_W`[src]

Bit 5 - IO port H clock enable

`pub fn gpiopeen(&mut self) -> GPIOPEEN_W`[src]

Bit 4 - IO port E clock enable

`pub fn gpiopden(&mut self) -> GPIOPDEN_W`[src]

Bit 3 - IO port D clock enable

`pub fn gpiopcen(&mut self) -> GPIOPCEN_W`[src]

Bit 2 - IO port C clock enable

`pub fn gpiopben(&mut self) -> GPIOPBEN_W`[src]

Bit 1 - IO port B clock enable

`pub fn gpiopaen(&mut self) -> GPIOPAEN_W`[src]

Bit 0 - IO port A clock enable

`impl W<u32, Reg<u32, _APB2ENR>>`[src]

`pub fn usart1en(&mut self) -> USART1EN_W`[src]

Bit 14 - USART1 clock enable

`pub fn spi1en(&mut self) -> SPI1EN_W`[src]

Bit 12 - SPI 1 clock enable

`pub fn sdioen(&mut self) -> SDIOEN_W`[src]

Bit 11 - SDIO clock enable

`pub fn adc1en(&mut self) -> ADC1EN_W`[src]

Bit 9 - ADC1 interface clock enable

`pub fn tim11en(&mut self) -> TIM11EN_W`[src]

Bit 4 - TIM11 timer clock enable

`pub fn tim10en(&mut self) -> TIM10EN_W`[src]

Bit 3 - TIM10 timer clock enable

`pub fn tim9en(&mut self) -> TIM9EN_W`[src]

Bit 2 - TIM9 timer clock enable

`pub fn syscfgen(&mut self) -> SYSCFGEN_W`[src]

Bit 0 - System configuration controller clock enable

`impl W<u32, Reg<u32, _APB1ENR>>`[src]

`pub fn compen(&mut self) -> COMPEN_W`[src]

Bit 31 - COMP interface clock enable

`pub fn dacen(&mut self) -> DACEN_W`[src]

Bit 29 - DAC interface clock enable

`pub fn pwren(&mut self) -> PWREN_W`[src]

Bit 28 - Power interface clock enable

`pub fn usben(&mut self) -> USBEN_W`[src]

Bit 23 - USB clock enable

`pub fn i2c2en(&mut self) -> I2C2EN_W`[src]

Bit 22 - I2C 2 clock enable

`pub fn i2c1en(&mut self) -> I2C1EN_W`[src]

Bit 21 - I2C 1 clock enable

`pub fn usart5en(&mut self) -> USART5EN_W`[src]

Bit 20 - UART 5 clock enable

`pub fn usart4en(&mut self) -> USART4EN_W`[src]

Bit 19 - UART 4 clock enable

`pub fn usart3en(&mut self) -> USART3EN_W`[src]

Bit 18 - USART 3 clock enable

`pub fn usart2en(&mut self) -> USART2EN_W`[src]

Bit 17 - USART 2 clock enable

`pub fn spi3en(&mut self) -> SPI3EN_W`[src]

Bit 15 - SPI 3 clock enable

`pub fn spi2en(&mut self) -> SPI2EN_W`[src]

Bit 14 - SPI 2 clock enable

`pub fn wwdgen(&mut self) -> WWDGEN_W`[src]

Bit 11 - Window watchdog clock enable

`pub fn lcden(&mut self) -> LCDEN_W`[src]

Bit 9 - LCD clock enable

`pub fn tim7en(&mut self) -> TIM7EN_W`[src]

Bit 5 - Timer 7 clock enable

`pub fn tim6en(&mut self) -> TIM6EN_W`[src]

Bit 4 - Timer 6 clock enable

`pub fn tim5en(&mut self) -> TIM5EN_W`[src]

Bit 3 - Timer 5 clock enable

`pub fn tim4en(&mut self) -> TIM4EN_W`[src]

Bit 2 - Timer 4 clock enable

`pub fn tim3en(&mut self) -> TIM3EN_W`[src]

Bit 1 - Timer 3 clock enable

`pub fn tim2en(&mut self) -> TIM2EN_W`[src]

Bit 0 - Timer 2 clock enable

`impl W<u32, Reg<u32, _AHBLPENR>>`[src]

`pub fn dma2lpen(&mut self) -> DMA2LPEN_W`[src]

Bit 25 - DMA2 clock enable during Sleep mode

`pub fn dma1lpen(&mut self) -> DMA1LPEN_W`[src]

Bit 24 - DMA1 clock enable during Sleep mode

`pub fn sramlpen(&mut self) -> SRAMLPEN_W`[src]

Bit 16 - SRAM clock enable during Sleep mode

`pub fn flitflpen(&mut self) -> FLITFLPEN_W`[src]

Bit 15 - FLITF clock enable during Sleep mode

`pub fn crclpen(&mut self) -> CRCLPEN_W`[src]

Bit 12 - CRC clock enable during Sleep mode

`pub fn gpioglpen(&mut self) -> GPIOGLPEN_W`[src]

Bit 7 - IO port G clock enable during Sleep mode

`pub fn gpioflpen(&mut self) -> GPIOFLPEN_W`[src]

Bit 6 - IO port F clock enable during Sleep mode

`pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W`[src]

Bit 5 - IO port H clock enable during Sleep mode

`pub fn gpioelpen(&mut self) -> GPIOELPEN_W`[src]

Bit 4 - IO port E clock enable during Sleep mode

`pub fn gpiodlpen(&mut self) -> GPIODLPEN_W`[src]

Bit 3 - IO port D clock enable during Sleep mode

`pub fn gpioclpen(&mut self) -> GPIOCLPEN_W`[src]

Bit 2 - IO port C clock enable during Sleep mode

`pub fn gpioblpen(&mut self) -> GPIOBLPEN_W`[src]

Bit 1 - IO port B clock enable during Sleep mode

`pub fn gpioalpen(&mut self) -> GPIOALPEN_W`[src]

Bit 0 - IO port A clock enable during Sleep mode

`pub fn fsmclpen(&mut self) -> FSMCLPEN_W`[src]

Bit 30 - FSMC clock enable during Sleep mode

`pub fn aeslpen(&mut self) -> AESLPEN_W`[src]

Bit 27 - AES clock enable during Sleep mode

`impl W<u32, Reg<u32, _APB2LPENR>>`[src]

`pub fn usart1lpen(&mut self) -> USART1LPEN_W`[src]

Bit 14 - USART1 clock enable during Sleep mode

`pub fn spi1lpen(&mut self) -> SPI1LPEN_W`[src]

Bit 12 - SPI 1 clock enable during Sleep mode

`pub fn sdiolpen(&mut self) -> SDIOLPEN_W`[src]

Bit 11 - SDIO clock enable during Sleep mode

`pub fn adc1lpen(&mut self) -> ADC1LPEN_W`[src]

Bit 9 - ADC1 interface clock enable during Sleep mode

`pub fn tim11lpen(&mut self) -> TIM11LPEN_W`[src]

Bit 4 - TIM11 timer clock enable during Sleep mode

`pub fn tim10lpen(&mut self) -> TIM10LPEN_W`[src]

Bit 3 - TIM10 timer clock enable during Sleep mode

`pub fn tim9lpen(&mut self) -> TIM9LPEN_W`[src]

Bit 2 - TIM9 timer clock enable during Sleep mode

`pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W`[src]

Bit 0 - System configuration controller clock enable during Sleep mode

`impl W<u32, Reg<u32, _APB1LPENR>>`[src]

`pub fn complpen(&mut self) -> COMPLPEN_W`[src]

Bit 31 - COMP interface clock enable during Sleep mode

`pub fn daclpen(&mut self) -> DACLPEN_W`[src]

Bit 29 - DAC interface clock enable during Sleep mode

`pub fn pwrlpen(&mut self) -> PWRLPEN_W`[src]

Bit 28 - Power interface clock enable during Sleep mode

`pub fn usblpen(&mut self) -> USBLPEN_W`[src]

Bit 23 - USB clock enable during Sleep mode

`pub fn i2c2lpen(&mut self) -> I2C2LPEN_W`[src]

Bit 22 - I2C 2 clock enable during Sleep mode

`pub fn i2c1lpen(&mut self) -> I2C1LPEN_W`[src]

Bit 21 - I2C 1 clock enable during Sleep mode

`pub fn usart3lpen(&mut self) -> USART3LPEN_W`[src]

Bit 18 - USART 3 clock enable during Sleep mode

`pub fn usart2lpen(&mut self) -> USART2LPEN_W`[src]

Bit 17 - USART 2 clock enable during Sleep mode

`pub fn spi2lpen(&mut self) -> SPI2LPEN_W`[src]

Bit 14 - SPI 2 clock enable during Sleep mode

`pub fn wwdglpen(&mut self) -> WWDGLPEN_W`[src]

Bit 11 - Window watchdog clock enable during Sleep mode

`pub fn lcdlpen(&mut self) -> LCDLPEN_W`[src]

Bit 9 - LCD clock enable during Sleep mode

`pub fn tim7lpen(&mut self) -> TIM7LPEN_W`[src]

Bit 5 - Timer 7 clock enable during Sleep mode

`pub fn tim6lpen(&mut self) -> TIM6LPEN_W`[src]

Bit 4 - Timer 6 clock enable during Sleep mode

`pub fn tim4lpen(&mut self) -> TIM4LPEN_W`[src]

Bit 2 - Timer 4 clock enable during Sleep mode

`pub fn tim3lpen(&mut self) -> TIM3LPEN_W`[src]

Bit 1 - Timer 3 clock enable during Sleep mode

`pub fn tim2lpen(&mut self) -> TIM2LPEN_W`[src]

Bit 0 - Timer 2 clock enable during Sleep mode

`pub fn uart5lpen(&mut self) -> UART5LPEN_W`[src]

Bit 20 - USART 5 clock enable during Sleep mode

`pub fn uart4lpen(&mut self) -> UART4LPEN_W`[src]

Bit 19 - USART 4 clock enable during Sleep mode

`pub fn spi3lpen(&mut self) -> SPI3LPEN_W`[src]

Bit 15 - SPI 3 clock enable during Sleep mode

`pub fn tim5lpen(&mut self) -> TIM5LPEN_W`[src]

Bit 3 - Timer 5 clock enable during Sleep mode

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn lpwrstf(&mut self) -> LPWRSTF_W`[src]

Bit 31 - Low-power reset flag

`pub fn wwdgrstf(&mut self) -> WWDGRSTF_W`[src]

Bit 30 - Window watchdog reset flag

`pub fn iwdgrstf(&mut self) -> IWDGRSTF_W`[src]

Bit 29 - Independent watchdog reset flag

`pub fn sftrstf(&mut self) -> SFTRSTF_W`[src]

Bit 28 - Software reset flag

`pub fn porrstf(&mut self) -> PORRSTF_W`[src]

Bit 27 - POR/PDR reset flag

`pub fn pinrstf(&mut self) -> PINRSTF_W`[src]

Bit 26 - PIN reset flag

`pub fn rmvf(&mut self) -> RMVF_W`[src]

Bit 24 - Remove reset flag

`pub fn rtcrst(&mut self) -> RTCRST_W`[src]

Bit 23 - RTC software reset

`pub fn rtcen(&mut self) -> RTCEN_W`[src]

Bit 22 - RTC clock enable

`pub fn rtcsel(&mut self) -> RTCSEL_W`[src]

Bits 16:17 - RTC and LCD clock source selection

`pub fn lsebyp(&mut self) -> LSEBYP_W`[src]

Bit 10 - External low-speed oscillator bypass

`pub fn lseon(&mut self) -> LSEON_W`[src]

Bit 8 - External low-speed oscillator enable

`pub fn lsion(&mut self) -> LSION_W`[src]

Bit 0 - Internal low-speed oscillator enable

`pub fn oblrstf(&mut self) -> OBLRSTF_W`[src]

Bit 25 - Options bytes loading reset flag

`pub fn lsecssd(&mut self) -> LSECSSD_W`[src]

Bit 12 - CSS on LSE failure Detection

`pub fn lsecsson(&mut self) -> LSECSSON_W`[src]

Bit 11 - CSS on LSE enable

`impl W<u32, Reg<u32, _ICR>>`[src]

`pub fn ic4(&mut self) -> IC4_W`[src]

Bit 21 - IC4

`pub fn ic3(&mut self) -> IC3_W`[src]

Bit 20 - IC3

`pub fn ic2(&mut self) -> IC2_W`[src]

Bit 19 - IC2

`pub fn ic1(&mut self) -> IC1_W`[src]

Bit 18 - IC1

`pub fn tim(&mut self) -> TIM_W`[src]

Bits 16:17 - Timer select bits

`pub fn ic4ios(&mut self) -> IC4IOS_W`[src]

Bits 12:15 - Input capture 4 select bits

`pub fn ic3ios(&mut self) -> IC3IOS_W`[src]

Bits 8:11 - Input capture 3 select bits

`pub fn ic2ios(&mut self) -> IC2IOS_W`[src]

Bits 4:7 - Input capture 2 select bits

`pub fn ic1ios(&mut self) -> IC1IOS_W`[src]

Bits 0:3 - Input capture 1 select bits

`impl W<u32, Reg<u32, _ASCR1>>`[src]

`pub fn scm(&mut self) -> SCM_W`[src]

Bit 31 - Switch control mode

`pub fn ch30gr11_4(&mut self) -> CH30GR11_4_W`[src]

Bit 30 - Analog switch control

`pub fn ch29gr11_3(&mut self) -> CH29GR11_3_W`[src]

Bit 29 - Analog switch control

`pub fn ch28gr11_2(&mut self) -> CH28GR11_2_W`[src]

Bit 28 - Analog switch control

`pub fn ch27gr11_1(&mut self) -> CH27GR11_1_W`[src]

Bit 27 - Analog switch control

`pub fn vcomp(&mut self) -> VCOMP_W`[src]

Bit 26 - ADC analog switch selection for internal node to comparator 1

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Analog I/O switch control of channel CH25

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Analog I/O switch control of channel CH24

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Analog I/O switch control of channel CH23

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Analog I/O switch control of channel CH22

`pub fn ch21gr7_4(&mut self) -> CH21GR7_4_W`[src]

Bit 21 - Analog switch control

`pub fn ch20gr7_3(&mut self) -> CH20GR7_3_W`[src]

Bit 20 - Analog switch control

`pub fn ch19gr7_2(&mut self) -> CH19GR7_2_W`[src]

Bit 19 - Analog switch control

`pub fn ch18gr7_1(&mut self) -> CH18GR7_1_W`[src]

Bit 18 - Analog switch control

`pub fn ch31gr7_1(&mut self) -> CH31GR7_1_W`[src]

Bit 16 - Analog switch control

`pub fn ch15gr9_2(&mut self) -> CH15GR9_2_W`[src]

Bit 15 - Analog switch control

`pub fn ch14gr9_1(&mut self) -> CH14GR9_1_W`[src]

Bit 14 - Analog switch control

`pub fn ch13gr8_4(&mut self) -> CH13GR8_4_W`[src]

Bit 13 - Analog switch control

`pub fn ch12gr8_3(&mut self) -> CH12GR8_3_W`[src]

Bit 12 - Analog switch control

`pub fn ch11gr8_2(&mut self) -> CH11GR8_2_W`[src]

Bit 11 - Analog switch control

`pub fn ch10gr8_1(&mut self) -> CH10GR8_1_W`[src]

Bit 10 - Analog switch control

`pub fn ch9gr3_2(&mut self) -> CH9GR3_2_W`[src]

Bit 9 - Analog switch control

`pub fn ch8gr3_1(&mut self) -> CH8GR3_1_W`[src]

Bit 8 - Analog switch control

`pub fn ch7gr2_2(&mut self) -> CH7GR2_2_W`[src]

Bit 7 - Analog switch control

`pub fn ch6gr2_1(&mut self) -> CH6GR2_1_W`[src]

Bit 6 - Analog switch control

`pub fn comp1_sw1(&mut self) -> COMP1_SW1_W`[src]

Bit 5 - Comparator 1 analog switch

`pub fn ch31gr11_5(&mut self) -> CH31GR11_5_W`[src]

Bit 4 - Analog switch control

`pub fn ch3gr1_4(&mut self) -> CH3GR1_4_W`[src]

Bit 3 - Analog switch control

`pub fn ch2gr1_3(&mut self) -> CH2GR1_3_W`[src]

Bit 2 - Analog switch control

`pub fn ch1gr1_2(&mut self) -> CH1GR1_2_W`[src]

Bit 1 - Analog switch control

`pub fn ch0gr1_1(&mut self) -> CH0GR1_1_W`[src]

Bit 0 - Analog switch control

`impl W<u32, Reg<u32, _ASCR2>>`[src]

`pub fn gr5_4(&mut self) -> GR5_4_W`[src]

Bit 29 - GR5_4 analog switch control

`pub fn gr6_4(&mut self) -> GR6_4_W`[src]

Bit 28 - GR6_4 analog switch control

`pub fn gr6_3(&mut self) -> GR6_3_W`[src]

Bit 27 - GR6_3 analog switch control

`pub fn gr7_7(&mut self) -> GR7_7_W`[src]

Bit 26 - GR7_7 analog switch control

`pub fn gr7_6(&mut self) -> GR7_6_W`[src]

Bit 25 - GR7_6 analog switch control

`pub fn gr7_5(&mut self) -> GR7_5_W`[src]

Bit 24 - GR7_5 analog switch control

`pub fn gr2_5(&mut self) -> GR2_5_W`[src]

Bit 23 - GR2_5 analog switch control

`pub fn gr2_4(&mut self) -> GR2_4_W`[src]

Bit 22 - GR2_4 analog switch control

`pub fn gr2_3(&mut self) -> GR2_3_W`[src]

Bit 21 - GR2_3 analog switch control

`pub fn gr9_4(&mut self) -> GR9_4_W`[src]

Bit 20 - GR9_4 analog switch control

`pub fn gr9_3(&mut self) -> GR9_3_W`[src]

Bit 19 - GR9_3 analog switch control

`pub fn gr3_5(&mut self) -> GR3_5_W`[src]

Bit 18 - GR3_5 analog switch control

`pub fn gr3_4(&mut self) -> GR3_4_W`[src]

Bit 17 - GR3_4 analog switch control

`pub fn gr3_3(&mut self) -> GR3_3_W`[src]

Bit 16 - GR3_3 analog switch control

`pub fn gr4_3(&mut self) -> GR4_3_W`[src]

Bit 11 - GR4_3 analog switch control

`pub fn gr4_2(&mut self) -> GR4_2_W`[src]

Bit 10 - GR4_2 analog switch control

`pub fn gr4_1(&mut self) -> GR4_1_W`[src]

Bit 9 - GR4_1 analog switch control

`pub fn gr5_3(&mut self) -> GR5_3_W`[src]

Bit 8 - GR5_3 analog switch control

`pub fn gr5_2(&mut self) -> GR5_2_W`[src]

Bit 7 - GR5_2 analog switch control

`pub fn gr5_1(&mut self) -> GR5_1_W`[src]

Bit 6 - GR5_1 analog switch control

`pub fn gr6_2(&mut self) -> GR6_2_W`[src]

Bit 5 - GR6_2 analog switch control

`pub fn gr6_1(&mut self) -> GR6_1_W`[src]

Bit 4 - GR6_1 analog switch control

`pub fn gr10_4(&mut self) -> GR10_4_W`[src]

Bit 3 - GR10_4 analog switch control

`pub fn gr10_3(&mut self) -> GR10_3_W`[src]

Bit 2 - GR10_3 analog switch control

`pub fn gr10_2(&mut self) -> GR10_2_W`[src]

Bit 1 - GR10_2 analog switch control

`pub fn gr10_1(&mut self) -> GR10_1_W`[src]

Bit 0 - GR10_1 analog switch control

`impl W<u32, Reg<u32, _HYSCR1>>`[src]

`pub fn pb(&mut self) -> PB_W`[src]

Bits 16:31 - Port B hysteresis control on/off

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:15 - Port A hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR2>>`[src]

`pub fn pd(&mut self) -> PD_W`[src]

Bits 16:31 - Port D hysteresis control on/off

`pub fn pc(&mut self) -> PC_W`[src]

Bits 0:15 - Port C hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR3>>`[src]

`pub fn pf(&mut self) -> PF_W`[src]

Bits 16:31 - Port F hysteresis control on/off

`pub fn pe(&mut self) -> PE_W`[src]

Bits 0:15 - Port E hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR4>>`[src]

`pub fn pg(&mut self) -> PG_W`[src]

Bits 0:15 - Port G hysteresis control on/off

`impl W<u32, Reg<u32, _TR>>`[src]

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn yt(&mut self) -> YT_W`[src]

Bits 20:23 - Year tens in BCD format

`pub fn yu(&mut self) -> YU_W`[src]

Bits 16:19 - Year units in BCD format

`pub fn wdu(&mut self) -> WDU_W`[src]

Bits 13:15 - Week day units

`pub fn mt(&mut self) -> MT_W`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&mut self) -> MU_W`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&mut self) -> DT_W`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&mut self) -> DU_W`[src]

Bits 0:3 - Date units in BCD format

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn coe(&mut self) -> COE_W`[src]

Bit 23 - Calibration output enable

`pub fn osel(&mut self) -> OSEL_W`[src]

Bits 21:22 - Output selection

`pub fn pol(&mut self) -> POL_W`[src]

Bit 20 - Output polarity

`pub fn cosel(&mut self) -> COSEL_W`[src]

Bit 19 - Calibration output selection

`pub fn bkp(&mut self) -> BKP_W`[src]

Bit 18 - Backup

`pub fn sub1h(&mut self) -> SUB1H_W`[src]

Bit 17 - Subtract 1 hour

`pub fn add1h(&mut self) -> ADD1H_W`[src]

Bit 16 - Add 1 hour

`pub fn tsie(&mut self) -> TSIE_W`[src]

Bit 15 - Time-stamp interrupt enable

`pub fn wutie(&mut self) -> WUTIE_W`[src]

Bit 14 - Wakeup timer interrupt enable

`pub fn alrbie(&mut self) -> ALRBIE_W`[src]

Bit 13 - Alarm B interrupt enable

`pub fn alraie(&mut self) -> ALRAIE_W`[src]

Bit 12 - Alarm A interrupt enable

`pub fn tse(&mut self) -> TSE_W`[src]

Bit 11 - Time stamp enable

`pub fn wute(&mut self) -> WUTE_W`[src]

Bit 10 - Wakeup timer enable

`pub fn alrbe(&mut self) -> ALRBE_W`[src]

Bit 9 - Alarm B enable

`pub fn alrae(&mut self) -> ALRAE_W`[src]

Bit 8 - Alarm A enable

`pub fn dce(&mut self) -> DCE_W`[src]

Bit 7 - Coarse digital calibration enable

`pub fn fmt(&mut self) -> FMT_W`[src]

Bit 6 - Hour format

`pub fn bypshad(&mut self) -> BYPSHAD_W`[src]

Bit 5 - Bypass the shadow registers

`pub fn refckon(&mut self) -> REFCKON_W`[src]

Bit 4 - Reference clock detection enable

`pub fn tsedge(&mut self) -> TSEDGE_W`[src]

Bit 3 - Time-stamp event active edge

`pub fn wcksel(&mut self) -> WCKSEL_W`[src]

Bits 0:2 - WCKSEL

`impl W<u32, Reg<u32, _ISR>>`[src]

`pub fn tamp3f(&mut self) -> TAMP3F_W`[src]

Bit 15 - TAMPER3 detection flag

`pub fn tamp2f(&mut self) -> TAMP2F_W`[src]

Bit 14 - TAMPER2 detection flag

`pub fn tamp1f(&mut self) -> TAMP1F_W`[src]

Bit 13 - Tamper detection flag

`pub fn tsovf(&mut self) -> TSOVF_W`[src]

Bit 12 - Timestamp overflow flag

`pub fn tsf(&mut self) -> TSF_W`[src]

Bit 11 - Timestamp flag

`pub fn wutf(&mut self) -> WUTF_W`[src]

Bit 10 - Wakeup timer flag

`pub fn alrbf(&mut self) -> ALRBF_W`[src]

Bit 9 - Alarm B flag

`pub fn alraf(&mut self) -> ALRAF_W`[src]

Bit 8 - Alarm A flag

`pub fn init(&mut self) -> INIT_W`[src]

Bit 7 - Initialization mode

`pub fn initf(&mut self) -> INITF_W`[src]

Bit 6 - Initialization flag

`pub fn rsf(&mut self) -> RSF_W`[src]

Bit 5 - Registers synchronization flag

`pub fn shpf(&mut self) -> SHPF_W`[src]

Bit 3 - Shift operation pending

`impl W<u32, Reg<u32, _PRER>>`[src]

`pub fn prediv_a(&mut self) -> PREDIV_A_W`[src]

Bits 16:22 - Asynchronous prescaler factor

`pub fn prediv_s(&mut self) -> PREDIV_S_W`[src]

Bits 0:14 - Synchronous prescaler factor

`impl W<u32, Reg<u32, _WUTR>>`[src]

`pub fn wut(&mut self) -> WUT_W`[src]

Bits 0:15 - Wakeup auto-reload value bits

`impl W<u32, Reg<u32, _CALIBR>>`[src]

`pub fn dcs(&mut self) -> DCS_W`[src]

Bit 7 - Digital calibration sign

`pub fn dc(&mut self) -> DC_W`[src]

Bits 0:4 - Digital calibration

`impl W<u32, Reg<u32, _ALRMAR>>`[src]

`pub fn msk4(&mut self) -> MSK4_W`[src]

Bit 31 - Alarm A date mask

`pub fn wdsel(&mut self) -> WDSEL_W`[src]

Bit 30 - Week day selection

`pub fn dt(&mut self) -> DT_W`[src]

Bits 28:29 - Date tens in BCD format.

`pub fn du(&mut self) -> DU_W`[src]

Bits 24:27 - Date units or day in BCD format.

`pub fn msk3(&mut self) -> MSK3_W`[src]

Bit 23 - Alarm A hours mask

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format.

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format.

`pub fn msk2(&mut self) -> MSK2_W`[src]

Bit 15 - Alarm A minutes mask

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format.

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format.

`pub fn msk1(&mut self) -> MSK1_W`[src]

Bit 7 - Alarm A seconds mask

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format.

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format.

`impl W<u32, Reg<u32, _ALRMBR>>`[src]

`pub fn msk4(&mut self) -> MSK4_W`[src]

Bit 31 - Alarm B date mask

`pub fn wdsel(&mut self) -> WDSEL_W`[src]

Bit 30 - Week day selection

`pub fn dt(&mut self) -> DT_W`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&mut self) -> DU_W`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&mut self) -> MSK3_W`[src]

Bit 23 - Alarm B hours mask

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&mut self) -> MSK2_W`[src]

Bit 15 - Alarm B minutes mask

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&mut self) -> MSK1_W`[src]

Bit 7 - Alarm B seconds mask

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format

`impl W<u32, Reg<u32, _WPR>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:7 - Write protection key

`impl W<u32, Reg<u32, _SHIFTR>>`[src]

`pub fn add1s(&mut self) -> ADD1S_W`[src]

Bit 31 - ADD1S

`pub fn subfs(&mut self) -> SUBFS_W`[src]

Bits 0:14 - Subtract a fraction of a second

`impl W<u32, Reg<u32, _CALR>>`[src]

`pub fn calp(&mut self) -> CALP_W`[src]

Bit 15 - Use an 8-second calibration cycle period

`pub fn calw8(&mut self) -> CALW8_W`[src]

Bit 14 - Use a 16-second calibration cycle period

`pub fn calw16(&mut self) -> CALW16_W`[src]

Bit 13 - CALW16

`pub fn calm(&mut self) -> CALM_W`[src]

Bits 0:8 - Calibration minus

`impl W<u32, Reg<u32, _TAFCR>>`[src]

`pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W`[src]

Bit 18 - AFO_ALARM output type

`pub fn tamppudis(&mut self) -> TAMPPUDIS_W`[src]

Bit 15 - TAMPER pull-up disable

`pub fn tampprch(&mut self) -> TAMPPRCH_W`[src]

Bits 13:14 - Tamper precharge duration

`pub fn tampflt(&mut self) -> TAMPFLT_W`[src]

Bits 11:12 - Tamper filter count

`pub fn tampfreq(&mut self) -> TAMPFREQ_W`[src]

Bits 8:10 - Tamper sampling frequency

`pub fn tampts(&mut self) -> TAMPTS_W`[src]

Bit 7 - Activate timestamp on tamper detection event

`pub fn tamp3trg(&mut self) -> TAMP3TRG_W`[src]

Bit 6 - TAMPER1 mapping

`pub fn tamp3e(&mut self) -> TAMP3E_W`[src]

Bit 5 - TIMESTAMP mapping

`pub fn tamp2trg(&mut self) -> TAMP2TRG_W`[src]

Bit 4 - Active level for tamper 2

`pub fn tamp2e(&mut self) -> TAMP2E_W`[src]

Bit 3 - Tamper 2 detection enable

`pub fn tampie(&mut self) -> TAMPIE_W`[src]

Bit 2 - Tamper interrupt enable

`pub fn tamp1etrg(&mut self) -> TAMP1ETRG_W`[src]

Bit 1 - Active level for tamper 1

`pub fn tamp1e(&mut self) -> TAMP1E_W`[src]

Bit 0 - Tamper 1 detection enable

`impl W<u32, Reg<u32, _ALRMASSR>>`[src]

`pub fn maskss(&mut self) -> MASKSS_W`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&mut self) -> SS_W`[src]

Bits 0:14 - Sub seconds value

`impl W<u32, Reg<u32, _ALRMBSSR>>`[src]

`pub fn maskss(&mut self) -> MASKSS_W`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&mut self) -> SS_W`[src]

Bits 0:14 - Sub seconds value

`impl W<u32, Reg<u32, _BKPR>>`[src]

`pub fn bkp(&mut self) -> BKP_W`[src]

Bits 0:31 - BKP

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn bidimode(&mut self) -> BIDIMODE_W`[src]

Bit 15 - Bidirectional data mode enable

`pub fn bidioe(&mut self) -> BIDIOE_W`[src]

Bit 14 - Output enable in bidirectional mode

`pub fn crcen(&mut self) -> CRCEN_W`[src]

Bit 13 - Hardware CRC calculation enable

`pub fn crcnext(&mut self) -> CRCNEXT_W`[src]

Bit 12 - CRC transfer next

`pub fn dff(&mut self) -> DFF_W`[src]

Bit 11 - Data frame format

`pub fn rxonly(&mut self) -> RXONLY_W`[src]

Bit 10 - Receive only

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 9 - Software slave management

`pub fn ssi(&mut self) -> SSI_W`[src]

Bit 8 - Internal slave select

`pub fn lsbfirst(&mut self) -> LSBFIRST_W`[src]

Bit 7 - Frame format

`pub fn spe(&mut self) -> SPE_W`[src]

Bit 6 - SPI enable

`pub fn br(&mut self) -> BR_W`[src]

Bits 3:5 - Baud rate control

`pub fn mstr(&mut self) -> MSTR_W`[src]

Bit 2 - Master selection

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 1 - Clock polarity

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 0 - Clock phase

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn txeie(&mut self) -> TXEIE_W`[src]

Bit 7 - Tx buffer empty interrupt enable

`pub fn rxneie(&mut self) -> RXNEIE_W`[src]

Bit 6 - RX buffer not empty interrupt enable

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 5 - Error interrupt enable

`pub fn frf(&mut self) -> FRF_W`[src]

Bit 4 - Frame format

`pub fn ssoe(&mut self) -> SSOE_W`[src]

Bit 2 - SS output enable

`pub fn txdmaen(&mut self) -> TXDMAEN_W`[src]

Bit 1 - Tx buffer DMA enable

`pub fn rxdmaen(&mut self) -> RXDMAEN_W`[src]

Bit 0 - Rx buffer DMA enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn crcerr(&mut self) -> CRCERR_W`[src]

Bit 4 - CRC error flag

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:15 - Data register

`impl W<u32, Reg<u32, _CRCPR>>`[src]

`pub fn crcpoly(&mut self) -> CRCPOLY_W`[src]

Bits 0:15 - CRC polynomial register

`impl W<u32, Reg<u32, _I2SCFGR>>`[src]

`pub fn i2smod(&mut self) -> I2SMOD_W`[src]

Bit 11 - I2S mode selection

`pub fn i2se(&mut self) -> I2SE_W`[src]

Bit 10 - I2S Enable

`pub fn i2scfg(&mut self) -> I2SCFG_W`[src]

Bits 8:9 - I2S configuration mode

`pub fn pcmsync(&mut self) -> PCMSYNC_W`[src]

Bit 7 - PCM frame synchronization

`pub fn i2sstd(&mut self) -> I2SSTD_W`[src]

Bits 4:5 - I2S standard selection

`pub fn ckpol(&mut self) -> CKPOL_W`[src]

Bit 3 - Steady state clock polarity

`pub fn datlen(&mut self) -> DATLEN_W`[src]

Bits 1:2 - Data length to be transferred

`pub fn chlen(&mut self) -> CHLEN_W`[src]

Bit 0 - Channel length (number of bits per audio channel)

`impl W<u32, Reg<u32, _I2SPR>>`[src]

`pub fn mckoe(&mut self) -> MCKOE_W`[src]

Bit 9 - Master clock output enable

`pub fn odd(&mut self) -> ODD_W`[src]

Bit 8 - Odd factor for the prescaler

`pub fn i2sdiv(&mut self) -> I2SDIV_W`[src]

Bits 0:7 - I2S Linear prescaler

`impl W<u32, Reg<u32, _MEMRMP>>`[src]

`pub fn mem_mode(&mut self) -> MEM_MODE_W`[src]

Bits 0:1 - MEM_MODE

`impl W<u32, Reg<u32, _PMC>>`[src]

`pub fn usb_pu(&mut self) -> USB_PU_W`[src]

Bit 0 - USB pull-up

`impl W<u32, Reg<u32, _EXTICR1>>`[src]

`pub fn exti3(&mut self) -> EXTI3_W`[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

`pub fn exti2(&mut self) -> EXTI2_W`[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

`pub fn exti1(&mut self) -> EXTI1_W`[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

`pub fn exti0(&mut self) -> EXTI0_W`[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

`impl W<u32, Reg<u32, _EXTICR2>>`[src]

`pub fn exti7(&mut self) -> EXTI7_W`[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

`pub fn exti6(&mut self) -> EXTI6_W`[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

`pub fn exti5(&mut self) -> EXTI5_W`[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

`pub fn exti4(&mut self) -> EXTI4_W`[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

`impl W<u32, Reg<u32, _EXTICR3>>`[src]

`pub fn exti11(&mut self) -> EXTI11_W`[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

`pub fn exti10(&mut self) -> EXTI10_W`[src]

Bits 8:11 - EXTI10

`pub fn exti9(&mut self) -> EXTI9_W`[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

`pub fn exti8(&mut self) -> EXTI8_W`[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

`impl W<u32, Reg<u32, _EXTICR4>>`[src]

`pub fn exti15(&mut self) -> EXTI15_W`[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

`pub fn exti14(&mut self) -> EXTI14_W`[src]

Bits 8:11 - EXTI14

`pub fn exti13(&mut self) -> EXTI13_W`[src]

Bits 4:7 - EXTI13

`pub fn exti12(&mut self) -> EXTI12_W`[src]

Bits 0:3 - EXTI12

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM10 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - TIM11 Input 1 remapping capability

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&mut self) -> CMS_W`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Direction

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn ti1s(&mut self) -> TI1S_W`[src]

Bit 7 - TI1 selection

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&mut self) -> CCDS_W`[src]

Bit 3 - Capture/compare DMA selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&mut self) -> ETP_W`[src]

Bit 15 - External trigger polarity

`pub fn ece(&mut self) -> ECE_W`[src]

Bit 14 - External clock enable

`pub fn etps(&mut self) -> ETPS_W`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&mut self) -> ETF_W`[src]

Bits 8:11 - External trigger filter

`pub fn msm(&mut self) -> MSM_W`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&mut self) -> TS_W`[src]

Bits 4:6 - Trigger selection

`pub fn occs(&mut self) -> OCCS_W`[src]

Bit 3 - OCREF clear selection

`pub fn sms(&mut self) -> SMS_W`[src]

Bits 0:2 - Slave mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn tde(&mut self) -> TDE_W`[src]

Bit 14 - Trigger DMA request enable

`pub fn cc4de(&mut self) -> CC4DE_W`[src]

Bit 12 - Capture/Compare 4 DMA request enable

`pub fn cc3de(&mut self) -> CC3DE_W`[src]

Bit 11 - Capture/Compare 3 DMA request enable

`pub fn cc2de(&mut self) -> CC2DE_W`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&mut self) -> CC1DE_W`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&mut self) -> UDE_W`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&mut self) -> TIE_W`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&mut self) -> CC4IE_W`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&mut self) -> CC3IE_W`[src]

Bit 3 - Capture/Compare 3 interrupt enable

`pub fn cc2ie(&mut self) -> CC2IE_W`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc4of(&mut self) -> CC4OF_W`[src]

Bit 12 - Capture/compare 1 overcapture flag

`pub fn cc3of(&mut self) -> CC3OF_W`[src]

Bit 11 - Capture/compare 3 overcapture flag

`pub fn cc2of(&mut self) -> CC2OF_W`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn tif(&mut self) -> TIF_W`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&mut self) -> CC4IF_W`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&mut self) -> CC3IF_W`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&mut self) -> CC2IF_W`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn tg(&mut self) -> TG_W`[src]

Bit 6 - Trigger generation

`pub fn cc4g(&mut self) -> CC4G_W`[src]

Bit 4 - Capture/compare 4 generation

`pub fn cc3g(&mut self) -> CC3G_W`[src]

Bit 3 - Capture/compare 3 generation

`pub fn cc2g(&mut self) -> CC2G_W`[src]

Bit 2 - Capture/compare 2 generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&mut self) -> OC2CE_W`[src]

Bit 15 - Output compare 2 clear enable

`pub fn oc2m(&mut self) -> OC2M_W`[src]

Bits 12:14 - Output compare 2 mode

`pub fn oc2pe(&mut self) -> OC2PE_W`[src]

Bit 11 - Output compare 2 preload enable

`pub fn oc2fe(&mut self) -> OC2FE_W`[src]

Bit 10 - Output compare 2 fast enable

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bit 8 - Capture/Compare 2 selection

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&mut self) -> IC2F_W`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&mut self) -> IC2PSC_W`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&mut self) -> OC4CE_W`[src]

Bit 15 - Output compare 4 clear enable

`pub fn oc4m(&mut self) -> OC4M_W`[src]

Bits 12:14 - Output compare 4 mode

`pub fn oc4pe(&mut self) -> OC4PE_W`[src]

Bit 11 - Output compare 4 preload enable

`pub fn oc4fe(&mut self) -> OC4FE_W`[src]

Bit 10 - Output compare 4 fast enable

`pub fn cc4s(&mut self) -> CC4S_W`[src]

Bit 8 - Capture/Compare 4 selection

`pub fn oc3ce(&mut self) -> OC3CE_W`[src]

Bit 7 - Output compare 3 clear enable

`pub fn oc3m(&mut self) -> OC3M_W`[src]

Bits 4:6 - Output compare 3 mode

`pub fn oc3pe(&mut self) -> OC3PE_W`[src]

Bit 3 - Output compare 3 preload enable

`pub fn oc3fe(&mut self) -> OC3FE_W`[src]

Bit 2 - Output compare 3 fast enable

`pub fn cc3s(&mut self) -> CC3S_W`[src]

Bits 0:1 - Capture/Compare 3 selection

`impl W<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&mut self) -> IC4F_W`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&mut self) -> IC4PSC_W`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&mut self) -> CC4S_W`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&mut self) -> IC3F_W`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&mut self) -> IC3PSC_W`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&mut self) -> CC3S_W`[src]

Bits 0:1 - Capture/compare 3 selection

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&mut self) -> CC4NP_W`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&mut self) -> CC4P_W`[src]

Bit 13 - Capture/Compare 4 output Polarity

`pub fn cc4e(&mut self) -> CC4E_W`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&mut self) -> CC3NP_W`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&mut self) -> CC3P_W`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&mut self) -> CC3E_W`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&mut self) -> CC2NP_W`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&mut self) -> CC2P_W`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&mut self) -> CC2E_W`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM2 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM2 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&mut self) -> DBL_W`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&mut self) -> DBA_W`[src]

Bits 0:4 - DMA base address

`impl W<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&mut self) -> DMAB_W`[src]

Bits 0:15 - DMA register for burst accesses

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn ude(&mut self) -> UDE_W`[src]

Bit 8 - Update DMA request enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - CNT

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Prescaler value

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn msm(&mut self) -> MSM_W`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&mut self) -> TS_W`[src]

Bits 4:6 - Trigger selection

`pub fn sms(&mut self) -> SMS_W`[src]

Bits 0:2 - Slave mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn tie(&mut self) -> TIE_W`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc2ie(&mut self) -> CC2IE_W`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc2of(&mut self) -> CC2OF_W`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn tif(&mut self) -> TIF_W`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc2if(&mut self) -> CC2IF_W`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn tg(&mut self) -> TG_W`[src]

Bit 6 - Trigger generation

`pub fn cc2g(&mut self) -> CC2G_W`[src]

Bit 2 - Capture/Compare 2 generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&mut self) -> OC2CE_W`[src]

Bit 15 - Output compare 2 clear enable

`pub fn oc2m(&mut self) -> OC2M_W`[src]

Bits 12:14 - Output compare 2 mode

`pub fn oc2pe(&mut self) -> OC2PE_W`[src]

Bit 11 - Output compare 2 preload enable

`pub fn oc2fe(&mut self) -> OC2FE_W`[src]

Bit 10 - Output compare 2 fast enable

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bit 8 - Capture/Compare 2 selection

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&mut self) -> IC2F_W`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&mut self) -> IC2PSC_W`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM9 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - TIM9 Input 1 remapping capability

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 9 - CTS flag

`pub fn lbd(&mut self) -> LBD_W`[src]

Bit 8 - LIN break detection flag

`pub fn tc(&mut self) -> TC_W`[src]

Bit 6 - Transmission complete

`pub fn rxne(&mut self) -> RXNE_W`[src]

Bit 5 - Read data register not empty

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:8 - Data value

`impl W<u32, Reg<u32, _BRR>>`[src]

`pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W`[src]

Bits 4:15 - mantissa of USARTDIV

`pub fn div_fraction(&mut self) -> DIV_FRACTION_W`[src]

Bits 0:3 - fraction of USARTDIV

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn over8(&mut self) -> OVER8_W`[src]

Bit 15 - Oversampling mode

`pub fn ue(&mut self) -> UE_W`[src]

Bit 13 - USART enable

`pub fn m(&mut self) -> M_W`[src]

Bit 12 - Word length

`pub fn wake(&mut self) -> WAKE_W`[src]

Bit 11 - Wakeup method

`pub fn pce(&mut self) -> PCE_W`[src]

Bit 10 - Parity control enable

`pub fn ps(&mut self) -> PS_W`[src]

Bit 9 - Parity selection

`pub fn peie(&mut self) -> PEIE_W`[src]

Bit 8 - PE interrupt enable

`pub fn txeie(&mut self) -> TXEIE_W`[src]

Bit 7 - TXE interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 6 - Transmission complete interrupt enable

`pub fn rxneie(&mut self) -> RXNEIE_W`[src]

Bit 5 - RXNE interrupt enable

`pub fn idleie(&mut self) -> IDLEIE_W`[src]

Bit 4 - IDLE interrupt enable

`pub fn te(&mut self) -> TE_W`[src]

Bit 3 - Transmitter enable

`pub fn re(&mut self) -> RE_W`[src]

Bit 2 - Receiver enable

`pub fn rwu(&mut self) -> RWU_W`[src]

Bit 1 - Receiver wakeup

`pub fn sbk(&mut self) -> SBK_W`[src]

Bit 0 - Send break

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn linen(&mut self) -> LINEN_W`[src]

Bit 14 - LIN mode enable

`pub fn stop(&mut self) -> STOP_W`[src]

Bits 12:13 - STOP bits

`pub fn clken(&mut self) -> CLKEN_W`[src]

Bit 11 - Clock enable

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 10 - Clock polarity

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 9 - Clock phase

`pub fn lbcl(&mut self) -> LBCL_W`[src]

Bit 8 - Last bit clock pulse

`pub fn lbdie(&mut self) -> LBDIE_W`[src]

Bit 6 - LIN break detection interrupt enable

`pub fn lbdl(&mut self) -> LBDL_W`[src]

Bit 5 - lin break detection length

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:3 - Address of the USART node

`impl W<u32, Reg<u32, _CR3>>`[src]

`pub fn onebit(&mut self) -> ONEBIT_W`[src]

Bit 11 - One sample bit method enable

`pub fn ctsie(&mut self) -> CTSIE_W`[src]

Bit 10 - CTS interrupt enable

`pub fn ctse(&mut self) -> CTSE_W`[src]

Bit 9 - CTS enable

`pub fn rtse(&mut self) -> RTSE_W`[src]

Bit 8 - RTS enable

`pub fn dmat(&mut self) -> DMAT_W`[src]

Bit 7 - DMA enable transmitter

`pub fn dmar(&mut self) -> DMAR_W`[src]

Bit 6 - DMA enable receiver

`pub fn scen(&mut self) -> SCEN_W`[src]

Bit 5 - Smartcard mode enable

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 4 - Smartcard NACK enable

`pub fn hdsel(&mut self) -> HDSEL_W`[src]

Bit 3 - Half-duplex selection

`pub fn irlp(&mut self) -> IRLP_W`[src]

Bit 2 - IrDA low-power

`pub fn iren(&mut self) -> IREN_W`[src]

Bit 1 - IrDA mode enable

`pub fn eie(&mut self) -> EIE_W`[src]

Bit 0 - Error interrupt enable

`impl W<u32, Reg<u32, _GTPR>>`[src]

`pub fn gt(&mut self) -> GT_W`[src]

Bits 8:15 - Guard time value

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:7 - Prescaler value

`impl W<u32, Reg<u32, _EP0R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP1R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP2R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP3R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP4R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP5R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP6R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP7R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _CNTR>>`[src]

`pub fn fres(&mut self) -> FRES_W`[src]

Bit 0 - Force USB Reset

`pub fn pdwn(&mut self) -> PDWN_W`[src]

Bit 1 - Power down

`pub fn lpmode(&mut self) -> LPMODE_W`[src]

Bit 2 - Low-power mode

`pub fn fsusp(&mut self) -> FSUSP_W`[src]

Bit 3 - Force suspend

`pub fn resume(&mut self) -> RESUME_W`[src]

Bit 4 - Resume request

`pub fn esofm(&mut self) -> ESOFM_W`[src]

Bit 8 - Expected start of frame interrupt mask

`pub fn sofm(&mut self) -> SOFM_W`[src]

Bit 9 - Start of frame interrupt mask

`pub fn resetm(&mut self) -> RESETM_W`[src]

Bit 10 - USB reset interrupt mask

`pub fn suspm(&mut self) -> SUSPM_W`[src]

Bit 11 - Suspend mode interrupt mask

`pub fn wkupm(&mut self) -> WKUPM_W`[src]

Bit 12 - Wakeup interrupt mask

`pub fn errm(&mut self) -> ERRM_W`[src]

Bit 13 - Error interrupt mask

`pub fn pmaovrm(&mut self) -> PMAOVRM_W`[src]

Bit 14 - Packet memory area over / underrun interrupt mask

`pub fn ctrm(&mut self) -> CTRM_W`[src]

Bit 15 - Correct transfer interrupt mask

`impl W<u32, Reg<u32, _ISTR>>`[src]

`pub fn ep_id(&mut self) -> EP_ID_W`[src]

Bits 0:3 - Endpoint Identifier

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Direction of transaction

`pub fn esof(&mut self) -> ESOF_W`[src]

Bit 8 - Expected start frame

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 9 - start of frame

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 10 - reset request

`pub fn susp(&mut self) -> SUSP_W`[src]

Bit 11 - Suspend mode request

`pub fn wkup(&mut self) -> WKUP_W`[src]

Bit 12 - Wakeup

`pub fn err(&mut self) -> ERR_W`[src]

Bit 13 - Error

`pub fn pmaovr(&mut self) -> PMAOVR_W`[src]

Bit 14 - Packet memory area over / underrun

`pub fn ctr(&mut self) -> CTR_W`[src]

Bit 15 - Correct transfer

`impl W<u32, Reg<u32, _DADDR>>`[src]

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:6 - Device address

`pub fn ef(&mut self) -> EF_W`[src]

Bit 7 - Enable function

`impl W<u32, Reg<u32, _BTABLE>>`[src]

`pub fn btable(&mut self) -> BTABLE_W`[src]

Bits 3:15 - Buffer table

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn wdga(&mut self) -> WDGA_W`[src]

Bit 7 - Activation bit

`pub fn t(&mut self) -> T_W`[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

`impl W<u32, Reg<u32, _CFR>>`[src]

`pub fn ewi(&mut self) -> EWI_W`[src]

Bit 9 - Early wakeup interrupt

`pub fn w(&mut self) -> W_W`[src]

Bits 0:6 - 7-bit window value

`pub fn wdgtb(&mut self) -> WDGTB_W`[src]

Bits 7:8 - Timer base

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn ewif(&mut self) -> EWIF_W`[src]

Bit 0 - EWIF

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn ovr(&mut self) -> OVR_W`[src]

Bit 5 - Overrun

`pub fn strt(&mut self) -> STRT_W`[src]

Bit 4 - Regular channel start flag

`pub fn jstrt(&mut self) -> JSTRT_W`[src]

Bit 3 - Injected channel start flag

`pub fn jeoc(&mut self) -> JEOC_W`[src]

Bit 2 - Injected channel end of conversion

`pub fn eoc(&mut self) -> EOC_W`[src]

Bit 1 - Regular channel end of conversion

`pub fn awd(&mut self) -> AWD_W`[src]

Bit 0 - Analog watchdog flag

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ovrie(&mut self) -> OVRIE_W`[src]

Bit 26 - Overrun interrupt enable

`pub fn res(&mut self) -> RES_W`[src]

Bits 24:25 - Resolution

`pub fn awden(&mut self) -> AWDEN_W`[src]

Bit 23 - Analog watchdog enable on regular channels

`pub fn jawden(&mut self) -> JAWDEN_W`[src]

Bit 22 - Analog watchdog enable on injected channels

`pub fn pdi(&mut self) -> PDI_W`[src]

Bit 17 - Power down during the idle phase

`pub fn pdd(&mut self) -> PDD_W`[src]

Bit 16 - Power down during the delay phase

`pub fn discnum(&mut self) -> DISCNUM_W`[src]

Bits 13:15 - Discontinuous mode channel count

`pub fn jdiscen(&mut self) -> JDISCEN_W`[src]

Bit 12 - Discontinuous mode on injected channels

`pub fn discen(&mut self) -> DISCEN_W`[src]

Bit 11 - Discontinuous mode on regular channels

`pub fn jauto(&mut self) -> JAUTO_W`[src]

Bit 10 - Automatic injected group conversion

`pub fn awdsgl(&mut self) -> AWDSGL_W`[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

`pub fn scan(&mut self) -> SCAN_W`[src]

Bit 8 - Scan mode

`pub fn jeocie(&mut self) -> JEOCIE_W`[src]

Bit 7 - Interrupt enable for injected channels

`pub fn awdie(&mut self) -> AWDIE_W`[src]

Bit 6 - Analog watchdog interrupt enable

`pub fn eocie(&mut self) -> EOCIE_W`[src]

Bit 5 - Interrupt enable for EOC

`pub fn awdch(&mut self) -> AWDCH_W`[src]

Bits 0:4 - Analog watchdog channel select bits

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn swstart(&mut self) -> SWSTART_W`[src]

Bit 30 - Start conversion of regular channels

`pub fn exten(&mut self) -> EXTEN_W`[src]

Bits 28:29 - External trigger enable for regular channels

`pub fn extsel(&mut self) -> EXTSEL_W`[src]

Bits 24:27 - External event select for regular group

`pub fn jswstart(&mut self) -> JSWSTART_W`[src]

Bit 22 - Start conversion of injected channels

`pub fn jexten(&mut self) -> JEXTEN_W`[src]

Bits 20:21 - External trigger enable for injected channels

`pub fn jextsel(&mut self) -> JEXTSEL_W`[src]

Bits 16:19 - External event select for injected group

`pub fn align(&mut self) -> ALIGN_W`[src]

Bit 11 - Data alignment

`pub fn eocs(&mut self) -> EOCS_W`[src]

Bit 10 - End of conversion selection

`pub fn dds(&mut self) -> DDS_W`[src]

Bit 9 - DMA disable selection

`pub fn dma(&mut self) -> DMA_W`[src]

Bit 8 - Direct memory access mode

`pub fn dels(&mut self) -> DELS_W`[src]

Bits 4:6 - Delay selection

`pub fn adc_cfg(&mut self) -> ADC_CFG_W`[src]

Bit 2 - ADC configuration

`pub fn cont(&mut self) -> CONT_W`[src]

Bit 1 - Continuous conversion

`pub fn adon(&mut self) -> ADON_W`[src]

Bit 0 - A/D Converter ON / OFF

`impl W<u32, Reg<u32, _SMPR1>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel sampling time selection

`impl W<u32, Reg<u32, _SMPR2>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel sampling time selection

`impl W<u32, Reg<u32, _SMPR3>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel Sample time selection

`impl W<u32, Reg<u32, _JOFR1>>`[src]

`pub fn joffset1(&mut self) -> JOFFSET1_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR2>>`[src]

`pub fn joffset2(&mut self) -> JOFFSET2_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR3>>`[src]

`pub fn joffset3(&mut self) -> JOFFSET3_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR4>>`[src]

`pub fn joffset4(&mut self) -> JOFFSET4_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _HTR>>`[src]

`pub fn ht(&mut self) -> HT_W`[src]

Bits 0:11 - Analog watchdog higher threshold

`impl W<u32, Reg<u32, _LTR>>`[src]

`pub fn lt(&mut self) -> LT_W`[src]

Bits 0:11 - Analog watchdog lower threshold

`impl W<u32, Reg<u32, _SQR1>>`[src]

`pub fn l(&mut self) -> L_W`[src]

Bits 20:23 - Regular channel sequence length

`pub fn sq28(&mut self) -> SQ28_W`[src]

Bits 15:19 - 28th conversion in regular sequence

`pub fn sq27(&mut self) -> SQ27_W`[src]

Bits 10:14 - 27th conversion in regular sequence

`pub fn sq26(&mut self) -> SQ26_W`[src]

Bits 5:9 - 26th conversion in regular sequence

`pub fn sq25(&mut self) -> SQ25_W`[src]

Bits 0:4 - 25th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR2>>`[src]

`pub fn sq24(&mut self) -> SQ24_W`[src]

Bits 25:29 - 24th conversion in regular sequence

`pub fn sq23(&mut self) -> SQ23_W`[src]

Bits 20:24 - 23rd conversion in regular sequence

`pub fn sq22(&mut self) -> SQ22_W`[src]

Bits 15:19 - 22nd conversion in regular sequence

`pub fn sq21(&mut self) -> SQ21_W`[src]

Bits 10:14 - 21st conversion in regular sequence

`pub fn sq20(&mut self) -> SQ20_W`[src]

Bits 5:9 - 20th conversion in regular sequence

`pub fn sq19(&mut self) -> SQ19_W`[src]

Bits 0:4 - 19th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR3>>`[src]

`pub fn sq18(&mut self) -> SQ18_W`[src]

Bits 25:29 - 18th conversion in regular sequence

`pub fn sq17(&mut self) -> SQ17_W`[src]

Bits 20:24 - 17th conversion in regular sequence

`pub fn sq16(&mut self) -> SQ16_W`[src]

Bits 15:19 - 16th conversion in regular sequence

`pub fn sq15(&mut self) -> SQ15_W`[src]

Bits 10:14 - 15th conversion in regular sequence

`pub fn sq14(&mut self) -> SQ14_W`[src]

Bits 5:9 - 14th conversion in regular sequence

`pub fn sq13(&mut self) -> SQ13_W`[src]

Bits 0:4 - 13th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR4>>`[src]

`pub fn sq12(&mut self) -> SQ12_W`[src]

Bits 25:29 - 12th conversion in regular sequence

`pub fn sq11(&mut self) -> SQ11_W`[src]

Bits 20:24 - 11th conversion in regular sequence

`pub fn sq10(&mut self) -> SQ10_W`[src]

Bits 15:19 - 10th conversion in regular sequence

`pub fn sq9(&mut self) -> SQ9_W`[src]

Bits 10:14 - 9th conversion in regular sequence

`pub fn sq8(&mut self) -> SQ8_W`[src]

Bits 5:9 - 8th conversion in regular sequence

`pub fn sq7(&mut self) -> SQ7_W`[src]

Bits 0:4 - 7th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR5>>`[src]

`pub fn sq6(&mut self) -> SQ6_W`[src]

Bits 25:29 - 6th conversion in regular sequence

`pub fn sq5(&mut self) -> SQ5_W`[src]

Bits 20:24 - 5th conversion in regular sequence

`pub fn sq4(&mut self) -> SQ4_W`[src]

Bits 15:19 - 4th conversion in regular sequence

`pub fn sq3(&mut self) -> SQ3_W`[src]

Bits 10:14 - 3rd conversion in regular sequence

`pub fn sq2(&mut self) -> SQ2_W`[src]

Bits 5:9 - 2nd conversion in regular sequence

`pub fn sq1(&mut self) -> SQ1_W`[src]

Bits 0:4 - 1st conversion in regular sequence

`impl W<u32, Reg<u32, _JSQR>>`[src]

`pub fn jl(&mut self) -> JL_W`[src]

Bits 20:21 - Injected sequence length

`pub fn jsq4(&mut self) -> JSQ4_W`[src]

Bits 15:19 - 4th conversion in injected sequence

`pub fn jsq3(&mut self) -> JSQ3_W`[src]

Bits 10:14 - 3rd conversion in injected sequence

`pub fn jsq2(&mut self) -> JSQ2_W`[src]

Bits 5:9 - 2nd conversion in injected sequence

`pub fn jsq1(&mut self) -> JSQ1_W`[src]

Bits 0:4 - 1st conversion in injected sequence

`impl W<u32, Reg<u32, _SMPR0>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:5 - Channel Sample time selection

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn adcpre(&mut self) -> ADCPRE_W`[src]

Bits 16:17 - ADC prescaler

`pub fn tsvrefe(&mut self) -> TSVREFE_W`[src]

Bit 23 - Temperature sensor and VREFINT enable

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W`[src]

Bit 0 - Debug Sleep mode

`pub fn dbg_stop(&mut self) -> DBG_STOP_W`[src]

Bit 1 - Debug Stop mode

`pub fn dbg_standby(&mut self) -> DBG_STANDBY_W`[src]

Bit 2 - Debug Standby mode

`pub fn trace_ioen(&mut self) -> TRACE_IOEN_W`[src]

Bit 5 - Trace pin assignment control

`pub fn trace_mode(&mut self) -> TRACE_MODE_W`[src]

Bits 6:7 - Trace pin assignment control

`impl W<u32, Reg<u32, _APB1_FZ>>`[src]

`pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W`[src]

Bit 0 - TIM2 counter stopped when core is halted

`pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W`[src]

Bit 1 - TIM3 counter stopped when core is halted

`pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W`[src]

Bit 2 - TIM4 counter stopped when core is halted

`pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W`[src]

Bit 3 - TIM5 counter stopped when core is halted

`pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W`[src]

Bit 4 - TIM6 counter stopped when core is halted

`pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W`[src]

Bit 5 - TIM7 counter stopped when core is halted

`pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W`[src]

Bit 10 - Debug RTC stopped when core is halted

`pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W`[src]

Bit 11 - Debug window watchdog stopped when core is halted

`pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W`[src]

Bit 12 - Debug independent watchdog stopped when core is halted

`pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W`[src]

Bit 21 - SMBUS timeout mode stopped when core is halted

`pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W`[src]

Bit 22 - SMBUS timeout mode stopped when core is halted

`impl W<u32, Reg<u32, _APB2_FZ>>`[src]

`pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W`[src]

Bit 2 - TIM counter stopped when core is halted

`pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W`[src]

Bit 3 - TIM counter stopped when core is halted

`pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W`[src]

Bit 4 - TIM counter stopped when core is halted

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn pwrctrl(&mut self) -> PWRCTRL_W`[src]

Bits 0:1 - Power supply control bits.

`impl W<u32, Reg<u32, _CLKCR>>`[src]

`pub fn hwfc_en(&mut self) -> HWFC_EN_W`[src]

Bit 14 - HW Flow Control enable

`pub fn negedge(&mut self) -> NEGEDGE_W`[src]

Bit 13 - SDIO_CK dephasing selection bit

`pub fn widbus(&mut self) -> WIDBUS_W`[src]

Bits 11:12 - Wide bus mode enable bit

`pub fn bypass(&mut self) -> BYPASS_W`[src]

Bit 10 - Clock divider bypass enable bit

`pub fn pwrsav(&mut self) -> PWRSAV_W`[src]

Bit 9 - Power saving configuration bit

`pub fn clken(&mut self) -> CLKEN_W`[src]

Bit 8 - Clock enable bit

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 0:7 - Clock divide factor

`impl W<u32, Reg<u32, _ARG>>`[src]

`pub fn cmdarg(&mut self) -> CMDARG_W`[src]

Bits 0:31 - Command argument

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn ce_atacmd(&mut self) -> CE_ATACMD_W`[src]

Bit 14 - CE-ATA command

`pub fn n_ien(&mut self) -> NIEN_W`[src]

Bit 13 - not Interrupt Enable

`pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W`[src]

Bit 12 - Enable CMD completion

`pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W`[src]

Bit 11 - SD I/O suspend command

`pub fn cpsmen(&mut self) -> CPSMEN_W`[src]

Bit 10 - Command path state machine (CPSM) Enable bit

`pub fn waitpend(&mut self) -> WAITPEND_W`[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

`pub fn waitint(&mut self) -> WAITINT_W`[src]

Bit 8 - CPSM waits for interrupt request

`pub fn waitresp(&mut self) -> WAITRESP_W`[src]

Bits 6:7 - Wait for response bits

`pub fn cmdindex(&mut self) -> CMDINDEX_W`[src]

Bits 0:5 - Command index

`impl W<u32, Reg<u32, _DTIMER>>`[src]

`pub fn datatime(&mut self) -> DATATIME_W`[src]

Bits 0:31 - Data timeout period

`impl W<u32, Reg<u32, _DLEN>>`[src]

`pub fn datalength(&mut self) -> DATALENGTH_W`[src]

Bits 0:24 - Data length value

`impl W<u32, Reg<u32, _DCTRL>>`[src]

`pub fn sdioen(&mut self) -> SDIOEN_W`[src]

Bit 11 - SD I/O enable functions

`pub fn rwmod(&mut self) -> RWMOD_W`[src]

Bit 10 - Read wait mode

`pub fn rwstop(&mut self) -> RWSTOP_W`[src]

Bit 9 - Read wait stop

`pub fn rwstart(&mut self) -> RWSTART_W`[src]

Bit 8 - Read wait start

`pub fn dblocksize(&mut self) -> DBLOCKSIZE_W`[src]

Bits 4:7 - Data block size

`pub fn dmaen(&mut self) -> DMAEN_W`[src]

Bit 3 - DMA enable bit

`pub fn dtmode(&mut self) -> DTMODE_W`[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

`pub fn dtdir(&mut self) -> DTDIR_W`[src]

Bit 1 - Data transfer direction selection

`pub fn dten(&mut self) -> DTEN_W`[src]

Bit 0 - Data transfer enabled bit

`impl W<u32, Reg<u32, _ICR>>`[src]

`pub fn ceataendc(&mut self) -> CEATAENDC_W`[src]

Bit 23 - CEATAEND flag clear bit

`pub fn sdioitc(&mut self) -> SDIOITC_W`[src]

Bit 22 - SDIOIT flag clear bit

`pub fn dbckendc(&mut self) -> DBCKENDC_W`[src]

Bit 10 - DBCKEND flag clear bit

`pub fn stbiterrc(&mut self) -> STBITERRC_W`[src]

Bit 9 - STBITERR flag clear bit

`pub fn dataendc(&mut self) -> DATAENDC_W`[src]

Bit 8 - DATAEND flag clear bit

`pub fn cmdsentc(&mut self) -> CMDSENTC_W`[src]

Bit 7 - CMDSENT flag clear bit

`pub fn cmdrendc(&mut self) -> CMDRENDC_W`[src]

Bit 6 - CMDREND flag clear bit

`pub fn rxoverrc(&mut self) -> RXOVERRC_W`[src]

Bit 5 - RXOVERR flag clear bit

`pub fn txunderrc(&mut self) -> TXUNDERRC_W`[src]

Bit 4 - TXUNDERR flag clear bit

`pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W`[src]

Bit 3 - DTIMEOUT flag clear bit

`pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W`[src]

Bit 2 - CTIMEOUT flag clear bit

`pub fn dcrcfailc(&mut self) -> DCRCFAILC_W`[src]

Bit 1 - DCRCFAIL flag clear bit

`pub fn ccrcfailc(&mut self) -> CCRCFAILC_W`[src]

Bit 0 - CCRCFAIL flag clear bit

`impl W<u32, Reg<u32, _MASK>>`[src]

`pub fn ceataendie(&mut self) -> CEATAENDIE_W`[src]

Bit 23 - CE-ATA command completion signal received interrupt enable

`pub fn sdioitie(&mut self) -> SDIOITIE_W`[src]

Bit 22 - SDIO mode interrupt received interrupt enable

`pub fn rxdavlie(&mut self) -> RXDAVLIE_W`[src]

Bit 21 - Data available in Rx FIFO interrupt enable

`pub fn txdavlie(&mut self) -> TXDAVLIE_W`[src]

Bit 20 - Data available in Tx FIFO interrupt enable

`pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W`[src]

Bit 19 - Rx FIFO empty interrupt enable

`pub fn txfifoeie(&mut self) -> TXFIFOEIE_W`[src]

Bit 18 - Tx FIFO empty interrupt enable

`pub fn rxfifofie(&mut self) -> RXFIFOFIE_W`[src]

Bit 17 - Rx FIFO full interrupt enable

`pub fn txfifofie(&mut self) -> TXFIFOFIE_W`[src]

Bit 16 - Tx FIFO full interrupt enable

`pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W`[src]

Bit 15 - Rx FIFO half full interrupt enable

`pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W`[src]

Bit 14 - Tx FIFO half empty interrupt enable

`pub fn rxactie(&mut self) -> RXACTIE_W`[src]

Bit 13 - Data receive acting interrupt enable

`pub fn txactie(&mut self) -> TXACTIE_W`[src]

Bit 12 - Data transmit acting interrupt enable

`pub fn cmdactie(&mut self) -> CMDACTIE_W`[src]

Bit 11 - Command acting interrupt enable

`pub fn dbckendie(&mut self) -> DBCKENDIE_W`[src]

Bit 10 - Data block end interrupt enable

`pub fn stbiterrie(&mut self) -> STBITERRIE_W`[src]

Bit 9 - Start bit error interrupt enable

`pub fn dataendie(&mut self) -> DATAENDIE_W`[src]

Bit 8 - Data end interrupt enable

`pub fn cmdsentie(&mut self) -> CMDSENTIE_W`[src]

Bit 7 - Command sent interrupt enable

`pub fn cmdrendie(&mut self) -> CMDRENDIE_W`[src]

Bit 6 - Command response received interrupt enable

`pub fn rxoverrie(&mut self) -> RXOVERRIE_W`[src]

Bit 5 - Rx FIFO overrun error interrupt enable

`pub fn txunderrie(&mut self) -> TXUNDERRIE_W`[src]

Bit 4 - Tx FIFO underrun error interrupt enable

`pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W`[src]

Bit 3 - Data timeout interrupt enable

`pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W`[src]

Bit 2 - Command timeout interrupt enable

`pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W`[src]

Bit 1 - Data CRC fail interrupt enable

`pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W`[src]

Bit 0 - Command CRC fail interrupt enable

`impl W<u32, Reg<u32, _FIFO>>`[src]

`pub fn fif0data(&mut self) -> FIF0DATA_W`[src]

Bits 0:31 - FIF0Data

`impl W<u32, Reg<u32, _ACTRL>>`[src]

`pub fn disfold(&mut self) -> DISFOLD_W`[src]

Bit 2 - DISFOLD

`pub fn fpexcodis(&mut self) -> FPEXCODIS_W`[src]

Bit 10 - FPEXCODIS

`pub fn disramode(&mut self) -> DISRAMODE_W`[src]

Bit 11 - DISRAMODE

`pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W`[src]

Bit 12 - DISITMATBFLUSH

`impl W<u32, Reg<u32, _STIR>>`[src]

`pub fn intid(&mut self) -> INTID_W`[src]

Bits 0:8 - Software generated interrupt ID

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Counter enable

`pub fn tickint(&mut self) -> TICKINT_W`[src]

Bit 1 - SysTick exception request enable

`pub fn clksource(&mut self) -> CLKSOURCE_W`[src]

Bit 2 - Clock source selection

`pub fn countflag(&mut self) -> COUNTFLAG_W`[src]

Bit 16 - COUNTFLAG

`impl W<u32, Reg<u32, _LOAD_>>`[src]

`pub fn reload(&mut self) -> RELOAD_W`[src]

Bits 0:23 - RELOAD value

`impl W<u32, Reg<u32, _VAL>>`[src]

`pub fn current(&mut self) -> CURRENT_W`[src]

Bits 0:23 - Current counter value

`impl W<u32, Reg<u32, _CALIB>>`[src]

`pub fn tenms(&mut self) -> TENMS_W`[src]

Bits 0:23 - Calibration value

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaouten(&mut self) -> DMAOUTEN_W`[src]

Bit 12 - Enable DMA management of data output phase

`pub fn dmainen(&mut self) -> DMAINEN_W`[src]

Bit 11 - Enable DMA management of data input phase

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 10 - Error interrupt enable

`pub fn ccfie(&mut self) -> CCFIE_W`[src]

Bit 9 - CCF flag interrupt enable

`pub fn errc(&mut self) -> ERRC_W`[src]

Bit 8 - Error clear

`pub fn ccfc(&mut self) -> CCFC_W`[src]

Bit 7 - Computation Complete Flag Clear

`pub fn chmod(&mut self) -> CHMOD_W`[src]

Bits 5:6 - AES chaining mode

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 3:4 - AES operating mode

`pub fn datatype(&mut self) -> DATATYPE_W`[src]

Bits 1:2 - Data type selection

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - AES enable

`impl W<u32, Reg<u32, _DINR>>`[src]

`pub fn dinr(&mut self) -> DINR_W`[src]

Bits 0:31 - Data input

`impl W<u32, Reg<u32, _KEYR0>>`[src]

`pub fn keyr0(&mut self) -> KEYR0_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR1>>`[src]

`pub fn keyr1(&mut self) -> KEYR1_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR2>>`[src]

`pub fn keyr2(&mut self) -> KEYR2_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR3>>`[src]

`pub fn keyr3(&mut self) -> KEYR3_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _IVR0>>`[src]

`pub fn ivr0(&mut self) -> IVR0_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR1>>`[src]

`pub fn ivr1(&mut self) -> IVR1_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR2>>`[src]

`pub fn ivr2(&mut self) -> IVR2_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR3>>`[src]

`pub fn ivr3(&mut self) -> IVR3_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn tsusp(&mut self) -> TSUSP_W`[src]

Bit 31 - Suspend Timer Mode

`pub fn caie(&mut self) -> CAIE_W`[src]

Bit 29 - Channel Acquisition Interrupt Enable / Clear

`pub fn rch13(&mut self) -> RCH13_W`[src]

Bit 28 - Select GPIO port PC3 as re-routed ADC input channel CH13.

`pub fn fch8(&mut self) -> FCH8_W`[src]

Bit 27 - Select GPIO port PB0 as fast ADC input channel CH8.

`pub fn fch3(&mut self) -> FCH3_W`[src]

Bit 26 - Select GPIO port PA3 as fast ADC input channel CH3.

`pub fn outsel(&mut self) -> OUTSEL_W`[src]

Bits 21:23 - Comparator 2 output selection

`pub fn insel(&mut self) -> INSEL_W`[src]

Bits 18:20 - Inverted input selection

`pub fn wndwe(&mut self) -> WNDWE_W`[src]

Bit 17 - Window mode enable

`pub fn vrefouten(&mut self) -> VREFOUTEN_W`[src]

Bit 16 - VREFINT output enable

`pub fn speed(&mut self) -> SPEED_W`[src]

Bit 12 - Comparator 2 speed mode

`pub fn sw1(&mut self) -> SW1_W`[src]

Bit 5 - SW1 analog switch enable

`pub fn cmp1en(&mut self) -> CMP1EN_W`[src]

Bit 4 - Comparator 1 enable

`pub fn pd400k(&mut self) -> PD400K_W`[src]

Bit 3 - 400 kO pull-down resistor

`pub fn pd10k(&mut self) -> PD10K_W`[src]

Bit 2 - 10 kO pull-down resistor

`pub fn pu400k(&mut self) -> PU400K_W`[src]

Bit 1 - 400 kO pull-up resistor

`pub fn pu10k(&mut self) -> PU10K_W`[src]

Bit 0 - 10 kO pull-up resistor

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:31 - Data Register

`impl W<u32, Reg<u32, _IDR>>`[src]

`pub fn idr(&mut self) -> IDR_W`[src]

Bits 0:6 - Independent data register

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 0 - RESET

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W`[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

`pub fn dmaen2(&mut self) -> DMAEN2_W`[src]

Bit 28 - DAC channel2 DMA enable

`pub fn mamp2(&mut self) -> MAMP2_W`[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

`pub fn wave2(&mut self) -> WAVE2_W`[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

`pub fn tsel2(&mut self) -> TSEL2_W`[src]

Bits 19:21 - DAC channel2 trigger selection

`pub fn ten2(&mut self) -> TEN2_W`[src]

Bit 18 - DAC channel2 trigger enable

`pub fn boff2(&mut self) -> BOFF2_W`[src]

Bit 17 - DAC channel2 output buffer disable

`pub fn en2(&mut self) -> EN2_W`[src]

Bit 16 - DAC channel2 enable

`pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W`[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

`pub fn dmaen1(&mut self) -> DMAEN1_W`[src]

Bit 12 - DAC channel1 DMA enable

`pub fn mamp1(&mut self) -> MAMP1_W`[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

`pub fn wave1(&mut self) -> WAVE1_W`[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

`pub fn tsel1(&mut self) -> TSEL1_W`[src]

Bits 3:5 - DAC channel1 trigger selection

`pub fn ten1(&mut self) -> TEN1_W`[src]

Bit 2 - DAC channel1 trigger enable

`pub fn boff1(&mut self) -> BOFF1_W`[src]

Bit 1 - DAC channel1 output buffer disable

`pub fn en1(&mut self) -> EN1_W`[src]

Bit 0 - DAC channel1 enable

`impl W<u32, Reg<u32, _SWTRIGR>>`[src]

`pub fn swtrig2(&mut self) -> SWTRIG2_W`[src]

Bit 1 - DAC channel2 software trigger

`pub fn swtrig1(&mut self) -> SWTRIG1_W`[src]

Bit 0 - DAC channel1 software trigger

`impl W<u32, Reg<u32, _DHR12R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12L1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12R2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12L2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8R2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12RD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12LD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8RD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn dmaudr2(&mut self) -> DMAUDR2_W`[src]

Bit 29 - DAC channel2 DMA underrun flag

`pub fn dmaudr1(&mut self) -> DMAUDR1_W`[src]

Bit 13 - DAC channel1 DMA underrun flag

`impl W<u32, Reg<u32, _IFCR>>`[src]

`pub fn cteif7(&mut self) -> CTEIF7_W`[src]

Bit 27 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif7(&mut self) -> CHTIF7_W`[src]

Bit 26 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif7(&mut self) -> CTCIF7_W`[src]

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif7(&mut self) -> CGIF7_W`[src]

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif6(&mut self) -> CTEIF6_W`[src]

Bit 23 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif6(&mut self) -> CHTIF6_W`[src]

Bit 22 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif6(&mut self) -> CTCIF6_W`[src]

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif6(&mut self) -> CGIF6_W`[src]

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif5(&mut self) -> CTEIF5_W`[src]

Bit 19 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif5(&mut self) -> CHTIF5_W`[src]

Bit 18 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif5(&mut self) -> CTCIF5_W`[src]

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif5(&mut self) -> CGIF5_W`[src]

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif4(&mut self) -> CTEIF4_W`[src]

Bit 15 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif4(&mut self) -> CHTIF4_W`[src]

Bit 14 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif4(&mut self) -> CTCIF4_W`[src]

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif4(&mut self) -> CGIF4_W`[src]

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif3(&mut self) -> CTEIF3_W`[src]

Bit 11 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif3(&mut self) -> CHTIF3_W`[src]

Bit 10 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif3(&mut self) -> CTCIF3_W`[src]

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif3(&mut self) -> CGIF3_W`[src]

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif2(&mut self) -> CTEIF2_W`[src]

Bit 7 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif2(&mut self) -> CHTIF2_W`[src]

Bit 6 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif2(&mut self) -> CTCIF2_W`[src]

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif2(&mut self) -> CGIF2_W`[src]

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif1(&mut self) -> CTEIF1_W`[src]

Bit 3 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif1(&mut self) -> CHTIF1_W`[src]

Bit 2 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif1(&mut self) -> CTCIF1_W`[src]

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif1(&mut self) -> CGIF1_W`[src]

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

`impl W<u32, Reg<u32, _CCR1>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR1>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR1>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR1>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR2>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR2>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR2>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR2>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR3>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR3>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR3>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR3>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR4>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR4>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR4>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR4>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR5>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR5>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR5>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR5>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR6>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR6>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR6>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR6>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR7>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR7>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR7>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR7>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _IMR>>`[src]

`pub fn mr0(&mut self) -> MR0_W`[src]

Bit 0 - Interrupt mask on line x

`pub fn mr1(&mut self) -> MR1_W`[src]

Bit 1 - Interrupt mask on line x

`pub fn mr2(&mut self) -> MR2_W`[src]

Bit 2 - Interrupt mask on line x

`pub fn mr3(&mut self) -> MR3_W`[src]

Bit 3 - Interrupt mask on line x

`pub fn mr4(&mut self) -> MR4_W`[src]

Bit 4 - Interrupt mask on line x

`pub fn mr5(&mut self) -> MR5_W`[src]

Bit 5 - Interrupt mask on line x

`pub fn mr6(&mut self) -> MR6_W`[src]

Bit 6 - Interrupt mask on line x

`pub fn mr7(&mut self) -> MR7_W`[src]

Bit 7 - Interrupt mask on line x

`pub fn mr8(&mut self) -> MR8_W`[src]

Bit 8 - Interrupt mask on line x

`pub fn mr9(&mut self) -> MR9_W`[src]

Bit 9 - Interrupt mask on line x

`pub fn mr10(&mut self) -> MR10_W`[src]

Bit 10 - Interrupt mask on line x

`pub fn mr11(&mut self) -> MR11_W`[src]

Bit 11 - Interrupt mask on line x

`pub fn mr12(&mut self) -> MR12_W`[src]

Bit 12 - Interrupt mask on line x

`pub fn mr13(&mut self) -> MR13_W`[src]

Bit 13 - Interrupt mask on line x

`pub fn mr14(&mut self) -> MR14_W`[src]

Bit 14 - Interrupt mask on line x

`pub fn mr15(&mut self) -> MR15_W`[src]

Bit 15 - Interrupt mask on line x

`pub fn mr16(&mut self) -> MR16_W`[src]

Bit 16 - Interrupt mask on line x

`pub fn mr17(&mut self) -> MR17_W`[src]

Bit 17 - Interrupt mask on line x

`pub fn mr18(&mut self) -> MR18_W`[src]

Bit 18 - Interrupt mask on line x

`pub fn mr19(&mut self) -> MR19_W`[src]

Bit 19 - Interrupt mask on line x

`pub fn mr20(&mut self) -> MR20_W`[src]

Bit 20 - Interrupt mask on line x

`pub fn mr21(&mut self) -> MR21_W`[src]

Bit 21 - Interrupt mask on line x

`pub fn mr22(&mut self) -> MR22_W`[src]

Bit 22 - Interrupt mask on line x

`impl W<u32, Reg<u32, _EMR>>`[src]

`pub fn mr0(&mut self) -> MR0_W`[src]

Bit 0 - Event mask on line x

`pub fn mr1(&mut self) -> MR1_W`[src]

Bit 1 - Event mask on line x

`pub fn mr2(&mut self) -> MR2_W`[src]

Bit 2 - Event mask on line x

`pub fn mr3(&mut self) -> MR3_W`[src]

Bit 3 - Event mask on line x

`pub fn mr4(&mut self) -> MR4_W`[src]

Bit 4 - Event mask on line x

`pub fn mr5(&mut self) -> MR5_W`[src]

Bit 5 - Event mask on line x

`pub fn mr6(&mut self) -> MR6_W`[src]

Bit 6 - Event mask on line x

`pub fn mr7(&mut self) -> MR7_W`[src]

Bit 7 - Event mask on line x

`pub fn mr8(&mut self) -> MR8_W`[src]

Bit 8 - Event mask on line x

`pub fn mr9(&mut self) -> MR9_W`[src]

Bit 9 - Event mask on line x

`pub fn mr10(&mut self) -> MR10_W`[src]

Bit 10 - Event mask on line x

`pub fn mr11(&mut self) -> MR11_W`[src]

Bit 11 - Event mask on line x

`pub fn mr12(&mut self) -> MR12_W`[src]

Bit 12 - Event mask on line x

`pub fn mr13(&mut self) -> MR13_W`[src]

Bit 13 - Event mask on line x

`pub fn mr14(&mut self) -> MR14_W`[src]

Bit 14 - Event mask on line x

`pub fn mr15(&mut self) -> MR15_W`[src]

Bit 15 - Event mask on line x

`pub fn mr16(&mut self) -> MR16_W`[src]

Bit 16 - Event mask on line x

`pub fn mr17(&mut self) -> MR17_W`[src]

Bit 17 - Event mask on line x

`pub fn mr18(&mut self) -> MR18_W`[src]

Bit 18 - Event mask on line x

`pub fn mr19(&mut self) -> MR19_W`[src]

Bit 19 - Event mask on line x

`pub fn mr20(&mut self) -> MR20_W`[src]

Bit 20 - Event mask on line x

`pub fn mr21(&mut self) -> MR21_W`[src]

Bit 21 - Event mask on line x

`pub fn mr22(&mut self) -> MR22_W`[src]

Bit 22 - Event mask on line x

`impl W<u32, Reg<u32, _RTSR>>`[src]

`pub fn tr0(&mut self) -> TR0_W`[src]

Bit 0 - Rising edge trigger event configuration bit of line x

`pub fn tr1(&mut self) -> TR1_W`[src]

Bit 1 - Rising edge trigger event configuration bit of line x

`pub fn tr2(&mut self) -> TR2_W`[src]

Bit 2 - Rising edge trigger event configuration bit of line x

`pub fn tr3(&mut self) -> TR3_W`[src]

Bit 3 - Rising edge trigger event configuration bit of line x

`pub fn tr4(&mut self) -> TR4_W`[src]

Bit 4 - Rising edge trigger event configuration bit of line x

`pub fn tr5(&mut self) -> TR5_W`[src]

Bit 5 - Rising edge trigger event configuration bit of line x

`pub fn tr6(&mut self) -> TR6_W`[src]

Bit 6 - Rising edge trigger event configuration bit of line x

`pub fn tr7(&mut self) -> TR7_W`[src]

Bit 7 - Rising edge trigger event configuration bit of line x

`pub fn tr8(&mut self) -> TR8_W`[src]

Bit 8 - Rising edge trigger event configuration bit of line x

`pub fn tr9(&mut self) -> TR9_W`[src]

Bit 9 - Rising edge trigger event configuration bit of line x

`pub fn tr10(&mut self) -> TR10_W`[src]

Bit 10 - Rising edge trigger event configuration bit of line x

`pub fn tr11(&mut self) -> TR11_W`[src]

Bit 11 - Rising edge trigger event configuration bit of line x

`pub fn tr12(&mut self) -> TR12_W`[src]

Bit 12 - Rising edge trigger event configuration bit of line x

`pub fn tr13(&mut self) -> TR13_W`[src]

Bit 13 - Rising edge trigger event configuration bit of line x

`pub fn tr14(&mut self) -> TR14_W`[src]

Bit 14 - Rising edge trigger event configuration bit of line x

`pub fn tr15(&mut self) -> TR15_W`[src]

Bit 15 - Rising edge trigger event configuration bit of line x

`pub fn tr16(&mut self) -> TR16_W`[src]

Bit 16 - Rising edge trigger event configuration bit of line x

`pub fn tr17(&mut self) -> TR17_W`[src]

Bit 17 - Rising edge trigger event configuration bit of line x

`pub fn tr18(&mut self) -> TR18_W`[src]

Bit 18 - Rising edge trigger event configuration bit of line x

`pub fn tr19(&mut self) -> TR19_W`[src]

Bit 19 - Rising edge trigger event configuration bit of line x

`pub fn tr20(&mut self) -> TR20_W`[src]

Bit 20 - Rising edge trigger event configuration bit of line x

`pub fn tr21(&mut self) -> TR21_W`[src]

Bit 21 - Rising edge trigger event configuration bit of line x

`pub fn tr22(&mut self) -> TR22_W`[src]

Bit 22 - Rising edge trigger event configuration bit of line x

`impl W<u32, Reg<u32, _FTSR>>`[src]

`pub fn tr0(&mut self) -> TR0_W`[src]

Bit 0 - Falling edge trigger event configuration bit of line x

`pub fn tr1(&mut self) -> TR1_W`[src]

Bit 1 - Falling edge trigger event configuration bit of line x

`pub fn tr2(&mut self) -> TR2_W`[src]

Bit 2 - Falling edge trigger event configuration bit of line x

`pub fn tr3(&mut self) -> TR3_W`[src]

Bit 3 - Falling edge trigger event configuration bit of line x

`pub fn tr4(&mut self) -> TR4_W`[src]

Bit 4 - Falling edge trigger event configuration bit of line x

`pub fn tr5(&mut self) -> TR5_W`[src]

Bit 5 - Falling edge trigger event configuration bit of line x

`pub fn tr6(&mut self) -> TR6_W`[src]

Bit 6 - Falling edge trigger event configuration bit of line x

`pub fn tr7(&mut self) -> TR7_W`[src]

Bit 7 - Falling edge trigger event configuration bit of line x

`pub fn tr8(&mut self) -> TR8_W`[src]

Bit 8 - Falling edge trigger event configuration bit of line x

`pub fn tr9(&mut self) -> TR9_W`[src]

Bit 9 - Falling edge trigger event configuration bit of line x

`pub fn tr10(&mut self) -> TR10_W`[src]

Bit 10 - Falling edge trigger event configuration bit of line x

`pub fn tr11(&mut self) -> TR11_W`[src]

Bit 11 - Falling edge trigger event configuration bit of line x

`pub fn tr12(&mut self) -> TR12_W`[src]

Bit 12 - Falling edge trigger event configuration bit of line x

`pub fn tr13(&mut self) -> TR13_W`[src]

Bit 13 - Falling edge trigger event configuration bit of line x

`pub fn tr14(&mut self) -> TR14_W`[src]

Bit 14 - Falling edge trigger event configuration bit of line x

`pub fn tr15(&mut self) -> TR15_W`[src]

Bit 15 - Falling edge trigger event configuration bit of line x

`pub fn tr16(&mut self) -> TR16_W`[src]

Bit 16 - Falling edge trigger event configuration bit of line x

`pub fn tr17(&mut self) -> TR17_W`[src]

Bit 17 - Falling edge trigger event configuration bit of line x

`pub fn tr18(&mut self) -> TR18_W`[src]

Bit 18 - Falling edge trigger event configuration bit of line x

`pub fn tr19(&mut self) -> TR19_W`[src]

Bit 19 - Falling edge trigger event configuration bit of line x

`pub fn tr20(&mut self) -> TR20_W`[src]

Bit 20 - Falling edge trigger event configuration bit of line x

`pub fn tr21(&mut self) -> TR21_W`[src]

Bit 21 - Falling edge trigger event configuration bit of line x

`pub fn tr22(&mut self) -> TR22_W`[src]

Bit 22 - Falling edge trigger event configuration bit of line x

`impl W<u32, Reg<u32, _SWIER>>`[src]

`pub fn swier0(&mut self) -> SWIER0_W`[src]

Bit 0 - Software interrupt on line x

`pub fn swier1(&mut self) -> SWIER1_W`[src]

Bit 1 - Software interrupt on line x

`pub fn swier2(&mut self) -> SWIER2_W`[src]

Bit 2 - Software interrupt on line x

`pub fn swier3(&mut self) -> SWIER3_W`[src]

Bit 3 - Software interrupt on line x

`pub fn swier4(&mut self) -> SWIER4_W`[src]

Bit 4 - Software interrupt on line x

`pub fn swier5(&mut self) -> SWIER5_W`[src]

Bit 5 - Software interrupt on line x

`pub fn swier6(&mut self) -> SWIER6_W`[src]

Bit 6 - Software interrupt on line x

`pub fn swier7(&mut self) -> SWIER7_W`[src]

Bit 7 - Software interrupt on line x

`pub fn swier8(&mut self) -> SWIER8_W`[src]

Bit 8 - Software interrupt on line x

`pub fn swier9(&mut self) -> SWIER9_W`[src]

Bit 9 - Software interrupt on line x

`pub fn swier10(&mut self) -> SWIER10_W`[src]

Bit 10 - Software interrupt on line x

`pub fn swier11(&mut self) -> SWIER11_W`[src]

Bit 11 - Software interrupt on line x

`pub fn swier12(&mut self) -> SWIER12_W`[src]

Bit 12 - Software interrupt on line x

`pub fn swier13(&mut self) -> SWIER13_W`[src]

Bit 13 - Software interrupt on line x

`pub fn swier14(&mut self) -> SWIER14_W`[src]

Bit 14 - Software interrupt on line x

`pub fn swier15(&mut self) -> SWIER15_W`[src]

Bit 15 - Software interrupt on line x

`pub fn swier16(&mut self) -> SWIER16_W`[src]

Bit 16 - Software interrupt on line x

`pub fn swier17(&mut self) -> SWIER17_W`[src]

Bit 17 - Software interrupt on line x

`pub fn swier18(&mut self) -> SWIER18_W`[src]

Bit 18 - Software interrupt on line x

`pub fn swier19(&mut self) -> SWIER19_W`[src]

Bit 19 - Software interrupt on line x

`pub fn swier20(&mut self) -> SWIER20_W`[src]

Bit 20 - Software interrupt on line x

`pub fn swier21(&mut self) -> SWIER21_W`[src]

Bit 21 - Software interrupt on line x

`pub fn swier22(&mut self) -> SWIER22_W`[src]

Bit 22 - Software interrupt on line x

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn pr0(&mut self) -> PR0_W`[src]

Bit 0 - Pending bit

`pub fn pr1(&mut self) -> PR1_W`[src]

Bit 1 - Pending bit

`pub fn pr2(&mut self) -> PR2_W`[src]

Bit 2 - Pending bit

`pub fn pr3(&mut self) -> PR3_W`[src]

Bit 3 - Pending bit

`pub fn pr4(&mut self) -> PR4_W`[src]

Bit 4 - Pending bit

`pub fn pr5(&mut self) -> PR5_W`[src]

Bit 5 - Pending bit

`pub fn pr6(&mut self) -> PR6_W`[src]

Bit 6 - Pending bit

`pub fn pr7(&mut self) -> PR7_W`[src]

Bit 7 - Pending bit

`pub fn pr8(&mut self) -> PR8_W`[src]

Bit 8 - Pending bit

`pub fn pr9(&mut self) -> PR9_W`[src]

Bit 9 - Pending bit

`pub fn pr10(&mut self) -> PR10_W`[src]

Bit 10 - Pending bit

`pub fn pr11(&mut self) -> PR11_W`[src]

Bit 11 - Pending bit

`pub fn pr12(&mut self) -> PR12_W`[src]

Bit 12 - Pending bit

`pub fn pr13(&mut self) -> PR13_W`[src]

Bit 13 - Pending bit

`pub fn pr14(&mut self) -> PR14_W`[src]

Bit 14 - Pending bit

`pub fn pr15(&mut self) -> PR15_W`[src]

Bit 15 - Pending bit

`pub fn pr16(&mut self) -> PR16_W`[src]

Bit 16 - Pending bit

`pub fn pr17(&mut self) -> PR17_W`[src]

Bit 17 - Pending bit

`pub fn pr18(&mut self) -> PR18_W`[src]

Bit 18 - Pending bit

`pub fn pr19(&mut self) -> PR19_W`[src]

Bit 19 - Pending bit

`pub fn pr20(&mut self) -> PR20_W`[src]

Bit 20 - Pending bit

`pub fn pr21(&mut self) -> PR21_W`[src]

Bit 21 - Pending bit

`pub fn pr22(&mut self) -> PR22_W`[src]

Bit 22 - Pending bit

`impl W<u32, Reg<u32, _ACR>>`[src]

`pub fn latency(&mut self) -> LATENCY_W`[src]

Bit 0 - Latency

`pub fn prften(&mut self) -> PRFTEN_W`[src]

Bit 1 - Prefetch enable

`pub fn acc64(&mut self) -> ACC64_W`[src]

Bit 2 - 64-bit access

`pub fn sleep_pd(&mut self) -> SLEEP_PD_W`[src]

Bit 3 - Flash mode during Sleep

`pub fn run_pd(&mut self) -> RUN_PD_W`[src]

Bit 4 - Flash mode during Run

`impl W<u32, Reg<u32, _PECR>>`[src]

`pub fn pelock(&mut self) -> PELOCK_W`[src]

Bit 0 - FLASH_PECR and data EEPROM lock

`pub fn prglock(&mut self) -> PRGLOCK_W`[src]

Bit 1 - Program memory lock

`pub fn optlock(&mut self) -> OPTLOCK_W`[src]

Bit 2 - Option bytes block lock

`pub fn prog(&mut self) -> PROG_W`[src]

Bit 3 - Program memory selection

`pub fn data(&mut self) -> DATA_W`[src]

Bit 4 - Data EEPROM selection

`pub fn ftdw(&mut self) -> FTDW_W`[src]

Bit 8 - Fixed time data write for Byte, Half Word and Word programming

`pub fn erase(&mut self) -> ERASE_W`[src]

Bit 9 - Page or Double Word erase mode

`pub fn fprg(&mut self) -> FPRG_W`[src]

Bit 10 - Half Page/Double Word programming mode

`pub fn parallelbank(&mut self) -> PARALLELBANK_W`[src]

Bit 15 - Parallel bank mode

`pub fn eopie(&mut self) -> EOPIE_W`[src]

Bit 16 - End of programming interrupt enable

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 17 - Error interrupt enable

`pub fn obl_launch(&mut self) -> OBL_LAUNCH_W`[src]

Bit 18 - Launch the option byte loading

`impl W<u32, Reg<u32, _PDKEYR>>`[src]

`pub fn pdkeyr(&mut self) -> PDKEYR_W`[src]

Bits 0:31 - RUN_PD in FLASH_ACR key

`impl W<u32, Reg<u32, _PEKEYR>>`[src]

`pub fn pekeyr(&mut self) -> PEKEYR_W`[src]

Bits 0:31 - FLASH_PEC and data EEPROM key

`impl W<u32, Reg<u32, _PRGKEYR>>`[src]

`pub fn prgkeyr(&mut self) -> PRGKEYR_W`[src]

Bits 0:31 - Program memory key

`impl W<u32, Reg<u32, _OPTKEYR>>`[src]

`pub fn optkeyr(&mut self) -> OPTKEYR_W`[src]

Bits 0:31 - Option byte key

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn wrperr(&mut self) -> WRPERR_W`[src]

Bit 8 - Write protected error

`pub fn pgaerr(&mut self) -> PGAERR_W`[src]

Bit 9 - Programming alignment error

`pub fn sizerr(&mut self) -> SIZERR_W`[src]

Bit 10 - Size error

`pub fn optverr(&mut self) -> OPTVERR_W`[src]

Bit 11 - Option validity error

`pub fn optverrusr(&mut self) -> OPTVERRUSR_W`[src]

Bit 12 - Option UserValidity Error

`impl W<u32, Reg<u32, _WRPR1>>`[src]

`pub fn wrp1(&mut self) -> WRP1_W`[src]

Bits 0:31 - Write protection

`impl W<u32, Reg<u32, _WRPR2>>`[src]

`pub fn wrp2(&mut self) -> WRP2_W`[src]

Bits 0:31 - WRP2

`impl W<u32, Reg<u32, _WRPR3>>`[src]

`pub fn wrp3(&mut self) -> WRP3_W`[src]

Bits 0:31 - WRP3

`impl W<u32, Reg<u32, _BCR1>>`[src]

`pub fn cburstrw(&mut self) -> CBURSTRW_W`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&mut self) -> ASYNCWAIT_W`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&mut self) -> EXTMOD_W`[src]

Bit 14 - EXTMOD

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 13 - WAITEN

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 12 - WREN

`pub fn waitcfg(&mut self) -> WAITCFG_W`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&mut self) -> WRAPMOD_W`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&mut self) -> WAITPOL_W`[src]

Bit 9 - WAITPOL

`pub fn bursten(&mut self) -> BURSTEN_W`[src]

Bit 8 - BURSTEN

`pub fn faccen(&mut self) -> FACCEN_W`[src]

Bit 6 - FACCEN

`pub fn mwid(&mut self) -> MWID_W`[src]

Bits 4:5 - MWID

`pub fn mtyp(&mut self) -> MTYP_W`[src]

Bits 2:3 - MTYP

`pub fn muxen(&mut self) -> MUXEN_W`[src]

Bit 1 - MUXEN

`pub fn mbken(&mut self) -> MBKEN_W`[src]

Bit 0 - MBKEN

`pub fn cpsize(&mut self) -> CPSIZE_W`[src]

Bits 16:18 - CRAM page size

`impl W<u32, Reg<u32, _BTR>>`[src]

`pub fn accmod(&mut self) -> ACCMOD_W`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&mut self) -> DATLAT_W`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 20:23 - CLKDIV

`pub fn busturn(&mut self) -> BUSTURN_W`[src]

Bits 16:19 - BUSTURN

`pub fn datast(&mut self) -> DATAST_W`[src]

Bits 8:15 - DATAST

`pub fn addhld(&mut self) -> ADDHLD_W`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&mut self) -> ADDSET_W`[src]

Bits 0:3 - ADDSET

`impl W<u32, Reg<u32, _BCR>>`[src]

`pub fn cburstrw(&mut self) -> CBURSTRW_W`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&mut self) -> ASYNCWAIT_W`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&mut self) -> EXTMOD_W`[src]

Bit 14 - EXTMOD

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 13 - WAITEN

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 12 - WREN

`pub fn waitcfg(&mut self) -> WAITCFG_W`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&mut self) -> WRAPMOD_W`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&mut self) -> WAITPOL_W`[src]

Bit 9 - WAITPOL

`pub fn bursten(&mut self) -> BURSTEN_W`[src]

Bit 8 - BURSTEN

`pub fn faccen(&mut self) -> FACCEN_W`[src]

Bit 6 - FACCEN

`pub fn mwid(&mut self) -> MWID_W`[src]

Bits 4:5 - MWID

`pub fn mtyp(&mut self) -> MTYP_W`[src]

Bits 2:3 - MTYP

`pub fn muxen(&mut self) -> MUXEN_W`[src]

Bit 1 - MUXEN

`pub fn mbken(&mut self) -> MBKEN_W`[src]

Bit 0 - MBKEN

`pub fn cpsize(&mut self) -> CPSIZE_W`[src]

Bits 16:18 - CRAM page size

`impl W<u32, Reg<u32, _BWTR>>`[src]

`pub fn accmod(&mut self) -> ACCMOD_W`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&mut self) -> DATLAT_W`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 20:23 - CLKDIV

`pub fn datast(&mut self) -> DATAST_W`[src]

Bits 8:15 - DATAST

`pub fn addhld(&mut self) -> ADDHLD_W`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&mut self) -> ADDSET_W`[src]

Bits 0:3 - ADDSET

`pub fn busturn(&mut self) -> BUSTURN_W`[src]

Bits 16:19 - Bus turnaround phase duration

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn swrst(&mut self) -> SWRST_W`[src]

Bit 15 - Software reset

`pub fn alert(&mut self) -> ALERT_W`[src]

Bit 13 - SMBus alert

`pub fn pec(&mut self) -> PEC_W`[src]

Bit 12 - Packet error checking

`pub fn pos(&mut self) -> POS_W`[src]

Bit 11 - Acknowledge/PEC Position (for data reception)

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 10 - Acknowledge enable

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 9 - Stop generation

`pub fn start(&mut self) -> START_W`[src]

Bit 8 - Start generation

`pub fn nostretch(&mut self) -> NOSTRETCH_W`[src]

Bit 7 - Clock stretching disable (Slave mode)

`pub fn engc(&mut self) -> ENGC_W`[src]

Bit 6 - General call enable

`pub fn enpec(&mut self) -> ENPEC_W`[src]

Bit 5 - PEC enable

`pub fn enarp(&mut self) -> ENARP_W`[src]

Bit 4 - ARP enable

`pub fn smbtype(&mut self) -> SMBTYPE_W`[src]

Bit 3 - SMBus type

`pub fn smbus(&mut self) -> SMBUS_W`[src]

Bit 1 - SMBus mode

`pub fn pe(&mut self) -> PE_W`[src]

Bit 0 - Peripheral enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn last(&mut self) -> LAST_W`[src]

Bit 12 - DMA last transfer

`pub fn dmaen(&mut self) -> DMAEN_W`[src]

Bit 11 - DMA requests enable

`pub fn itbufen(&mut self) -> ITBUFEN_W`[src]

Bit 10 - Buffer interrupt enable

`pub fn itevten(&mut self) -> ITEVTEN_W`[src]

Bit 9 - Event interrupt enable

`pub fn iterren(&mut self) -> ITERREN_W`[src]

Bit 8 - Error interrupt enable

`pub fn freq(&mut self) -> FREQ_W`[src]

Bits 0:5 - Peripheral clock frequency

`impl W<u32, Reg<u32, _OAR1>>`[src]

`pub fn addmode(&mut self) -> ADDMODE_W`[src]

Bit 15 - ADDMODE

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:9 - Interface address

`impl W<u32, Reg<u32, _OAR2>>`[src]

`pub fn add2(&mut self) -> ADD2_W`[src]

Bits 1:7 - Interface address

`pub fn endual(&mut self) -> ENDUAL_W`[src]

Bit 0 - Dual addressing mode enable

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:7 - -bit data register

`impl W<u32, Reg<u32, _SR1>>`[src]

`pub fn smbalert(&mut self) -> SMBALERT_W`[src]

Bit 15 - SMBus alert

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 14 - Timeout or Tlow error

`pub fn pecerr(&mut self) -> PECERR_W`[src]

Bit 12 - PEC Error in reception

`pub fn ovr(&mut self) -> OVR_W`[src]

Bit 11 - Overrun/Underrun

`pub fn af(&mut self) -> AF_W`[src]

Bit 10 - Acknowledge failure

`pub fn arlo(&mut self) -> ARLO_W`[src]

Bit 9 - Arbitration lost (master mode)

`pub fn berr(&mut self) -> BERR_W`[src]

Bit 8 - Bus error

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn f_s(&mut self) -> F_S_W`[src]

Bit 15 - I2C master mode selection

`pub fn duty(&mut self) -> DUTY_W`[src]

Bit 14 - Fast mode duty cycle

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

`impl W<u32, Reg<u32, _TRISE>>`[src]

`pub fn trise(&mut self) -> TRISE_W`[src]

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

`impl W<u32, Reg<u32, _KR>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:15 - Key value (write only, read 0000h)

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn pr(&mut self) -> PR_W`[src]

Bits 0:2 - Prescaler divider

`impl W<u32, Reg<u32, _RLR>>`[src]

`pub fn rl(&mut self) -> RL_W`[src]

Bits 0:11 - Watchdog counter reload value

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn mux_seg(&mut self) -> MUX_SEG_W`[src]

Bit 7 - Mux segment enable

`pub fn bias(&mut self) -> BIAS_W`[src]

Bits 5:6 - Bias selector

`pub fn duty(&mut self) -> DUTY_W`[src]

Bits 2:4 - Duty selection

`pub fn vsel(&mut self) -> VSEL_W`[src]

Bit 1 - Voltage source selection

`pub fn lcden(&mut self) -> LCDEN_W`[src]

Bit 0 - LCD controller enable

`impl W<u32, Reg<u32, _FCR>>`[src]

`pub fn ps(&mut self) -> PS_W`[src]

Bits 22:25 - PS 16-bit prescaler

`pub fn div(&mut self) -> DIV_W`[src]

Bits 18:21 - DIV clock divider

`pub fn blink(&mut self) -> BLINK_W`[src]

Bits 16:17 - Blink mode selection

`pub fn blinkf(&mut self) -> BLINKF_W`[src]

Bits 13:15 - Blink frequency selection

`pub fn cc(&mut self) -> CC_W`[src]

Bits 10:12 - Contrast control

`pub fn dead(&mut self) -> DEAD_W`[src]

Bits 7:9 - Dead time duration

`pub fn pon(&mut self) -> PON_W`[src]

Bits 4:6 - Pulse ON duration

`pub fn uddie(&mut self) -> UDDIE_W`[src]

Bit 3 - Update display done interrupt enable

`pub fn sofie(&mut self) -> SOFIE_W`[src]

Bit 1 - Start of frame interrupt enable

`pub fn hd(&mut self) -> HD_W`[src]

Bit 0 - High drive enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn udr(&mut self) -> UDR_W`[src]

Bit 2 - Update display request

`impl W<u32, Reg<u32, _CLR>>`[src]

`pub fn uddc(&mut self) -> UDDC_W`[src]

Bit 3 - Update display done clear

`pub fn sofc(&mut self) -> SOFC_W`[src]

Bit 1 - Start of frame flag clear

`impl W<u32, Reg<u32, _RAM_COM0>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM1>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM2>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM3>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM4>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM5>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM6>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM7>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn opa3calout(&mut self) -> OPA3CALOUT_W`[src]

Bit 31 - OPAMP3 calibration output

`pub fn opa2calout(&mut self) -> OPA2CALOUT_W`[src]

Bit 30 - OPAMP2 calibration output

`pub fn opa1calout(&mut self) -> OPA1CALOUT_W`[src]

Bit 29 - OPAMP1 calibration output

`pub fn aop_range(&mut self) -> AOP_RANGE_W`[src]

Bit 28 - Power range selection

`pub fn s7sel2(&mut self) -> S7SEL2_W`[src]

Bit 27 - Switch 7 for OPAMP2 enable

`pub fn anawsel3(&mut self) -> ANAWSEL3_W`[src]

Bit 26 - Switch SanA enable for OPAMP3

`pub fn anawsel2(&mut self) -> ANAWSEL2_W`[src]

Bit 25 - Switch SanA enable for OPAMP2

`pub fn anawsel1(&mut self) -> ANAWSEL1_W`[src]

Bit 24 - Switch SanA enable for OPAMP1

`pub fn opa3lpm(&mut self) -> OPA3LPM_W`[src]

Bit 23 - OPAMP3 low power mode

`pub fn opa3cal_h(&mut self) -> OPA3CAL_H_W`[src]

Bit 22 - OPAMP3 offset calibration for N differential pair

`pub fn opa3cal_l(&mut self) -> OPA3CAL_L_W`[src]

Bit 21 - OPAMP3 offset Calibration for P differential pair

`pub fn s6sel3(&mut self) -> S6SEL3_W`[src]

Bit 20 - Switch 6 for OPAMP3 enable

`pub fn s5sel3(&mut self) -> S5SEL3_W`[src]

Bit 19 - Switch 5 for OPAMP3 enable

`pub fn s4sel3(&mut self) -> S4SEL3_W`[src]

Bit 18 - Switch 4 for OPAMP3 enable

`pub fn s3sel3(&mut self) -> S3SEL3_W`[src]

Bit 17 - Switch 3 for OPAMP3 Enable

`pub fn opa3pd(&mut self) -> OPA3PD_W`[src]

Bit 16 - OPAMP3 power down

`pub fn opa2lpm(&mut self) -> OPA2LPM_W`[src]

Bit 15 - OPAMP2 low power mode

`pub fn opa2cal_h(&mut self) -> OPA2CAL_H_W`[src]

Bit 14 - OPAMP2 offset calibration for N differential pair

`pub fn opa2cal_l(&mut self) -> OPA2CAL_L_W`[src]

Bit 13 - OPAMP2 offset Calibration for P differential pair

`pub fn s6sel2(&mut self) -> S6SEL2_W`[src]

Bit 12 - Switch 6 for OPAMP2 enable

`pub fn s5sel2(&mut self) -> S5SEL2_W`[src]

Bit 11 - Switch 5 for OPAMP2 enable

`pub fn s4sel2(&mut self) -> S4SEL2_W`[src]

Bit 10 - Switch 4 for OPAMP2 enable

`pub fn s3sel2(&mut self) -> S3SEL2_W`[src]

Bit 9 - Switch 3 for OPAMP2 enable

`pub fn opa2pd(&mut self) -> OPA2PD_W`[src]

Bit 8 - OPAMP2 power down

`pub fn opa1lpm(&mut self) -> OPA1LPM_W`[src]

Bit 7 - OPAMP1 low power mode

`pub fn opa1cal_h(&mut self) -> OPA1CAL_H_W`[src]

Bit 6 - OPAMP1 offset calibration for N differential pair

`pub fn opa1cal_l(&mut self) -> OPA1CAL_L_W`[src]

Bit 5 - OPAMP1 offset calibration for P differential pair

`pub fn s6sel1(&mut self) -> S6SEL1_W`[src]

Bit 4 - Switch 6 for OPAMP1 enable

`pub fn s5sel1(&mut self) -> S5SEL1_W`[src]

Bit 3 - Switch 5 for OPAMP1 enable

`pub fn s4sel1(&mut self) -> S4SEL1_W`[src]

Bit 2 - Switch 4 for OPAMP1 enable

`pub fn s3sel1(&mut self) -> S3SEL1_W`[src]

Bit 1 - Switch 3 for OPAMP1 enable

`pub fn opa1pd(&mut self) -> OPA1PD_W`[src]

Bit 0 - OPAMP1 power down

`impl W<u32, Reg<u32, _OTR>>`[src]

`pub fn ot_user(&mut self) -> OT_USER_W`[src]

Bit 31 - Select user or factory trimming value

`pub fn ao3_opt_offset_trim(&mut self) -> AO3_OPT_OFFSET_TRIM_W`[src]

Bits 20:29 - OPAMP3, 10-bit offset trim value for normal mode

`pub fn ao2_opt_offset_trim(&mut self) -> AO2_OPT_OFFSET_TRIM_W`[src]

Bits 10:19 - OPAMP2, 10-bit offset trim value for normal mode

`pub fn ao1_opt_offset_trim(&mut self) -> AO1_OPT_OFFSET_TRIM_W`[src]

Bits 0:9 - OPAMP1, 10-bit offset trim value for normal mode

`impl W<u32, Reg<u32, _LPOTR>>`[src]

`pub fn ao3_opt_offset_trim_lp(&mut self) -> AO3_OPT_OFFSET_TRIM_LP_W`[src]

Bits 20:29 - OPAMP3, 10-bit offset trim value for low power mode

`pub fn ao2_opt_offset_trim_lp(&mut self) -> AO2_OPT_OFFSET_TRIM_LP_W`[src]

Bits 10:19 - OPAMP2, 10-bit offset trim value for low power mode

`pub fn ao1_opt_offset_trim_lp(&mut self) -> AO1_OPT_OFFSET_TRIM_LP_W`[src]

Bits 0:9 - OPAMP1, 10-bit offset trim value for low power mode

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn lprun(&mut self) -> LPRUN_W`[src]

Bit 14 - Low power run mode

`pub fn vos(&mut self) -> VOS_W`[src]

Bits 11:12 - Voltage scaling range selection

`pub fn fwu(&mut self) -> FWU_W`[src]

Bit 10 - Fast wakeup

`pub fn ulp(&mut self) -> ULP_W`[src]

Bit 9 - Ultralow power mode

`pub fn dbp(&mut self) -> DBP_W`[src]

Bit 8 - Disable backup domain write protection

`pub fn pls(&mut self) -> PLS_W`[src]

Bits 5:7 - PVD level selection

`pub fn pvde(&mut self) -> PVDE_W`[src]

Bit 4 - Power voltage detector enable

`pub fn csbf(&mut self) -> CSBF_W`[src]

Bit 3 - Clear standby flag

`pub fn cwuf(&mut self) -> CWUF_W`[src]

Bit 2 - Clear wakeup flag

`pub fn pdds(&mut self) -> PDDS_W`[src]

Bit 1 - Power down deepsleep

`pub fn lpsdsr(&mut self) -> LPSDSR_W`[src]

Bit 0 - Low-power deep sleep

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn ewup3(&mut self) -> EWUP3_W`[src]

Bit 10 - Enable WKUP pin 3

`pub fn ewup2(&mut self) -> EWUP2_W`[src]

Bit 9 - Enable WKUP pin 2

`pub fn ewup1(&mut self) -> EWUP1_W`[src]

Bit 8 - Enable WKUP pin 1

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn rtcpre1(&mut self) -> RTCPRE1_W`[src]

Bit 30 - TC/LCD prescaler

`pub fn rtcpre0(&mut self) -> RTCPRE0_W`[src]

Bit 29 - RTCPRE0

`pub fn csson(&mut self) -> CSSON_W`[src]

Bit 28 - Clock security system enable

`pub fn pllon(&mut self) -> PLLON_W`[src]

Bit 24 - PLL enable

`pub fn hsebyp(&mut self) -> HSEBYP_W`[src]

Bit 18 - HSE clock bypass

`pub fn hseon(&mut self) -> HSEON_W`[src]

Bit 16 - HSE clock enable

`pub fn msion(&mut self) -> MSION_W`[src]

Bit 8 - MSI clock enable

`pub fn hsion(&mut self) -> HSION_W`[src]

Bit 0 - Internal high-speed clock enable

`impl W<u32, Reg<u32, _ICSCR>>`[src]

`pub fn msitrim(&mut self) -> MSITRIM_W`[src]

Bits 24:31 - MSI clock trimming

`pub fn msirange(&mut self) -> MSIRANGE_W`[src]

Bits 13:15 - MSI clock ranges

`pub fn hsitrim(&mut self) -> HSITRIM_W`[src]

Bits 8:12 - High speed internal clock trimming

`impl W<u32, Reg<u32, _CFGR>>`[src]

`pub fn mcopre(&mut self) -> MCOPRE_W`[src]

Bits 28:30 - Microcontroller clock output prescaler

`pub fn mcosel(&mut self) -> MCOSEL_W`[src]

Bits 24:26 - Microcontroller clock output selection

`pub fn plldiv(&mut self) -> PLLDIV_W`[src]

Bits 22:23 - PLL output division

`pub fn pllmul(&mut self) -> PLLMUL_W`[src]

Bits 18:21 - PLL multiplication factor

`pub fn pllsrc(&mut self) -> PLLSRC_W`[src]

Bit 16 - PLL entry clock source

`pub fn ppre2(&mut self) -> PPRE2_W`[src]

Bits 11:13 - APB high-speed prescaler (APB2)

`pub fn ppre1(&mut self) -> PPRE1_W`[src]

Bits 8:10 - APB low-speed prescaler (APB1)

`pub fn hpre(&mut self) -> HPRE_W`[src]

Bits 4:7 - AHB prescaler

`pub fn sw(&mut self) -> SW_W`[src]

Bits 0:1 - System clock switch

`impl W<u32, Reg<u32, _CIR>>`[src]

`pub fn cssc(&mut self) -> CSSC_W`[src]

Bit 23 - Clock security system interrupt clear

`pub fn msirdyc(&mut self) -> MSIRDYC_W`[src]

Bit 21 - MSI ready interrupt clear

`pub fn pllrdyc(&mut self) -> PLLRDYC_W`[src]

Bit 20 - PLL ready interrupt clear

`pub fn hserdyc(&mut self) -> HSERDYC_W`[src]

Bit 19 - HSE ready interrupt clear

`pub fn hsirdyc(&mut self) -> HSIRDYC_W`[src]

Bit 18 - HSI ready interrupt clear

`pub fn lserdyc(&mut self) -> LSERDYC_W`[src]

Bit 17 - LSE ready interrupt clear

`pub fn lsirdyc(&mut self) -> LSIRDYC_W`[src]

Bit 16 - LSI ready interrupt clear

`pub fn msirdyie(&mut self) -> MSIRDYIE_W`[src]

Bit 13 - MSI ready interrupt enable

`pub fn pllrdyie(&mut self) -> PLLRDYIE_W`[src]

Bit 12 - PLL ready interrupt enable

`pub fn hserdyie(&mut self) -> HSERDYIE_W`[src]

Bit 11 - HSE ready interrupt enable

`pub fn hsirdyie(&mut self) -> HSIRDYIE_W`[src]

Bit 10 - HSI ready interrupt enable

`pub fn lserdyie(&mut self) -> LSERDYIE_W`[src]

Bit 9 - LSE ready interrupt enable

`pub fn lsirdyie(&mut self) -> LSIRDYIE_W`[src]

Bit 8 - LSI ready interrupt enable

`impl W<u32, Reg<u32, _AHBRSTR>>`[src]

`pub fn fsmcrst(&mut self) -> FSMCRST_W`[src]

Bit 30 - FSMC reset

`pub fn dma2rst(&mut self) -> DMA2RST_W`[src]

Bit 25 - DMA2 reset

`pub fn dma1rst(&mut self) -> DMA1RST_W`[src]

Bit 24 - DMA1 reset

`pub fn flitfrst(&mut self) -> FLITFRST_W`[src]

Bit 15 - FLITF reset

`pub fn crcrst(&mut self) -> CRCRST_W`[src]

Bit 12 - CRC reset

`pub fn gpiogrst(&mut self) -> GPIOGRST_W`[src]

Bit 7 - IO port G reset

`pub fn gpiofrst(&mut self) -> GPIOFRST_W`[src]

Bit 6 - IO port F reset

`pub fn gpiohrst(&mut self) -> GPIOHRST_W`[src]

Bit 5 - IO port H reset

`pub fn gpioerst(&mut self) -> GPIOERST_W`[src]

Bit 4 - IO port E reset

`pub fn gpiodrst(&mut self) -> GPIODRST_W`[src]

Bit 3 - IO port D reset

`pub fn gpiocrst(&mut self) -> GPIOCRST_W`[src]

Bit 2 - IO port C reset

`pub fn gpiobrst(&mut self) -> GPIOBRST_W`[src]

Bit 1 - IO port B reset

`pub fn gpioarst(&mut self) -> GPIOARST_W`[src]

Bit 0 - IO port A reset

`impl W<u32, Reg<u32, _APB2RSTR>>`[src]

`pub fn usart1rst(&mut self) -> USART1RST_W`[src]

Bit 14 - USART1RST

`pub fn spi1rst(&mut self) -> SPI1RST_W`[src]

Bit 12 - SPI1RST

`pub fn sdiorst(&mut self) -> SDIORST_W`[src]

Bit 11 - SDIORST

`pub fn adc1rst(&mut self) -> ADC1RST_W`[src]

Bit 9 - ADC1RST

`pub fn tm11rst(&mut self) -> TM11RST_W`[src]

Bit 4 - TM11RST

`pub fn tm10rst(&mut self) -> TM10RST_W`[src]

Bit 3 - TM10RST

`pub fn tim9rst(&mut self) -> TIM9RST_W`[src]

Bit 2 - TIM9RST

`pub fn syscfgrst(&mut self) -> SYSCFGRST_W`[src]

Bit 0 - SYSCFGRST

`impl W<u32, Reg<u32, _APB1RSTR>>`[src]

`pub fn comprst(&mut self) -> COMPRST_W`[src]

Bit 31 - COMP interface reset

`pub fn dacrst(&mut self) -> DACRST_W`[src]

Bit 29 - DAC interface reset

`pub fn pwrrst(&mut self) -> PWRRST_W`[src]

Bit 28 - Power interface reset

`pub fn usbrst(&mut self) -> USBRST_W`[src]

Bit 23 - USB reset

`pub fn i2c2rst(&mut self) -> I2C2RST_W`[src]

Bit 22 - I2C 2 reset

`pub fn i2c1rst(&mut self) -> I2C1RST_W`[src]

Bit 21 - I2C 1 reset

`pub fn uart5rst(&mut self) -> UART5RST_W`[src]

Bit 20 - UART 5 reset

`pub fn uart4rst(&mut self) -> UART4RST_W`[src]

Bit 19 - UART 4 reset

`pub fn usart3rst(&mut self) -> USART3RST_W`[src]

Bit 18 - USART 3 reset

`pub fn usart2rst(&mut self) -> USART2RST_W`[src]

Bit 17 - USART 2 reset

`pub fn spi3rst(&mut self) -> SPI3RST_W`[src]

Bit 15 - SPI 3 reset

`pub fn spi2rst(&mut self) -> SPI2RST_W`[src]

Bit 14 - SPI 2 reset

`pub fn wwdrst(&mut self) -> WWDRST_W`[src]

Bit 11 - Window watchdog reset

`pub fn lcdrst(&mut self) -> LCDRST_W`[src]

Bit 9 - LCD reset

`pub fn tim7rst(&mut self) -> TIM7RST_W`[src]

Bit 5 - Timer 7 reset

`pub fn tim6rst(&mut self) -> TIM6RST_W`[src]

Bit 4 - Timer 6reset

`pub fn tim5rst(&mut self) -> TIM5RST_W`[src]

Bit 3 - Timer 5 reset

`pub fn tim4rst(&mut self) -> TIM4RST_W`[src]

Bit 2 - Timer 4 reset

`pub fn tim3rst(&mut self) -> TIM3RST_W`[src]

Bit 1 - Timer 3 reset

`pub fn tim2rst(&mut self) -> TIM2RST_W`[src]

Bit 0 - Timer 2 reset

`impl W<u32, Reg<u32, _AHBENR>>`[src]

`pub fn fsmcen(&mut self) -> FSMCEN_W`[src]

Bit 30 - FSMCEN

`pub fn dma2en(&mut self) -> DMA2EN_W`[src]

Bit 25 - DMA2 clock enable

`pub fn dma1en(&mut self) -> DMA1EN_W`[src]

Bit 24 - DMA1 clock enable

`pub fn flitfen(&mut self) -> FLITFEN_W`[src]

Bit 15 - FLITF clock enable

`pub fn crcen(&mut self) -> CRCEN_W`[src]

Bit 12 - CRC clock enable

`pub fn gpiopgen(&mut self) -> GPIOPGEN_W`[src]

Bit 7 - IO port G clock enable

`pub fn gpiopfen(&mut self) -> GPIOPFEN_W`[src]

Bit 6 - IO port F clock enable

`pub fn gpiophen(&mut self) -> GPIOPHEN_W`[src]

Bit 5 - IO port H clock enable

`pub fn gpiopeen(&mut self) -> GPIOPEEN_W`[src]

Bit 4 - IO port E clock enable

`pub fn gpiopden(&mut self) -> GPIOPDEN_W`[src]

Bit 3 - IO port D clock enable

`pub fn gpiopcen(&mut self) -> GPIOPCEN_W`[src]

Bit 2 - IO port C clock enable

`pub fn gpiopben(&mut self) -> GPIOPBEN_W`[src]

Bit 1 - IO port B clock enable

`pub fn gpiopaen(&mut self) -> GPIOPAEN_W`[src]

Bit 0 - IO port A clock enable

`impl W<u32, Reg<u32, _APB2ENR>>`[src]

`pub fn usart1en(&mut self) -> USART1EN_W`[src]

Bit 14 - USART1 clock enable

`pub fn spi1en(&mut self) -> SPI1EN_W`[src]

Bit 12 - SPI 1 clock enable

`pub fn sdioen(&mut self) -> SDIOEN_W`[src]

Bit 11 - SDIO clock enable

`pub fn adc1en(&mut self) -> ADC1EN_W`[src]

Bit 9 - ADC1 interface clock enable

`pub fn tim11en(&mut self) -> TIM11EN_W`[src]

Bit 4 - TIM11 timer clock enable

`pub fn tim10en(&mut self) -> TIM10EN_W`[src]

Bit 3 - TIM10 timer clock enable

`pub fn tim9en(&mut self) -> TIM9EN_W`[src]

Bit 2 - TIM9 timer clock enable

`pub fn syscfgen(&mut self) -> SYSCFGEN_W`[src]

Bit 0 - System configuration controller clock enable

`impl W<u32, Reg<u32, _APB1ENR>>`[src]

`pub fn compen(&mut self) -> COMPEN_W`[src]

Bit 31 - COMP interface clock enable

`pub fn dacen(&mut self) -> DACEN_W`[src]

Bit 29 - DAC interface clock enable

`pub fn pwren(&mut self) -> PWREN_W`[src]

Bit 28 - Power interface clock enable

`pub fn usben(&mut self) -> USBEN_W`[src]

Bit 23 - USB clock enable

`pub fn i2c2en(&mut self) -> I2C2EN_W`[src]

Bit 22 - I2C 2 clock enable

`pub fn i2c1en(&mut self) -> I2C1EN_W`[src]

Bit 21 - I2C 1 clock enable

`pub fn usart5en(&mut self) -> USART5EN_W`[src]

Bit 20 - UART 5 clock enable

`pub fn usart4en(&mut self) -> USART4EN_W`[src]

Bit 19 - UART 4 clock enable

`pub fn usart3en(&mut self) -> USART3EN_W`[src]

Bit 18 - USART 3 clock enable

`pub fn usart2en(&mut self) -> USART2EN_W`[src]

Bit 17 - USART 2 clock enable

`pub fn spi3en(&mut self) -> SPI3EN_W`[src]

Bit 15 - SPI 3 clock enable

`pub fn spi2en(&mut self) -> SPI2EN_W`[src]

Bit 14 - SPI 2 clock enable

`pub fn wwdgen(&mut self) -> WWDGEN_W`[src]

Bit 11 - Window watchdog clock enable

`pub fn lcden(&mut self) -> LCDEN_W`[src]

Bit 9 - LCD clock enable

`pub fn tim7en(&mut self) -> TIM7EN_W`[src]

Bit 5 - Timer 7 clock enable

`pub fn tim6en(&mut self) -> TIM6EN_W`[src]

Bit 4 - Timer 6 clock enable

`pub fn tim5en(&mut self) -> TIM5EN_W`[src]

Bit 3 - Timer 5 clock enable

`pub fn tim4en(&mut self) -> TIM4EN_W`[src]

Bit 2 - Timer 4 clock enable

`pub fn tim3en(&mut self) -> TIM3EN_W`[src]

Bit 1 - Timer 3 clock enable

`pub fn tim2en(&mut self) -> TIM2EN_W`[src]

Bit 0 - Timer 2 clock enable

`impl W<u32, Reg<u32, _AHBLPENR>>`[src]

`pub fn dma2lpen(&mut self) -> DMA2LPEN_W`[src]

Bit 25 - DMA2 clock enable during Sleep mode

`pub fn dma1lpen(&mut self) -> DMA1LPEN_W`[src]

Bit 24 - DMA1 clock enable during Sleep mode

`pub fn sramlpen(&mut self) -> SRAMLPEN_W`[src]

Bit 16 - SRAM clock enable during Sleep mode

`pub fn flitflpen(&mut self) -> FLITFLPEN_W`[src]

Bit 15 - FLITF clock enable during Sleep mode

`pub fn crclpen(&mut self) -> CRCLPEN_W`[src]

Bit 12 - CRC clock enable during Sleep mode

`pub fn gpioglpen(&mut self) -> GPIOGLPEN_W`[src]

Bit 7 - IO port G clock enable during Sleep mode

`pub fn gpioflpen(&mut self) -> GPIOFLPEN_W`[src]

Bit 6 - IO port F clock enable during Sleep mode

`pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W`[src]

Bit 5 - IO port H clock enable during Sleep mode

`pub fn gpioelpen(&mut self) -> GPIOELPEN_W`[src]

Bit 4 - IO port E clock enable during Sleep mode

`pub fn gpiodlpen(&mut self) -> GPIODLPEN_W`[src]

Bit 3 - IO port D clock enable during Sleep mode

`pub fn gpioclpen(&mut self) -> GPIOCLPEN_W`[src]

Bit 2 - IO port C clock enable during Sleep mode

`pub fn gpioblpen(&mut self) -> GPIOBLPEN_W`[src]

Bit 1 - IO port B clock enable during Sleep mode

`pub fn gpioalpen(&mut self) -> GPIOALPEN_W`[src]

Bit 0 - IO port A clock enable during Sleep mode

`impl W<u32, Reg<u32, _APB2LPENR>>`[src]

`pub fn usart1lpen(&mut self) -> USART1LPEN_W`[src]

Bit 14 - USART1 clock enable during Sleep mode

`pub fn spi1lpen(&mut self) -> SPI1LPEN_W`[src]

Bit 12 - SPI 1 clock enable during Sleep mode

`pub fn sdiolpen(&mut self) -> SDIOLPEN_W`[src]

Bit 11 - SDIO clock enable during Sleep mode

`pub fn adc1lpen(&mut self) -> ADC1LPEN_W`[src]

Bit 9 - ADC1 interface clock enable during Sleep mode

`pub fn tim11lpen(&mut self) -> TIM11LPEN_W`[src]

Bit 4 - TIM11 timer clock enable during Sleep mode

`pub fn tim10lpen(&mut self) -> TIM10LPEN_W`[src]

Bit 3 - TIM10 timer clock enable during Sleep mode

`pub fn tim9lpen(&mut self) -> TIM9LPEN_W`[src]

Bit 2 - TIM9 timer clock enable during Sleep mode

`pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W`[src]

Bit 0 - System configuration controller clock enable during Sleep mode

`impl W<u32, Reg<u32, _APB1LPENR>>`[src]

`pub fn complpen(&mut self) -> COMPLPEN_W`[src]

Bit 31 - COMP interface clock enable during Sleep mode

`pub fn daclpen(&mut self) -> DACLPEN_W`[src]

Bit 29 - DAC interface clock enable during Sleep mode

`pub fn pwrlpen(&mut self) -> PWRLPEN_W`[src]

Bit 28 - Power interface clock enable during Sleep mode

`pub fn usblpen(&mut self) -> USBLPEN_W`[src]

Bit 23 - USB clock enable during Sleep mode

`pub fn i2c2lpen(&mut self) -> I2C2LPEN_W`[src]

Bit 22 - I2C 2 clock enable during Sleep mode

`pub fn i2c1lpen(&mut self) -> I2C1LPEN_W`[src]

Bit 21 - I2C 1 clock enable during Sleep mode

`pub fn usart3lpen(&mut self) -> USART3LPEN_W`[src]

Bit 18 - USART 3 clock enable during Sleep mode

`pub fn usart2lpen(&mut self) -> USART2LPEN_W`[src]

Bit 17 - USART 2 clock enable during Sleep mode

`pub fn spi2lpen(&mut self) -> SPI2LPEN_W`[src]

Bit 14 - SPI 2 clock enable during Sleep mode

`pub fn wwdglpen(&mut self) -> WWDGLPEN_W`[src]

Bit 11 - Window watchdog clock enable during Sleep mode

`pub fn lcdlpen(&mut self) -> LCDLPEN_W`[src]

Bit 9 - LCD clock enable during Sleep mode

`pub fn tim7lpen(&mut self) -> TIM7LPEN_W`[src]

Bit 5 - Timer 7 clock enable during Sleep mode

`pub fn tim6lpen(&mut self) -> TIM6LPEN_W`[src]

Bit 4 - Timer 6 clock enable during Sleep mode

`pub fn tim4lpen(&mut self) -> TIM4LPEN_W`[src]

Bit 2 - Timer 4 clock enable during Sleep mode

`pub fn tim3lpen(&mut self) -> TIM3LPEN_W`[src]

Bit 1 - Timer 3 clock enable during Sleep mode

`pub fn tim2lpen(&mut self) -> TIM2LPEN_W`[src]

Bit 0 - Timer 2 clock enable during Sleep mode

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn lpwrstf(&mut self) -> LPWRSTF_W`[src]

Bit 31 - Low-power reset flag

`pub fn wwdgrstf(&mut self) -> WWDGRSTF_W`[src]

Bit 30 - Window watchdog reset flag

`pub fn iwdgrstf(&mut self) -> IWDGRSTF_W`[src]

Bit 29 - Independent watchdog reset flag

`pub fn sftrstf(&mut self) -> SFTRSTF_W`[src]

Bit 28 - Software reset flag

`pub fn porrstf(&mut self) -> PORRSTF_W`[src]

Bit 27 - POR/PDR reset flag

`pub fn pinrstf(&mut self) -> PINRSTF_W`[src]

Bit 26 - PIN reset flag

`pub fn rmvf(&mut self) -> RMVF_W`[src]

Bit 24 - Remove reset flag

`pub fn rtcrst(&mut self) -> RTCRST_W`[src]

Bit 23 - RTC software reset

`pub fn rtcen(&mut self) -> RTCEN_W`[src]

Bit 22 - RTC clock enable

`pub fn rtcsel(&mut self) -> RTCSEL_W`[src]

Bits 16:17 - RTC and LCD clock source selection

`pub fn lsebyp(&mut self) -> LSEBYP_W`[src]

Bit 10 - External low-speed oscillator bypass

`pub fn lseon(&mut self) -> LSEON_W`[src]

Bit 8 - External low-speed oscillator enable

`pub fn lsion(&mut self) -> LSION_W`[src]

Bit 0 - Internal low-speed oscillator enable

`impl W<u32, Reg<u32, _ICR>>`[src]

`pub fn ic4(&mut self) -> IC4_W`[src]

Bit 21 - IC4

`pub fn ic3(&mut self) -> IC3_W`[src]

Bit 20 - IC3

`pub fn ic2(&mut self) -> IC2_W`[src]

Bit 19 - IC2

`pub fn ic1(&mut self) -> IC1_W`[src]

Bit 18 - IC1

`pub fn tim(&mut self) -> TIM_W`[src]

Bits 16:17 - Timer select bits

`pub fn ic4ios(&mut self) -> IC4IOS_W`[src]

Bits 12:15 - Input capture 4 select bits

`pub fn ic3ios(&mut self) -> IC3IOS_W`[src]

Bits 8:11 - Input capture 3 select bits

`pub fn ic2ios(&mut self) -> IC2IOS_W`[src]

Bits 4:7 - Input capture 2 select bits

`pub fn ic1ios(&mut self) -> IC1IOS_W`[src]

Bits 0:3 - Input capture 1 select bits

`impl W<u32, Reg<u32, _ASCR1>>`[src]

`pub fn scm(&mut self) -> SCM_W`[src]

Bit 31 - Switch control mode

`pub fn ch30gr11_4(&mut self) -> CH30GR11_4_W`[src]

Bit 30 - Analog switch control

`pub fn ch29gr11_3(&mut self) -> CH29GR11_3_W`[src]

Bit 29 - Analog switch control

`pub fn ch28gr11_2(&mut self) -> CH28GR11_2_W`[src]

Bit 28 - Analog switch control

`pub fn ch27gr11_1(&mut self) -> CH27GR11_1_W`[src]

Bit 27 - Analog switch control

`pub fn vcomp(&mut self) -> VCOMP_W`[src]

Bit 26 - ADC analog switch selection for internal node to comparator 1

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Analog I/O switch control of channel CH25

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Analog I/O switch control of channel CH24

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Analog I/O switch control of channel CH23

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Analog I/O switch control of channel CH22

`pub fn ch21gr7_4(&mut self) -> CH21GR7_4_W`[src]

Bit 21 - Analog switch control

`pub fn ch20gr7_3(&mut self) -> CH20GR7_3_W`[src]

Bit 20 - Analog switch control

`pub fn ch19gr7_2(&mut self) -> CH19GR7_2_W`[src]

Bit 19 - Analog switch control

`pub fn ch18gr7_1(&mut self) -> CH18GR7_1_W`[src]

Bit 18 - Analog switch control

`pub fn ch31gr7_1(&mut self) -> CH31GR7_1_W`[src]

Bit 16 - Analog switch control

`pub fn ch15gr9_2(&mut self) -> CH15GR9_2_W`[src]

Bit 15 - Analog switch control

`pub fn ch14gr9_1(&mut self) -> CH14GR9_1_W`[src]

Bit 14 - Analog switch control

`pub fn ch13gr8_4(&mut self) -> CH13GR8_4_W`[src]

Bit 13 - Analog switch control

`pub fn ch12gr8_3(&mut self) -> CH12GR8_3_W`[src]

Bit 12 - Analog switch control

`pub fn ch11gr8_2(&mut self) -> CH11GR8_2_W`[src]

Bit 11 - Analog switch control

`pub fn ch10gr8_1(&mut self) -> CH10GR8_1_W`[src]

Bit 10 - Analog switch control

`pub fn ch9gr3_2(&mut self) -> CH9GR3_2_W`[src]

Bit 9 - Analog switch control

`pub fn ch8gr3_1(&mut self) -> CH8GR3_1_W`[src]

Bit 8 - Analog switch control

`pub fn ch7gr2_2(&mut self) -> CH7GR2_2_W`[src]

Bit 7 - Analog switch control

`pub fn ch6gr2_1(&mut self) -> CH6GR2_1_W`[src]

Bit 6 - Analog switch control

`pub fn comp1_sw1(&mut self) -> COMP1_SW1_W`[src]

Bit 5 - Comparator 1 analog switch

`pub fn ch31gr11_5(&mut self) -> CH31GR11_5_W`[src]

Bit 4 - Analog switch control

`pub fn ch3gr1_4(&mut self) -> CH3GR1_4_W`[src]

Bit 3 - Analog switch control

`pub fn ch2gr1_3(&mut self) -> CH2GR1_3_W`[src]

Bit 2 - Analog switch control

`pub fn ch1gr1_2(&mut self) -> CH1GR1_2_W`[src]

Bit 1 - Analog switch control

`pub fn ch0gr1_1(&mut self) -> CH0GR1_1_W`[src]

Bit 0 - Analog switch control

`impl W<u32, Reg<u32, _ASCR2>>`[src]

`pub fn gr5_4(&mut self) -> GR5_4_W`[src]

Bit 29 - GR5_4 analog switch control

`pub fn gr6_4(&mut self) -> GR6_4_W`[src]

Bit 28 - GR6_4 analog switch control

`pub fn gr6_3(&mut self) -> GR6_3_W`[src]

Bit 27 - GR6_3 analog switch control

`pub fn gr7_7(&mut self) -> GR7_7_W`[src]

Bit 26 - GR7_7 analog switch control

`pub fn gr7_6(&mut self) -> GR7_6_W`[src]

Bit 25 - GR7_6 analog switch control

`pub fn gr7_5(&mut self) -> GR7_5_W`[src]

Bit 24 - GR7_5 analog switch control

`pub fn gr2_5(&mut self) -> GR2_5_W`[src]

Bit 23 - GR2_5 analog switch control

`pub fn gr2_4(&mut self) -> GR2_4_W`[src]

Bit 22 - GR2_4 analog switch control

`pub fn gr2_3(&mut self) -> GR2_3_W`[src]

Bit 21 - GR2_3 analog switch control

`pub fn gr9_4(&mut self) -> GR9_4_W`[src]

Bit 20 - GR9_4 analog switch control

`pub fn gr9_3(&mut self) -> GR9_3_W`[src]

Bit 19 - GR9_3 analog switch control

`pub fn gr3_5(&mut self) -> GR3_5_W`[src]

Bit 18 - GR3_5 analog switch control

`pub fn gr3_4(&mut self) -> GR3_4_W`[src]

Bit 17 - GR3_4 analog switch control

`pub fn gr3_3(&mut self) -> GR3_3_W`[src]

Bit 16 - GR3_3 analog switch control

`pub fn gr4_3(&mut self) -> GR4_3_W`[src]

Bit 11 - GR4_3 analog switch control

`pub fn gr4_2(&mut self) -> GR4_2_W`[src]

Bit 10 - GR4_2 analog switch control

`pub fn gr4_1(&mut self) -> GR4_1_W`[src]

Bit 9 - GR4_1 analog switch control

`pub fn gr5_3(&mut self) -> GR5_3_W`[src]

Bit 8 - GR5_3 analog switch control

`pub fn gr5_2(&mut self) -> GR5_2_W`[src]

Bit 7 - GR5_2 analog switch control

`pub fn gr5_1(&mut self) -> GR5_1_W`[src]

Bit 6 - GR5_1 analog switch control

`pub fn gr6_2(&mut self) -> GR6_2_W`[src]

Bit 5 - GR6_2 analog switch control

`pub fn gr6_1(&mut self) -> GR6_1_W`[src]

Bit 4 - GR6_1 analog switch control

`pub fn gr10_4(&mut self) -> GR10_4_W`[src]

Bit 3 - GR10_4 analog switch control

`pub fn gr10_3(&mut self) -> GR10_3_W`[src]

Bit 2 - GR10_3 analog switch control

`pub fn gr10_2(&mut self) -> GR10_2_W`[src]

Bit 1 - GR10_2 analog switch control

`pub fn gr10_1(&mut self) -> GR10_1_W`[src]

Bit 0 - GR10_1 analog switch control

`impl W<u32, Reg<u32, _HYSCR1>>`[src]

`pub fn pb(&mut self) -> PB_W`[src]

Bits 16:31 - Port B hysteresis control on/off

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:15 - Port A hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR2>>`[src]

`pub fn pd(&mut self) -> PD_W`[src]

Bits 16:31 - Port D hysteresis control on/off

`pub fn pc(&mut self) -> PC_W`[src]

Bits 0:15 - Port C hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR3>>`[src]

`pub fn pf(&mut self) -> PF_W`[src]

Bits 16:31 - Port F hysteresis control on/off

`pub fn pe(&mut self) -> PE_W`[src]

Bits 0:15 - Port E hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR4>>`[src]

`pub fn pg(&mut self) -> PG_W`[src]

Bits 0:15 - Port G hysteresis control on/off

`impl W<u32, Reg<u32, _TR>>`[src]

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn yt(&mut self) -> YT_W`[src]

Bits 20:23 - Year tens in BCD format

`pub fn yu(&mut self) -> YU_W`[src]

Bits 16:19 - Year units in BCD format

`pub fn wdu(&mut self) -> WDU_W`[src]

Bits 13:15 - Week day units

`pub fn mt(&mut self) -> MT_W`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&mut self) -> MU_W`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&mut self) -> DT_W`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&mut self) -> DU_W`[src]

Bits 0:3 - Date units in BCD format

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn coe(&mut self) -> COE_W`[src]

Bit 23 - Calibration output enable

`pub fn osel(&mut self) -> OSEL_W`[src]

Bits 21:22 - Output selection

`pub fn pol(&mut self) -> POL_W`[src]

Bit 20 - Output polarity

`pub fn cosel(&mut self) -> COSEL_W`[src]

Bit 19 - Calibration output selection

`pub fn bkp(&mut self) -> BKP_W`[src]

Bit 18 - Backup

`pub fn sub1h(&mut self) -> SUB1H_W`[src]

Bit 17 - Subtract 1 hour

`pub fn add1h(&mut self) -> ADD1H_W`[src]

Bit 16 - Add 1 hour

`pub fn tsie(&mut self) -> TSIE_W`[src]

Bit 15 - Time-stamp interrupt enable

`pub fn wutie(&mut self) -> WUTIE_W`[src]

Bit 14 - Wakeup timer interrupt enable

`pub fn alrbie(&mut self) -> ALRBIE_W`[src]

Bit 13 - Alarm B interrupt enable

`pub fn alraie(&mut self) -> ALRAIE_W`[src]

Bit 12 - Alarm A interrupt enable

`pub fn tse(&mut self) -> TSE_W`[src]

Bit 11 - Time stamp enable

`pub fn wute(&mut self) -> WUTE_W`[src]

Bit 10 - Wakeup timer enable

`pub fn alrbe(&mut self) -> ALRBE_W`[src]

Bit 9 - Alarm B enable

`pub fn alrae(&mut self) -> ALRAE_W`[src]

Bit 8 - Alarm A enable

`pub fn dce(&mut self) -> DCE_W`[src]

Bit 7 - Coarse digital calibration enable

`pub fn fmt(&mut self) -> FMT_W`[src]

Bit 6 - Hour format

`pub fn bypshad(&mut self) -> BYPSHAD_W`[src]

Bit 5 - Bypass the shadow registers

`pub fn refckon(&mut self) -> REFCKON_W`[src]

Bit 4 - Reference clock detection enable

`pub fn tsedge(&mut self) -> TSEDGE_W`[src]

Bit 3 - Time-stamp event active edge

`pub fn wcksel(&mut self) -> WCKSEL_W`[src]

Bits 0:2 - WCKSEL

`impl W<u32, Reg<u32, _ISR>>`[src]

`pub fn tamp3f(&mut self) -> TAMP3F_W`[src]

Bit 15 - TAMPER3 detection flag

`pub fn tamp2f(&mut self) -> TAMP2F_W`[src]

Bit 14 - TAMPER2 detection flag

`pub fn tamp1f(&mut self) -> TAMP1F_W`[src]

Bit 13 - Tamper detection flag

`pub fn tsovf(&mut self) -> TSOVF_W`[src]

Bit 12 - Timestamp overflow flag

`pub fn tsf(&mut self) -> TSF_W`[src]

Bit 11 - Timestamp flag

`pub fn wutf(&mut self) -> WUTF_W`[src]

Bit 10 - Wakeup timer flag

`pub fn alrbf(&mut self) -> ALRBF_W`[src]

Bit 9 - Alarm B flag

`pub fn alraf(&mut self) -> ALRAF_W`[src]

Bit 8 - Alarm A flag

`pub fn init(&mut self) -> INIT_W`[src]

Bit 7 - Initialization mode

`pub fn initf(&mut self) -> INITF_W`[src]

Bit 6 - Initialization flag

`pub fn rsf(&mut self) -> RSF_W`[src]

Bit 5 - Registers synchronization flag

`pub fn shpf(&mut self) -> SHPF_W`[src]

Bit 3 - Shift operation pending

`impl W<u32, Reg<u32, _PRER>>`[src]

`pub fn prediv_a(&mut self) -> PREDIV_A_W`[src]

Bits 16:22 - Asynchronous prescaler factor

`pub fn prediv_s(&mut self) -> PREDIV_S_W`[src]

Bits 0:14 - Synchronous prescaler factor

`impl W<u32, Reg<u32, _WUTR>>`[src]

`pub fn wut(&mut self) -> WUT_W`[src]

Bits 0:15 - Wakeup auto-reload value bits

`impl W<u32, Reg<u32, _CALIBR>>`[src]

`pub fn dcs(&mut self) -> DCS_W`[src]

Bit 7 - Digital calibration sign

`pub fn dc(&mut self) -> DC_W`[src]

Bits 0:4 - Digital calibration

`impl W<u32, Reg<u32, _ALRMAR>>`[src]

`pub fn msk4(&mut self) -> MSK4_W`[src]

Bit 31 - Alarm A date mask

`pub fn wdsel(&mut self) -> WDSEL_W`[src]

Bit 30 - Week day selection

`pub fn dt(&mut self) -> DT_W`[src]

Bits 28:29 - Date tens in BCD format.

`pub fn du(&mut self) -> DU_W`[src]

Bits 24:27 - Date units or day in BCD format.

`pub fn msk3(&mut self) -> MSK3_W`[src]

Bit 23 - Alarm A hours mask

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format.

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format.

`pub fn msk2(&mut self) -> MSK2_W`[src]

Bit 15 - Alarm A minutes mask

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format.

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format.

`pub fn msk1(&mut self) -> MSK1_W`[src]

Bit 7 - Alarm A seconds mask

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format.

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format.

`impl W<u32, Reg<u32, _ALRMBR>>`[src]

`pub fn msk4(&mut self) -> MSK4_W`[src]

Bit 31 - Alarm B date mask

`pub fn wdsel(&mut self) -> WDSEL_W`[src]

Bit 30 - Week day selection

`pub fn dt(&mut self) -> DT_W`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&mut self) -> DU_W`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&mut self) -> MSK3_W`[src]

Bit 23 - Alarm B hours mask

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&mut self) -> MSK2_W`[src]

Bit 15 - Alarm B minutes mask

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&mut self) -> MSK1_W`[src]

Bit 7 - Alarm B seconds mask

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format

`impl W<u32, Reg<u32, _WPR>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:7 - Write protection key

`impl W<u32, Reg<u32, _SHIFTR>>`[src]

`pub fn add1s(&mut self) -> ADD1S_W`[src]

Bit 31 - ADD1S

`pub fn subfs(&mut self) -> SUBFS_W`[src]

Bits 0:14 - Subtract a fraction of a second

`impl W<u32, Reg<u32, _CALR>>`[src]

`pub fn calp(&mut self) -> CALP_W`[src]

Bit 15 - Use an 8-second calibration cycle period

`pub fn calw8(&mut self) -> CALW8_W`[src]

Bit 14 - Use a 16-second calibration cycle period

`pub fn calw16(&mut self) -> CALW16_W`[src]

Bit 13 - CALW16

`pub fn calm(&mut self) -> CALM_W`[src]

Bits 0:8 - Calibration minus

`impl W<u32, Reg<u32, _TAFCR>>`[src]

`pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W`[src]

Bit 18 - AFO_ALARM output type

`pub fn tamppudis(&mut self) -> TAMPPUDIS_W`[src]

Bit 15 - TAMPER pull-up disable

`pub fn tampprch(&mut self) -> TAMPPRCH_W`[src]

Bits 13:14 - Tamper precharge duration

`pub fn tampflt(&mut self) -> TAMPFLT_W`[src]

Bits 11:12 - Tamper filter count

`pub fn tampfreq(&mut self) -> TAMPFREQ_W`[src]

Bits 8:10 - Tamper sampling frequency

`pub fn tampts(&mut self) -> TAMPTS_W`[src]

Bit 7 - Activate timestamp on tamper detection event

`pub fn tamp3trg(&mut self) -> TAMP3TRG_W`[src]

Bit 6 - TAMPER1 mapping

`pub fn tamp3e(&mut self) -> TAMP3E_W`[src]

Bit 5 - TIMESTAMP mapping

`pub fn tamp2trg(&mut self) -> TAMP2TRG_W`[src]

Bit 4 - Active level for tamper 2

`pub fn tamp2e(&mut self) -> TAMP2E_W`[src]

Bit 3 - Tamper 2 detection enable

`pub fn tampie(&mut self) -> TAMPIE_W`[src]

Bit 2 - Tamper interrupt enable

`pub fn tamp1etrg(&mut self) -> TAMP1ETRG_W`[src]

Bit 1 - Active level for tamper 1

`pub fn tamp1e(&mut self) -> TAMP1E_W`[src]

Bit 0 - Tamper 1 detection enable

`impl W<u32, Reg<u32, _ALRMASSR>>`[src]

`pub fn maskss(&mut self) -> MASKSS_W`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&mut self) -> SS_W`[src]

Bits 0:14 - Sub seconds value

`impl W<u32, Reg<u32, _ALRMBSSR>>`[src]

`pub fn maskss(&mut self) -> MASKSS_W`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&mut self) -> SS_W`[src]

Bits 0:14 - Sub seconds value

`impl W<u32, Reg<u32, _BKPR>>`[src]

`pub fn bkp(&mut self) -> BKP_W`[src]

Bits 0:31 - BKP

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn pwrctrl(&mut self) -> PWRCTRL_W`[src]

Bits 0:1 - Power supply control bits.

`impl W<u32, Reg<u32, _CLKCR>>`[src]

`pub fn hwfc_en(&mut self) -> HWFC_EN_W`[src]

Bit 14 - HW Flow Control enable

`pub fn negedge(&mut self) -> NEGEDGE_W`[src]

Bit 13 - SDIO_CK dephasing selection bit

`pub fn widbus(&mut self) -> WIDBUS_W`[src]

Bits 11:12 - Wide bus mode enable bit

`pub fn bypass(&mut self) -> BYPASS_W`[src]

Bit 10 - Clock divider bypass enable bit

`pub fn pwrsav(&mut self) -> PWRSAV_W`[src]

Bit 9 - Power saving configuration bit

`pub fn clken(&mut self) -> CLKEN_W`[src]

Bit 8 - Clock enable bit

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 0:7 - Clock divide factor

`impl W<u32, Reg<u32, _ARG>>`[src]

`pub fn cmdarg(&mut self) -> CMDARG_W`[src]

Bits 0:31 - Command argument

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn ce_atacmd(&mut self) -> CE_ATACMD_W`[src]

Bit 14 - CE-ATA command

`pub fn n_ien(&mut self) -> NIEN_W`[src]

Bit 13 - not Interrupt Enable

`pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W`[src]

Bit 12 - Enable CMD completion

`pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W`[src]

Bit 11 - SD I/O suspend command

`pub fn cpsmen(&mut self) -> CPSMEN_W`[src]

Bit 10 - Command path state machine (CPSM) Enable bit

`pub fn waitpend(&mut self) -> WAITPEND_W`[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

`pub fn waitint(&mut self) -> WAITINT_W`[src]

Bit 8 - CPSM waits for interrupt request

`pub fn waitresp(&mut self) -> WAITRESP_W`[src]

Bits 6:7 - Wait for response bits

`pub fn cmdindex(&mut self) -> CMDINDEX_W`[src]

Bits 0:5 - Command index

`impl W<u32, Reg<u32, _DTIMER>>`[src]

`pub fn datatime(&mut self) -> DATATIME_W`[src]

Bits 0:31 - Data timeout period

`impl W<u32, Reg<u32, _DLEN>>`[src]

`pub fn datalength(&mut self) -> DATALENGTH_W`[src]

Bits 0:24 - Data length value

`impl W<u32, Reg<u32, _DCTRL>>`[src]

`pub fn sdioen(&mut self) -> SDIOEN_W`[src]

Bit 11 - SD I/O enable functions

`pub fn rwmod(&mut self) -> RWMOD_W`[src]

Bit 10 - Read wait mode

`pub fn rwstop(&mut self) -> RWSTOP_W`[src]

Bit 9 - Read wait stop

`pub fn rwstart(&mut self) -> RWSTART_W`[src]

Bit 8 - Read wait start

`pub fn dblocksize(&mut self) -> DBLOCKSIZE_W`[src]

Bits 4:7 - Data block size

`pub fn dmaen(&mut self) -> DMAEN_W`[src]

Bit 3 - DMA enable bit

`pub fn dtmode(&mut self) -> DTMODE_W`[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

`pub fn dtdir(&mut self) -> DTDIR_W`[src]

Bit 1 - Data transfer direction selection

`pub fn dten(&mut self) -> DTEN_W`[src]

Bit 0 - Data transfer enabled bit

`impl W<u32, Reg<u32, _ICR>>`[src]

`pub fn ceataendc(&mut self) -> CEATAENDC_W`[src]

Bit 23 - CEATAEND flag clear bit

`pub fn sdioitc(&mut self) -> SDIOITC_W`[src]

Bit 22 - SDIOIT flag clear bit

`pub fn dbckendc(&mut self) -> DBCKENDC_W`[src]

Bit 10 - DBCKEND flag clear bit

`pub fn stbiterrc(&mut self) -> STBITERRC_W`[src]

Bit 9 - STBITERR flag clear bit

`pub fn dataendc(&mut self) -> DATAENDC_W`[src]

Bit 8 - DATAEND flag clear bit

`pub fn cmdsentc(&mut self) -> CMDSENTC_W`[src]

Bit 7 - CMDSENT flag clear bit

`pub fn cmdrendc(&mut self) -> CMDRENDC_W`[src]

Bit 6 - CMDREND flag clear bit

`pub fn rxoverrc(&mut self) -> RXOVERRC_W`[src]

Bit 5 - RXOVERR flag clear bit

`pub fn txunderrc(&mut self) -> TXUNDERRC_W`[src]

Bit 4 - TXUNDERR flag clear bit

`pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W`[src]

Bit 3 - DTIMEOUT flag clear bit

`pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W`[src]

Bit 2 - CTIMEOUT flag clear bit

`pub fn dcrcfailc(&mut self) -> DCRCFAILC_W`[src]

Bit 1 - DCRCFAIL flag clear bit

`pub fn ccrcfailc(&mut self) -> CCRCFAILC_W`[src]

Bit 0 - CCRCFAIL flag clear bit

`impl W<u32, Reg<u32, _MASK>>`[src]

`pub fn ceataendie(&mut self) -> CEATAENDIE_W`[src]

Bit 23 - CE-ATA command completion signal received interrupt enable

`pub fn sdioitie(&mut self) -> SDIOITIE_W`[src]

Bit 22 - SDIO mode interrupt received interrupt enable

`pub fn rxdavlie(&mut self) -> RXDAVLIE_W`[src]

Bit 21 - Data available in Rx FIFO interrupt enable

`pub fn txdavlie(&mut self) -> TXDAVLIE_W`[src]

Bit 20 - Data available in Tx FIFO interrupt enable

`pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W`[src]

Bit 19 - Rx FIFO empty interrupt enable

`pub fn txfifoeie(&mut self) -> TXFIFOEIE_W`[src]

Bit 18 - Tx FIFO empty interrupt enable

`pub fn rxfifofie(&mut self) -> RXFIFOFIE_W`[src]

Bit 17 - Rx FIFO full interrupt enable

`pub fn txfifofie(&mut self) -> TXFIFOFIE_W`[src]

Bit 16 - Tx FIFO full interrupt enable

`pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W`[src]

Bit 15 - Rx FIFO half full interrupt enable

`pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W`[src]

Bit 14 - Tx FIFO half empty interrupt enable

`pub fn rxactie(&mut self) -> RXACTIE_W`[src]

Bit 13 - Data receive acting interrupt enable

`pub fn txactie(&mut self) -> TXACTIE_W`[src]

Bit 12 - Data transmit acting interrupt enable

`pub fn cmdactie(&mut self) -> CMDACTIE_W`[src]

Bit 11 - Command acting interrupt enable

`pub fn dbckendie(&mut self) -> DBCKENDIE_W`[src]

Bit 10 - Data block end interrupt enable

`pub fn stbiterrie(&mut self) -> STBITERRIE_W`[src]

Bit 9 - Start bit error interrupt enable

`pub fn dataendie(&mut self) -> DATAENDIE_W`[src]

Bit 8 - Data end interrupt enable

`pub fn cmdsentie(&mut self) -> CMDSENTIE_W`[src]

Bit 7 - Command sent interrupt enable

`pub fn cmdrendie(&mut self) -> CMDRENDIE_W`[src]

Bit 6 - Command response received interrupt enable

`pub fn rxoverrie(&mut self) -> RXOVERRIE_W`[src]

Bit 5 - Rx FIFO overrun error interrupt enable

`pub fn txunderrie(&mut self) -> TXUNDERRIE_W`[src]

Bit 4 - Tx FIFO underrun error interrupt enable

`pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W`[src]

Bit 3 - Data timeout interrupt enable

`pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W`[src]

Bit 2 - Command timeout interrupt enable

`pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W`[src]

Bit 1 - Data CRC fail interrupt enable

`pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W`[src]

Bit 0 - Command CRC fail interrupt enable

`impl W<u32, Reg<u32, _FIFO>>`[src]

`pub fn fif0data(&mut self) -> FIF0DATA_W`[src]

Bits 0:31 - FIF0Data

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn bidimode(&mut self) -> BIDIMODE_W`[src]

Bit 15 - Bidirectional data mode enable

`pub fn bidioe(&mut self) -> BIDIOE_W`[src]

Bit 14 - Output enable in bidirectional mode

`pub fn crcen(&mut self) -> CRCEN_W`[src]

Bit 13 - Hardware CRC calculation enable

`pub fn crcnext(&mut self) -> CRCNEXT_W`[src]

Bit 12 - CRC transfer next

`pub fn dff(&mut self) -> DFF_W`[src]

Bit 11 - Data frame format

`pub fn rxonly(&mut self) -> RXONLY_W`[src]

Bit 10 - Receive only

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 9 - Software slave management

`pub fn ssi(&mut self) -> SSI_W`[src]

Bit 8 - Internal slave select

`pub fn lsbfirst(&mut self) -> LSBFIRST_W`[src]

Bit 7 - Frame format

`pub fn spe(&mut self) -> SPE_W`[src]

Bit 6 - SPI enable

`pub fn br(&mut self) -> BR_W`[src]

Bits 3:5 - Baud rate control

`pub fn mstr(&mut self) -> MSTR_W`[src]

Bit 2 - Master selection

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 1 - Clock polarity

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 0 - Clock phase

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn txeie(&mut self) -> TXEIE_W`[src]

Bit 7 - Tx buffer empty interrupt enable

`pub fn rxneie(&mut self) -> RXNEIE_W`[src]

Bit 6 - RX buffer not empty interrupt enable

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 5 - Error interrupt enable

`pub fn frf(&mut self) -> FRF_W`[src]

Bit 4 - Frame format

`pub fn ssoe(&mut self) -> SSOE_W`[src]

Bit 2 - SS output enable

`pub fn txdmaen(&mut self) -> TXDMAEN_W`[src]

Bit 1 - Tx buffer DMA enable

`pub fn rxdmaen(&mut self) -> RXDMAEN_W`[src]

Bit 0 - Rx buffer DMA enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn crcerr(&mut self) -> CRCERR_W`[src]

Bit 4 - CRC error flag

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:15 - Data register

`impl W<u32, Reg<u32, _CRCPR>>`[src]

`pub fn crcpoly(&mut self) -> CRCPOLY_W`[src]

Bits 0:15 - CRC polynomial register

`impl W<u32, Reg<u32, _I2SCFGR>>`[src]

`pub fn i2smod(&mut self) -> I2SMOD_W`[src]

Bit 11 - I2S mode selection

`pub fn i2se(&mut self) -> I2SE_W`[src]

Bit 10 - I2S Enable

`pub fn i2scfg(&mut self) -> I2SCFG_W`[src]

Bits 8:9 - I2S configuration mode

`pub fn pcmsync(&mut self) -> PCMSYNC_W`[src]

Bit 7 - PCM frame synchronization

`pub fn i2sstd(&mut self) -> I2SSTD_W`[src]

Bits 4:5 - I2S standard selection

`pub fn ckpol(&mut self) -> CKPOL_W`[src]

Bit 3 - Steady state clock polarity

`pub fn datlen(&mut self) -> DATLEN_W`[src]

Bits 1:2 - Data length to be transferred

`pub fn chlen(&mut self) -> CHLEN_W`[src]

Bit 0 - Channel length (number of bits per audio channel)

`impl W<u32, Reg<u32, _I2SPR>>`[src]

`pub fn mckoe(&mut self) -> MCKOE_W`[src]

Bit 9 - Master clock output enable

`pub fn odd(&mut self) -> ODD_W`[src]

Bit 8 - Odd factor for the prescaler

`pub fn i2sdiv(&mut self) -> I2SDIV_W`[src]

Bits 0:7 - I2S Linear prescaler

`impl W<u32, Reg<u32, _MEMRMP>>`[src]

`pub fn mem_mode(&mut self) -> MEM_MODE_W`[src]

Bits 0:1 - MEM_MODE

`impl W<u32, Reg<u32, _PMC>>`[src]

`pub fn usb_pu(&mut self) -> USB_PU_W`[src]

Bit 0 - USB pull-up

`pub fn lcd_capa(&mut self) -> LCD_CAPA_W`[src]

Bits 1:5 - USB pull-up enable on DP line

`impl W<u32, Reg<u32, _EXTICR1>>`[src]

`pub fn exti3(&mut self) -> EXTI3_W`[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

`pub fn exti2(&mut self) -> EXTI2_W`[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

`pub fn exti1(&mut self) -> EXTI1_W`[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

`pub fn exti0(&mut self) -> EXTI0_W`[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

`impl W<u32, Reg<u32, _EXTICR2>>`[src]

`pub fn exti7(&mut self) -> EXTI7_W`[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

`pub fn exti6(&mut self) -> EXTI6_W`[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

`pub fn exti5(&mut self) -> EXTI5_W`[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

`pub fn exti4(&mut self) -> EXTI4_W`[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

`impl W<u32, Reg<u32, _EXTICR3>>`[src]

`pub fn exti11(&mut self) -> EXTI11_W`[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

`pub fn exti10(&mut self) -> EXTI10_W`[src]

Bits 8:11 - EXTI10

`pub fn exti9(&mut self) -> EXTI9_W`[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

`pub fn exti8(&mut self) -> EXTI8_W`[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

`impl W<u32, Reg<u32, _EXTICR4>>`[src]

`pub fn exti15(&mut self) -> EXTI15_W`[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

`pub fn exti14(&mut self) -> EXTI14_W`[src]

Bits 8:11 - EXTI14

`pub fn exti13(&mut self) -> EXTI13_W`[src]

Bits 4:7 - EXTI13

`pub fn exti12(&mut self) -> EXTI12_W`[src]

Bits 0:3 - EXTI12

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM10 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - Timer 10 input 1 remap

`pub fn etr_rmp(&mut self) -> ETR_RMP_W`[src]

Bit 2 - Timer10 ETR remap

`pub fn ti1_rmp_ri(&mut self) -> TI1_RMP_RI_W`[src]

Bit 3 - Timer10 Input 1 remap for Routing Interface (RI)

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn etf(&mut self) -> ETF_W`[src]

Bits 8:11 - External trigger filter

`pub fn etps(&mut self) -> ETPS_W`[src]

Bits 12:13 - External trigger prescaler

`pub fn ece(&mut self) -> ECE_W`[src]

Bit 14 - External clock enable

`pub fn etp(&mut self) -> ETP_W`[src]

Bit 15 - External trigger polarity

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM10 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - TIM11 Input 1 remapping capability

`pub fn etr_rmp(&mut self) -> ETR_RMP_W`[src]

Bit 2 - Timer11 ETR remap

`pub fn ti1_rmp_ri(&mut self) -> TI1_RMP_RI_W`[src]

Bit 3 - Timer11 Input 1 remap for Routing Interface (RI)

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn etf(&mut self) -> ETF_W`[src]

Bits 8:11 - External trigger filter

`pub fn etps(&mut self) -> ETPS_W`[src]

Bits 12:13 - External trigger prescaler

`pub fn ece(&mut self) -> ECE_W`[src]

Bit 14 - External clock enable

`pub fn etp(&mut self) -> ETP_W`[src]

Bit 15 - External trigger polarity

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&mut self) -> CMS_W`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Direction

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn ti1s(&mut self) -> TI1S_W`[src]

Bit 7 - TI1 selection

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&mut self) -> CCDS_W`[src]

Bit 3 - Capture/compare DMA selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&mut self) -> ETP_W`[src]

Bit 15 - External trigger polarity

`pub fn ece(&mut self) -> ECE_W`[src]

Bit 14 - External clock enable

`pub fn etps(&mut self) -> ETPS_W`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&mut self) -> ETF_W`[src]

Bits 8:11 - External trigger filter

`pub fn msm(&mut self) -> MSM_W`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&mut self) -> TS_W`[src]

Bits 4:6 - Trigger selection

`pub fn occs(&mut self) -> OCCS_W`[src]

Bit 3 - OCREF clear selection

`pub fn sms(&mut self) -> SMS_W`[src]

Bits 0:2 - Slave mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn tde(&mut self) -> TDE_W`[src]

Bit 14 - Trigger DMA request enable

`pub fn cc4de(&mut self) -> CC4DE_W`[src]

Bit 12 - Capture/Compare 4 DMA request enable

`pub fn cc3de(&mut self) -> CC3DE_W`[src]

Bit 11 - Capture/Compare 3 DMA request enable

`pub fn cc2de(&mut self) -> CC2DE_W`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&mut self) -> CC1DE_W`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&mut self) -> UDE_W`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&mut self) -> TIE_W`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&mut self) -> CC4IE_W`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&mut self) -> CC3IE_W`[src]

Bit 3 - Capture/Compare 3 interrupt enable

`pub fn cc2ie(&mut self) -> CC2IE_W`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc4of(&mut self) -> CC4OF_W`[src]

Bit 12 - Capture/compare 1 overcapture flag

`pub fn cc3of(&mut self) -> CC3OF_W`[src]

Bit 11 - Capture/compare 3 overcapture flag

`pub fn cc2of(&mut self) -> CC2OF_W`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn tif(&mut self) -> TIF_W`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&mut self) -> CC4IF_W`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&mut self) -> CC3IF_W`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&mut self) -> CC2IF_W`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn tg(&mut self) -> TG_W`[src]

Bit 6 - Trigger generation

`pub fn cc4g(&mut self) -> CC4G_W`[src]

Bit 4 - Capture/compare 4 generation

`pub fn cc3g(&mut self) -> CC3G_W`[src]

Bit 3 - Capture/compare 3 generation

`pub fn cc2g(&mut self) -> CC2G_W`[src]

Bit 2 - Capture/compare 2 generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&mut self) -> OC2CE_W`[src]

Bit 15 - Output compare 2 clear enable

`pub fn oc2m(&mut self) -> OC2M_W`[src]

Bits 12:14 - Output compare 2 mode

`pub fn oc2pe(&mut self) -> OC2PE_W`[src]

Bit 11 - Output compare 2 preload enable

`pub fn oc2fe(&mut self) -> OC2FE_W`[src]

Bit 10 - Output compare 2 fast enable

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bit 8 - Capture/Compare 2 selection

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&mut self) -> IC2F_W`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&mut self) -> IC2PSC_W`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&mut self) -> OC4CE_W`[src]

Bit 15 - Output compare 4 clear enable

`pub fn oc4m(&mut self) -> OC4M_W`[src]

Bits 12:14 - Output compare 4 mode

`pub fn oc4pe(&mut self) -> OC4PE_W`[src]

Bit 11 - Output compare 4 preload enable

`pub fn oc4fe(&mut self) -> OC4FE_W`[src]

Bit 10 - Output compare 4 fast enable

`pub fn cc4s(&mut self) -> CC4S_W`[src]

Bit 8 - Capture/Compare 4 selection

`pub fn oc3ce(&mut self) -> OC3CE_W`[src]

Bit 7 - Output compare 3 clear enable

`pub fn oc3m(&mut self) -> OC3M_W`[src]

Bits 4:6 - Output compare 3 mode

`pub fn oc3pe(&mut self) -> OC3PE_W`[src]

Bit 3 - Output compare 3 preload enable

`pub fn oc3fe(&mut self) -> OC3FE_W`[src]

Bit 2 - Output compare 3 fast enable

`pub fn cc3s(&mut self) -> CC3S_W`[src]

Bits 0:1 - Capture/Compare 3 selection

`impl W<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&mut self) -> IC4F_W`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&mut self) -> IC4PSC_W`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&mut self) -> CC4S_W`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&mut self) -> IC3F_W`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&mut self) -> IC3PSC_W`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&mut self) -> CC3S_W`[src]

Bits 0:1 - Capture/compare 3 selection

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&mut self) -> CC4NP_W`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&mut self) -> CC4P_W`[src]

Bit 13 - Capture/Compare 4 output Polarity

`pub fn cc4e(&mut self) -> CC4E_W`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&mut self) -> CC3NP_W`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&mut self) -> CC3P_W`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&mut self) -> CC3E_W`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&mut self) -> CC2NP_W`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&mut self) -> CC2P_W`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&mut self) -> CC2E_W`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM2 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM2 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&mut self) -> DBL_W`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&mut self) -> DBA_W`[src]

Bits 0:4 - DMA base address

`impl W<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&mut self) -> DMAB_W`[src]

Bits 0:15 - DMA register for burst accesses

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn ude(&mut self) -> UDE_W`[src]

Bit 8 - Update DMA request enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - CNT

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Prescaler value

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn msm(&mut self) -> MSM_W`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&mut self) -> TS_W`[src]

Bits 4:6 - Trigger selection

`pub fn sms(&mut self) -> SMS_W`[src]

Bits 0:2 - Slave mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn tie(&mut self) -> TIE_W`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc2ie(&mut self) -> CC2IE_W`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc2of(&mut self) -> CC2OF_W`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn tif(&mut self) -> TIF_W`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc2if(&mut self) -> CC2IF_W`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn tg(&mut self) -> TG_W`[src]

Bit 6 - Trigger generation

`pub fn cc2g(&mut self) -> CC2G_W`[src]

Bit 2 - Capture/Compare 2 generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&mut self) -> OC2CE_W`[src]

Bit 15 - Output compare 2 clear enable

`pub fn oc2m(&mut self) -> OC2M_W`[src]

Bits 12:14 - Output compare 2 mode

`pub fn oc2pe(&mut self) -> OC2PE_W`[src]

Bit 11 - Output compare 2 preload enable

`pub fn oc2fe(&mut self) -> OC2FE_W`[src]

Bit 10 - Output compare 2 fast enable

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bit 8 - Capture/Compare 2 selection

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&mut self) -> IC2F_W`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&mut self) -> IC2PSC_W`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM9 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - TIM9 Input 1 remapping capability

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 9 - CTS flag

`pub fn lbd(&mut self) -> LBD_W`[src]

Bit 8 - LIN break detection flag

`pub fn tc(&mut self) -> TC_W`[src]

Bit 6 - Transmission complete

`pub fn rxne(&mut self) -> RXNE_W`[src]

Bit 5 - Read data register not empty

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:8 - Data value

`impl W<u32, Reg<u32, _BRR>>`[src]

`pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W`[src]

Bits 4:15 - mantissa of USARTDIV

`pub fn div_fraction(&mut self) -> DIV_FRACTION_W`[src]

Bits 0:3 - fraction of USARTDIV

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn over8(&mut self) -> OVER8_W`[src]

Bit 15 - Oversampling mode

`pub fn ue(&mut self) -> UE_W`[src]

Bit 13 - USART enable

`pub fn m(&mut self) -> M_W`[src]

Bit 12 - Word length

`pub fn wake(&mut self) -> WAKE_W`[src]

Bit 11 - Wakeup method

`pub fn pce(&mut self) -> PCE_W`[src]

Bit 10 - Parity control enable

`pub fn ps(&mut self) -> PS_W`[src]

Bit 9 - Parity selection

`pub fn peie(&mut self) -> PEIE_W`[src]

Bit 8 - PE interrupt enable

`pub fn txeie(&mut self) -> TXEIE_W`[src]

Bit 7 - TXE interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 6 - Transmission complete interrupt enable

`pub fn rxneie(&mut self) -> RXNEIE_W`[src]

Bit 5 - RXNE interrupt enable

`pub fn idleie(&mut self) -> IDLEIE_W`[src]

Bit 4 - IDLE interrupt enable

`pub fn te(&mut self) -> TE_W`[src]

Bit 3 - Transmitter enable

`pub fn re(&mut self) -> RE_W`[src]

Bit 2 - Receiver enable

`pub fn rwu(&mut self) -> RWU_W`[src]

Bit 1 - Receiver wakeup

`pub fn sbk(&mut self) -> SBK_W`[src]

Bit 0 - Send break

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn linen(&mut self) -> LINEN_W`[src]

Bit 14 - LIN mode enable

`pub fn stop(&mut self) -> STOP_W`[src]

Bits 12:13 - STOP bits

`pub fn clken(&mut self) -> CLKEN_W`[src]

Bit 11 - Clock enable

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 10 - Clock polarity

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 9 - Clock phase

`pub fn lbcl(&mut self) -> LBCL_W`[src]

Bit 8 - Last bit clock pulse

`pub fn lbdie(&mut self) -> LBDIE_W`[src]

Bit 6 - LIN break detection interrupt enable

`pub fn lbdl(&mut self) -> LBDL_W`[src]

Bit 5 - lin break detection length

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:3 - Address of the USART node

`impl W<u32, Reg<u32, _CR3>>`[src]

`pub fn onebit(&mut self) -> ONEBIT_W`[src]

Bit 11 - One sample bit method enable

`pub fn ctsie(&mut self) -> CTSIE_W`[src]

Bit 10 - CTS interrupt enable

`pub fn ctse(&mut self) -> CTSE_W`[src]

Bit 9 - CTS enable

`pub fn rtse(&mut self) -> RTSE_W`[src]

Bit 8 - RTS enable

`pub fn dmat(&mut self) -> DMAT_W`[src]

Bit 7 - DMA enable transmitter

`pub fn dmar(&mut self) -> DMAR_W`[src]

Bit 6 - DMA enable receiver

`pub fn scen(&mut self) -> SCEN_W`[src]

Bit 5 - Smartcard mode enable

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 4 - Smartcard NACK enable

`pub fn hdsel(&mut self) -> HDSEL_W`[src]

Bit 3 - Half-duplex selection

`pub fn irlp(&mut self) -> IRLP_W`[src]

Bit 2 - IrDA low-power

`pub fn iren(&mut self) -> IREN_W`[src]

Bit 1 - IrDA mode enable

`pub fn eie(&mut self) -> EIE_W`[src]

Bit 0 - Error interrupt enable

`impl W<u32, Reg<u32, _GTPR>>`[src]

`pub fn gt(&mut self) -> GT_W`[src]

Bits 8:15 - Guard time value

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:7 - Prescaler value

`impl W<u32, Reg<u32, _EP0R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP1R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP2R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP3R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP4R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP5R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP6R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP7R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _CNTR>>`[src]

`pub fn fres(&mut self) -> FRES_W`[src]

Bit 0 - Force USB Reset

`pub fn pdwn(&mut self) -> PDWN_W`[src]

Bit 1 - Power down

`pub fn lpmode(&mut self) -> LPMODE_W`[src]

Bit 2 - Low-power mode

`pub fn fsusp(&mut self) -> FSUSP_W`[src]

Bit 3 - Force suspend

`pub fn resume(&mut self) -> RESUME_W`[src]

Bit 4 - Resume request

`pub fn esofm(&mut self) -> ESOFM_W`[src]

Bit 8 - Expected start of frame interrupt mask

`pub fn sofm(&mut self) -> SOFM_W`[src]

Bit 9 - Start of frame interrupt mask

`pub fn resetm(&mut self) -> RESETM_W`[src]

Bit 10 - USB reset interrupt mask

`pub fn suspm(&mut self) -> SUSPM_W`[src]

Bit 11 - Suspend mode interrupt mask

`pub fn wkupm(&mut self) -> WKUPM_W`[src]

Bit 12 - Wakeup interrupt mask

`pub fn errm(&mut self) -> ERRM_W`[src]

Bit 13 - Error interrupt mask

`pub fn pmaovrm(&mut self) -> PMAOVRM_W`[src]

Bit 14 - Packet memory area over / underrun interrupt mask

`pub fn ctrm(&mut self) -> CTRM_W`[src]

Bit 15 - Correct transfer interrupt mask

`impl W<u32, Reg<u32, _ISTR>>`[src]

`pub fn ep_id(&mut self) -> EP_ID_W`[src]

Bits 0:3 - Endpoint Identifier

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Direction of transaction

`pub fn esof(&mut self) -> ESOF_W`[src]

Bit 8 - Expected start frame

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 9 - start of frame

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 10 - reset request

`pub fn susp(&mut self) -> SUSP_W`[src]

Bit 11 - Suspend mode request

`pub fn wkup(&mut self) -> WKUP_W`[src]

Bit 12 - Wakeup

`pub fn err(&mut self) -> ERR_W`[src]

Bit 13 - Error

`pub fn pmaovr(&mut self) -> PMAOVR_W`[src]

Bit 14 - Packet memory area over / underrun

`pub fn ctr(&mut self) -> CTR_W`[src]

Bit 15 - Correct transfer

`impl W<u32, Reg<u32, _DADDR>>`[src]

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:6 - Device address

`pub fn ef(&mut self) -> EF_W`[src]

Bit 7 - Enable function

`impl W<u32, Reg<u32, _BTABLE>>`[src]

`pub fn btable(&mut self) -> BTABLE_W`[src]

Bits 3:15 - Buffer table

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn wdga(&mut self) -> WDGA_W`[src]

Bit 7 - Activation bit

`pub fn t(&mut self) -> T_W`[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

`impl W<u32, Reg<u32, _CFR>>`[src]

`pub fn ewi(&mut self) -> EWI_W`[src]

Bit 9 - Early wakeup interrupt

`pub fn w(&mut self) -> W_W`[src]

Bits 0:6 - 7-bit window value

`pub fn wdgtb(&mut self) -> WDGTB_W`[src]

Bits 7:8 - Timer base

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn ewif(&mut self) -> EWIF_W`[src]

Bit 0 - EWIF

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn ovr(&mut self) -> OVR_W`[src]

Bit 5 - Overrun

`pub fn strt(&mut self) -> STRT_W`[src]

Bit 4 - Regular channel start flag

`pub fn jstrt(&mut self) -> JSTRT_W`[src]

Bit 3 - Injected channel start flag

`pub fn jeoc(&mut self) -> JEOC_W`[src]

Bit 2 - Injected channel end of conversion

`pub fn eoc(&mut self) -> EOC_W`[src]

Bit 1 - Regular channel end of conversion

`pub fn awd(&mut self) -> AWD_W`[src]

Bit 0 - Analog watchdog flag

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ovrie(&mut self) -> OVRIE_W`[src]

Bit 26 - Overrun interrupt enable

`pub fn res(&mut self) -> RES_W`[src]

Bits 24:25 - Resolution

`pub fn awden(&mut self) -> AWDEN_W`[src]

Bit 23 - Analog watchdog enable on regular channels

`pub fn jawden(&mut self) -> JAWDEN_W`[src]

Bit 22 - Analog watchdog enable on injected channels

`pub fn pdi(&mut self) -> PDI_W`[src]

Bit 17 - Power down during the idle phase

`pub fn pdd(&mut self) -> PDD_W`[src]

Bit 16 - Power down during the delay phase

`pub fn discnum(&mut self) -> DISCNUM_W`[src]

Bits 13:15 - Discontinuous mode channel count

`pub fn jdiscen(&mut self) -> JDISCEN_W`[src]

Bit 12 - Discontinuous mode on injected channels

`pub fn discen(&mut self) -> DISCEN_W`[src]

Bit 11 - Discontinuous mode on regular channels

`pub fn jauto(&mut self) -> JAUTO_W`[src]

Bit 10 - Automatic injected group conversion

`pub fn awdsgl(&mut self) -> AWDSGL_W`[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

`pub fn scan(&mut self) -> SCAN_W`[src]

Bit 8 - Scan mode

`pub fn jeocie(&mut self) -> JEOCIE_W`[src]

Bit 7 - Interrupt enable for injected channels

`pub fn awdie(&mut self) -> AWDIE_W`[src]

Bit 6 - Analog watchdog interrupt enable

`pub fn eocie(&mut self) -> EOCIE_W`[src]

Bit 5 - Interrupt enable for EOC

`pub fn awdch(&mut self) -> AWDCH_W`[src]

Bits 0:4 - Analog watchdog channel select bits

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn swstart(&mut self) -> SWSTART_W`[src]

Bit 30 - Start conversion of regular channels

`pub fn exten(&mut self) -> EXTEN_W`[src]

Bits 28:29 - External trigger enable for regular channels

`pub fn extsel(&mut self) -> EXTSEL_W`[src]

Bits 24:27 - External event select for regular group

`pub fn jswstart(&mut self) -> JSWSTART_W`[src]

Bit 22 - Start conversion of injected channels

`pub fn jexten(&mut self) -> JEXTEN_W`[src]

Bits 20:21 - External trigger enable for injected channels

`pub fn jextsel(&mut self) -> JEXTSEL_W`[src]

Bits 16:19 - External event select for injected group

`pub fn align(&mut self) -> ALIGN_W`[src]

Bit 11 - Data alignment

`pub fn eocs(&mut self) -> EOCS_W`[src]

Bit 10 - End of conversion selection

`pub fn dds(&mut self) -> DDS_W`[src]

Bit 9 - DMA disable selection

`pub fn dma(&mut self) -> DMA_W`[src]

Bit 8 - Direct memory access mode

`pub fn dels(&mut self) -> DELS_W`[src]

Bits 4:6 - Delay selection

`pub fn adc_cfg(&mut self) -> ADC_CFG_W`[src]

Bit 2 - ADC configuration

`pub fn cont(&mut self) -> CONT_W`[src]

Bit 1 - Continuous conversion

`pub fn adon(&mut self) -> ADON_W`[src]

Bit 0 - A/D Converter ON / OFF

`impl W<u32, Reg<u32, _SMPR1>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel sampling time selection

`impl W<u32, Reg<u32, _SMPR2>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel sampling time selection

`impl W<u32, Reg<u32, _SMPR3>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel Sample time selection

`impl W<u32, Reg<u32, _JOFR1>>`[src]

`pub fn joffset1(&mut self) -> JOFFSET1_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR2>>`[src]

`pub fn joffset2(&mut self) -> JOFFSET2_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR3>>`[src]

`pub fn joffset3(&mut self) -> JOFFSET3_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR4>>`[src]

`pub fn joffset4(&mut self) -> JOFFSET4_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _HTR>>`[src]

`pub fn ht(&mut self) -> HT_W`[src]

Bits 0:11 - Analog watchdog higher threshold

`impl W<u32, Reg<u32, _LTR>>`[src]

`pub fn lt(&mut self) -> LT_W`[src]

Bits 0:11 - Analog watchdog lower threshold

`impl W<u32, Reg<u32, _SQR1>>`[src]

`pub fn l(&mut self) -> L_W`[src]

Bits 20:23 - Regular channel sequence length

`pub fn sq28(&mut self) -> SQ28_W`[src]

Bits 15:19 - 28th conversion in regular sequence

`pub fn sq27(&mut self) -> SQ27_W`[src]

Bits 10:14 - 27th conversion in regular sequence

`pub fn sq26(&mut self) -> SQ26_W`[src]

Bits 5:9 - 26th conversion in regular sequence

`pub fn sq25(&mut self) -> SQ25_W`[src]

Bits 0:4 - 25th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR2>>`[src]

`pub fn sq24(&mut self) -> SQ24_W`[src]

Bits 25:29 - 24th conversion in regular sequence

`pub fn sq23(&mut self) -> SQ23_W`[src]

Bits 20:24 - 23rd conversion in regular sequence

`pub fn sq22(&mut self) -> SQ22_W`[src]

Bits 15:19 - 22nd conversion in regular sequence

`pub fn sq21(&mut self) -> SQ21_W`[src]

Bits 10:14 - 21st conversion in regular sequence

`pub fn sq20(&mut self) -> SQ20_W`[src]

Bits 5:9 - 20th conversion in regular sequence

`pub fn sq19(&mut self) -> SQ19_W`[src]

Bits 0:4 - 19th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR3>>`[src]

`pub fn sq18(&mut self) -> SQ18_W`[src]

Bits 25:29 - 18th conversion in regular sequence

`pub fn sq17(&mut self) -> SQ17_W`[src]

Bits 20:24 - 17th conversion in regular sequence

`pub fn sq16(&mut self) -> SQ16_W`[src]

Bits 15:19 - 16th conversion in regular sequence

`pub fn sq15(&mut self) -> SQ15_W`[src]

Bits 10:14 - 15th conversion in regular sequence

`pub fn sq14(&mut self) -> SQ14_W`[src]

Bits 5:9 - 14th conversion in regular sequence

`pub fn sq13(&mut self) -> SQ13_W`[src]

Bits 0:4 - 13th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR4>>`[src]

`pub fn sq12(&mut self) -> SQ12_W`[src]

Bits 25:29 - 12th conversion in regular sequence

`pub fn sq11(&mut self) -> SQ11_W`[src]

Bits 20:24 - 11th conversion in regular sequence

`pub fn sq10(&mut self) -> SQ10_W`[src]

Bits 15:19 - 10th conversion in regular sequence

`pub fn sq9(&mut self) -> SQ9_W`[src]

Bits 10:14 - 9th conversion in regular sequence

`pub fn sq8(&mut self) -> SQ8_W`[src]

Bits 5:9 - 8th conversion in regular sequence

`pub fn sq7(&mut self) -> SQ7_W`[src]

Bits 0:4 - 7th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR5>>`[src]

`pub fn sq6(&mut self) -> SQ6_W`[src]

Bits 25:29 - 6th conversion in regular sequence

`pub fn sq5(&mut self) -> SQ5_W`[src]

Bits 20:24 - 5th conversion in regular sequence

`pub fn sq4(&mut self) -> SQ4_W`[src]

Bits 15:19 - 4th conversion in regular sequence

`pub fn sq3(&mut self) -> SQ3_W`[src]

Bits 10:14 - 3rd conversion in regular sequence

`pub fn sq2(&mut self) -> SQ2_W`[src]

Bits 5:9 - 2nd conversion in regular sequence

`pub fn sq1(&mut self) -> SQ1_W`[src]

Bits 0:4 - 1st conversion in regular sequence

`impl W<u32, Reg<u32, _JSQR>>`[src]

`pub fn jl(&mut self) -> JL_W`[src]

Bits 20:21 - Injected sequence length

`pub fn jsq4(&mut self) -> JSQ4_W`[src]

Bits 15:19 - 4th conversion in injected sequence

`pub fn jsq3(&mut self) -> JSQ3_W`[src]

Bits 10:14 - 3rd conversion in injected sequence

`pub fn jsq2(&mut self) -> JSQ2_W`[src]

Bits 5:9 - 2nd conversion in injected sequence

`pub fn jsq1(&mut self) -> JSQ1_W`[src]

Bits 0:4 - 1st conversion in injected sequence

`impl W<u32, Reg<u32, _SMPR0>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:5 - Channel Sample time selection

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn adcpre(&mut self) -> ADCPRE_W`[src]

Bits 16:17 - ADC prescaler

`pub fn tsvrefe(&mut self) -> TSVREFE_W`[src]

Bit 23 - Temperature sensor and VREFINT enable

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W`[src]

Bit 0 - Debug Sleep mode

`pub fn dbg_stop(&mut self) -> DBG_STOP_W`[src]

Bit 1 - Debug Stop mode

`pub fn dbg_standby(&mut self) -> DBG_STANDBY_W`[src]

Bit 2 - Debug Standby mode

`pub fn trace_ioen(&mut self) -> TRACE_IOEN_W`[src]

Bit 5 - Trace pin assignment control

`pub fn trace_mode(&mut self) -> TRACE_MODE_W`[src]

Bits 6:7 - Trace pin assignment control

`impl W<u32, Reg<u32, _APB1_FZ>>`[src]

`pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W`[src]

Bit 0 - TIM2 counter stopped when core is halted

`pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W`[src]

Bit 1 - TIM3 counter stopped when core is halted

`pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W`[src]

Bit 2 - TIM4 counter stopped when core is halted

`pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W`[src]

Bit 3 - TIM5 counter stopped when core is halted

`pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W`[src]

Bit 4 - TIM6 counter stopped when core is halted

`pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W`[src]

Bit 5 - TIM7 counter stopped when core is halted

`pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W`[src]

Bit 10 - Debug RTC stopped when core is halted

`pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W`[src]

Bit 11 - Debug window watchdog stopped when core is halted

`pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W`[src]

Bit 12 - Debug independent watchdog stopped when core is halted

`pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W`[src]

Bit 21 - SMBUS timeout mode stopped when core is halted

`pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W`[src]

Bit 22 - SMBUS timeout mode stopped when core is halted

`impl W<u32, Reg<u32, _APB2_FZ>>`[src]

`pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W`[src]

Bit 2 - TIM counter stopped when core is halted

`pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W`[src]

Bit 3 - TIM counter stopped when core is halted

`pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W`[src]

Bit 4 - TIM counter stopped when core is halted

`impl W<u32, Reg<u32, _ACTRL>>`[src]

`pub fn disfold(&mut self) -> DISFOLD_W`[src]

Bit 2 - DISFOLD

`pub fn fpexcodis(&mut self) -> FPEXCODIS_W`[src]

Bit 10 - FPEXCODIS

`pub fn disramode(&mut self) -> DISRAMODE_W`[src]

Bit 11 - DISRAMODE

`pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W`[src]

Bit 12 - DISITMATBFLUSH

`impl W<u32, Reg<u32, _STIR>>`[src]

`pub fn intid(&mut self) -> INTID_W`[src]

Bits 0:8 - Software generated interrupt ID

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Counter enable

`pub fn tickint(&mut self) -> TICKINT_W`[src]

Bit 1 - SysTick exception request enable

`pub fn clksource(&mut self) -> CLKSOURCE_W`[src]

Bit 2 - Clock source selection

`pub fn countflag(&mut self) -> COUNTFLAG_W`[src]

Bit 16 - COUNTFLAG

`impl W<u32, Reg<u32, _LOAD_>>`[src]

`pub fn reload(&mut self) -> RELOAD_W`[src]

Bits 0:23 - RELOAD value

`impl W<u32, Reg<u32, _VAL>>`[src]

`pub fn current(&mut self) -> CURRENT_W`[src]

Bits 0:23 - Current counter value

`impl W<u32, Reg<u32, _CALIB>>`[src]

`pub fn tenms(&mut self) -> TENMS_W`[src]

Bits 0:23 - Calibration value

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaouten(&mut self) -> DMAOUTEN_W`[src]

Bit 12 - Enable DMA management of data output phase

`pub fn dmainen(&mut self) -> DMAINEN_W`[src]

Bit 11 - Enable DMA management of data input phase

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 10 - Error interrupt enable

`pub fn ccfie(&mut self) -> CCFIE_W`[src]

Bit 9 - CCF flag interrupt enable

`pub fn errc(&mut self) -> ERRC_W`[src]

Bit 8 - Error clear

`pub fn ccfc(&mut self) -> CCFC_W`[src]

Bit 7 - Computation Complete Flag Clear

`pub fn chmod(&mut self) -> CHMOD_W`[src]

Bits 5:6 - AES chaining mode

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 3:4 - AES operating mode

`pub fn datatype(&mut self) -> DATATYPE_W`[src]

Bits 1:2 - Data type selection

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - AES enable

`impl W<u32, Reg<u32, _DINR>>`[src]

`pub fn dinr(&mut self) -> DINR_W`[src]

Bits 0:31 - Data input

`impl W<u32, Reg<u32, _KEYR0>>`[src]

`pub fn keyr0(&mut self) -> KEYR0_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR1>>`[src]

`pub fn keyr1(&mut self) -> KEYR1_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR2>>`[src]

`pub fn keyr2(&mut self) -> KEYR2_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _KEYR3>>`[src]

`pub fn keyr3(&mut self) -> KEYR3_W`[src]

Bits 0:31 - AES key

`impl W<u32, Reg<u32, _IVR0>>`[src]

`pub fn ivr0(&mut self) -> IVR0_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR1>>`[src]

`pub fn ivr1(&mut self) -> IVR1_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR2>>`[src]

`pub fn ivr2(&mut self) -> IVR2_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _IVR3>>`[src]

`pub fn ivr3(&mut self) -> IVR3_W`[src]

Bits 0:31 - Initialization Vector Register

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn tsusp(&mut self) -> TSUSP_W`[src]

Bit 31 - Suspend Timer Mode

`pub fn caie(&mut self) -> CAIE_W`[src]

Bit 29 - Channel Acquisition Interrupt Enable / Clear

`pub fn rch13(&mut self) -> RCH13_W`[src]

Bit 28 - Select GPIO port PC3 as re-routed ADC input channel CH13.

`pub fn fch8(&mut self) -> FCH8_W`[src]

Bit 27 - Select GPIO port PB0 as fast ADC input channel CH8.

`pub fn fch3(&mut self) -> FCH3_W`[src]

Bit 26 - Select GPIO port PA3 as fast ADC input channel CH3.

`pub fn outsel(&mut self) -> OUTSEL_W`[src]

Bits 21:23 - Comparator 2 output selection

`pub fn insel(&mut self) -> INSEL_W`[src]

Bits 18:20 - Inverted input selection

`pub fn wndwe(&mut self) -> WNDWE_W`[src]

Bit 17 - Window mode enable

`pub fn vrefouten(&mut self) -> VREFOUTEN_W`[src]

Bit 16 - VREFINT output enable

`pub fn speed(&mut self) -> SPEED_W`[src]

Bit 12 - Comparator 2 speed mode

`pub fn sw1(&mut self) -> SW1_W`[src]

Bit 5 - SW1 analog switch enable

`pub fn cmp1en(&mut self) -> CMP1EN_W`[src]

Bit 4 - Comparator 1 enable

`pub fn pd400k(&mut self) -> PD400K_W`[src]

Bit 3 - 400 kO pull-down resistor

`pub fn pd10k(&mut self) -> PD10K_W`[src]

Bit 2 - 10 kO pull-down resistor

`pub fn pu400k(&mut self) -> PU400K_W`[src]

Bit 1 - 400 kO pull-up resistor

`pub fn pu10k(&mut self) -> PU10K_W`[src]

Bit 0 - 10 kO pull-up resistor

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:31 - Data Register

`impl W<u32, Reg<u32, _IDR>>`[src]

`pub fn idr(&mut self) -> IDR_W`[src]

Bits 0:6 - Independent data register

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 0 - RESET

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W`[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

`pub fn dmaen2(&mut self) -> DMAEN2_W`[src]

Bit 28 - DAC channel2 DMA enable

`pub fn mamp2(&mut self) -> MAMP2_W`[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

`pub fn wave2(&mut self) -> WAVE2_W`[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

`pub fn tsel2(&mut self) -> TSEL2_W`[src]

Bits 19:21 - DAC channel2 trigger selection

`pub fn ten2(&mut self) -> TEN2_W`[src]

Bit 18 - DAC channel2 trigger enable

`pub fn boff2(&mut self) -> BOFF2_W`[src]

Bit 17 - DAC channel2 output buffer disable

`pub fn en2(&mut self) -> EN2_W`[src]

Bit 16 - DAC channel2 enable

`pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W`[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

`pub fn dmaen1(&mut self) -> DMAEN1_W`[src]

Bit 12 - DAC channel1 DMA enable

`pub fn mamp1(&mut self) -> MAMP1_W`[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

`pub fn wave1(&mut self) -> WAVE1_W`[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

`pub fn tsel1(&mut self) -> TSEL1_W`[src]

Bits 3:5 - DAC channel1 trigger selection

`pub fn ten1(&mut self) -> TEN1_W`[src]

Bit 2 - DAC channel1 trigger enable

`pub fn boff1(&mut self) -> BOFF1_W`[src]

Bit 1 - DAC channel1 output buffer disable

`pub fn en1(&mut self) -> EN1_W`[src]

Bit 0 - DAC channel1 enable

`impl W<u32, Reg<u32, _SWTRIGR>>`[src]

`pub fn swtrig2(&mut self) -> SWTRIG2_W`[src]

Bit 1 - DAC channel2 software trigger

`pub fn swtrig1(&mut self) -> SWTRIG1_W`[src]

Bit 0 - DAC channel1 software trigger

`impl W<u32, Reg<u32, _DHR12R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12L1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12R2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12L2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8R2>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12RD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl W<u32, Reg<u32, _DHR12LD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl W<u32, Reg<u32, _DHR8RD>>`[src]

`pub fn dacc2dhr(&mut self) -> DACC2DHR_W`[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn dmaudr2(&mut self) -> DMAUDR2_W`[src]

Bit 29 - DAC channel2 DMA underrun flag

`pub fn dmaudr1(&mut self) -> DMAUDR1_W`[src]

Bit 13 - DAC channel1 DMA underrun flag

`impl W<u32, Reg<u32, _IFCR>>`[src]

`pub fn cteif7(&mut self) -> CTEIF7_W`[src]

Bit 27 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif7(&mut self) -> CHTIF7_W`[src]

Bit 26 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif7(&mut self) -> CTCIF7_W`[src]

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif7(&mut self) -> CGIF7_W`[src]

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif6(&mut self) -> CTEIF6_W`[src]

Bit 23 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif6(&mut self) -> CHTIF6_W`[src]

Bit 22 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif6(&mut self) -> CTCIF6_W`[src]

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif6(&mut self) -> CGIF6_W`[src]

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif5(&mut self) -> CTEIF5_W`[src]

Bit 19 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif5(&mut self) -> CHTIF5_W`[src]

Bit 18 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif5(&mut self) -> CTCIF5_W`[src]

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif5(&mut self) -> CGIF5_W`[src]

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif4(&mut self) -> CTEIF4_W`[src]

Bit 15 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif4(&mut self) -> CHTIF4_W`[src]

Bit 14 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif4(&mut self) -> CTCIF4_W`[src]

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif4(&mut self) -> CGIF4_W`[src]

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif3(&mut self) -> CTEIF3_W`[src]

Bit 11 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif3(&mut self) -> CHTIF3_W`[src]

Bit 10 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif3(&mut self) -> CTCIF3_W`[src]

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif3(&mut self) -> CGIF3_W`[src]

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif2(&mut self) -> CTEIF2_W`[src]

Bit 7 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif2(&mut self) -> CHTIF2_W`[src]

Bit 6 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif2(&mut self) -> CTCIF2_W`[src]

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif2(&mut self) -> CGIF2_W`[src]

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

`pub fn cteif1(&mut self) -> CTEIF1_W`[src]

Bit 3 - Channel x transfer error clear (x = 1 ..7)

`pub fn chtif1(&mut self) -> CHTIF1_W`[src]

Bit 2 - Channel x half transfer clear (x = 1 ..7)

`pub fn ctcif1(&mut self) -> CTCIF1_W`[src]

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

`pub fn cgif1(&mut self) -> CGIF1_W`[src]

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

`impl W<u32, Reg<u32, _CCR1>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR1>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR1>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR1>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR2>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR2>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR2>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR2>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR3>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR3>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR3>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR3>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR4>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR4>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR4>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR4>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR5>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR5>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR5>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR5>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR6>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR6>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR6>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR6>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _CCR7>>`[src]

`pub fn mem2mem(&mut self) -> MEM2MEM_W`[src]

Bit 14 - Memory to memory mode

`pub fn pl(&mut self) -> PL_W`[src]

Bits 12:13 - Channel priority level

`pub fn msize(&mut self) -> MSIZE_W`[src]

Bits 10:11 - Memory size

`pub fn psize(&mut self) -> PSIZE_W`[src]

Bits 8:9 - Peripheral size

`pub fn minc(&mut self) -> MINC_W`[src]

Bit 7 - Memory increment mode

`pub fn pinc(&mut self) -> PINC_W`[src]

Bit 6 - Peripheral increment mode

`pub fn circ(&mut self) -> CIRC_W`[src]

Bit 5 - Circular mode

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Data transfer direction

`pub fn teie(&mut self) -> TEIE_W`[src]

Bit 3 - Transfer error interrupt enable

`pub fn htie(&mut self) -> HTIE_W`[src]

Bit 2 - Half transfer interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 1 - Transfer complete interrupt enable

`pub fn en(&mut self) -> EN_W`[src]

Bit 0 - Channel enable

`impl W<u32, Reg<u32, _CNDTR7>>`[src]

`pub fn ndt(&mut self) -> NDT_W`[src]

Bits 0:15 - Number of data to transfer

`impl W<u32, Reg<u32, _CPAR7>>`[src]

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:31 - Peripheral address

`impl W<u32, Reg<u32, _CMAR7>>`[src]

`pub fn ma(&mut self) -> MA_W`[src]

Bits 0:31 - Memory address

`impl W<u32, Reg<u32, _IMR>>`[src]

`pub fn mr0(&mut self) -> MR0_W`[src]

Bit 0 - Interrupt mask on line x

`pub fn mr1(&mut self) -> MR1_W`[src]

Bit 1 - Interrupt mask on line x

`pub fn mr2(&mut self) -> MR2_W`[src]

Bit 2 - Interrupt mask on line x

`pub fn mr3(&mut self) -> MR3_W`[src]

Bit 3 - Interrupt mask on line x

`pub fn mr4(&mut self) -> MR4_W`[src]

Bit 4 - Interrupt mask on line x

`pub fn mr5(&mut self) -> MR5_W`[src]

Bit 5 - Interrupt mask on line x

`pub fn mr6(&mut self) -> MR6_W`[src]

Bit 6 - Interrupt mask on line x

`pub fn mr7(&mut self) -> MR7_W`[src]

Bit 7 - Interrupt mask on line x

`pub fn mr8(&mut self) -> MR8_W`[src]

Bit 8 - Interrupt mask on line x

`pub fn mr9(&mut self) -> MR9_W`[src]

Bit 9 - Interrupt mask on line x

`pub fn mr10(&mut self) -> MR10_W`[src]

Bit 10 - Interrupt mask on line x

`pub fn mr11(&mut self) -> MR11_W`[src]

Bit 11 - Interrupt mask on line x

`pub fn mr12(&mut self) -> MR12_W`[src]

Bit 12 - Interrupt mask on line x

`pub fn mr13(&mut self) -> MR13_W`[src]

Bit 13 - Interrupt mask on line x

`pub fn mr14(&mut self) -> MR14_W`[src]

Bit 14 - Interrupt mask on line x

`pub fn mr15(&mut self) -> MR15_W`[src]

Bit 15 - Interrupt mask on line x

`pub fn mr16(&mut self) -> MR16_W`[src]

Bit 16 - Interrupt mask on line x

`pub fn mr17(&mut self) -> MR17_W`[src]

Bit 17 - Interrupt mask on line x

`pub fn mr18(&mut self) -> MR18_W`[src]

Bit 18 - Interrupt mask on line x

`pub fn mr19(&mut self) -> MR19_W`[src]

Bit 19 - Interrupt mask on line x

`pub fn mr20(&mut self) -> MR20_W`[src]

Bit 20 - Interrupt mask on line x

`pub fn mr21(&mut self) -> MR21_W`[src]

Bit 21 - Interrupt mask on line x

`pub fn mr22(&mut self) -> MR22_W`[src]

Bit 22 - Interrupt mask on line x

`impl W<u32, Reg<u32, _EMR>>`[src]

`pub fn mr0(&mut self) -> MR0_W`[src]

Bit 0 - Event mask on line x

`pub fn mr1(&mut self) -> MR1_W`[src]

Bit 1 - Event mask on line x

`pub fn mr2(&mut self) -> MR2_W`[src]

Bit 2 - Event mask on line x

`pub fn mr3(&mut self) -> MR3_W`[src]

Bit 3 - Event mask on line x

`pub fn mr4(&mut self) -> MR4_W`[src]

Bit 4 - Event mask on line x

`pub fn mr5(&mut self) -> MR5_W`[src]

Bit 5 - Event mask on line x

`pub fn mr6(&mut self) -> MR6_W`[src]

Bit 6 - Event mask on line x

`pub fn mr7(&mut self) -> MR7_W`[src]

Bit 7 - Event mask on line x

`pub fn mr8(&mut self) -> MR8_W`[src]

Bit 8 - Event mask on line x

`pub fn mr9(&mut self) -> MR9_W`[src]

Bit 9 - Event mask on line x

`pub fn mr10(&mut self) -> MR10_W`[src]

Bit 10 - Event mask on line x

`pub fn mr11(&mut self) -> MR11_W`[src]

Bit 11 - Event mask on line x

`pub fn mr12(&mut self) -> MR12_W`[src]

Bit 12 - Event mask on line x

`pub fn mr13(&mut self) -> MR13_W`[src]

Bit 13 - Event mask on line x

`pub fn mr14(&mut self) -> MR14_W`[src]

Bit 14 - Event mask on line x

`pub fn mr15(&mut self) -> MR15_W`[src]

Bit 15 - Event mask on line x

`pub fn mr16(&mut self) -> MR16_W`[src]

Bit 16 - Event mask on line x

`pub fn mr17(&mut self) -> MR17_W`[src]

Bit 17 - Event mask on line x

`pub fn mr18(&mut self) -> MR18_W`[src]

Bit 18 - Event mask on line x

`pub fn mr19(&mut self) -> MR19_W`[src]

Bit 19 - Event mask on line x

`pub fn mr20(&mut self) -> MR20_W`[src]

Bit 20 - Event mask on line x

`pub fn mr21(&mut self) -> MR21_W`[src]

Bit 21 - Event mask on line x

`pub fn mr22(&mut self) -> MR22_W`[src]

Bit 22 - Event mask on line x

`impl W<u32, Reg<u32, _RTSR>>`[src]

`pub fn tr0(&mut self) -> TR0_W`[src]

Bit 0 - Rising edge trigger event configuration bit of line x

`pub fn tr1(&mut self) -> TR1_W`[src]

Bit 1 - Rising edge trigger event configuration bit of line x

`pub fn tr2(&mut self) -> TR2_W`[src]

Bit 2 - Rising edge trigger event configuration bit of line x

`pub fn tr3(&mut self) -> TR3_W`[src]

Bit 3 - Rising edge trigger event configuration bit of line x

`pub fn tr4(&mut self) -> TR4_W`[src]

Bit 4 - Rising edge trigger event configuration bit of line x

`pub fn tr5(&mut self) -> TR5_W`[src]

Bit 5 - Rising edge trigger event configuration bit of line x

`pub fn tr6(&mut self) -> TR6_W`[src]

Bit 6 - Rising edge trigger event configuration bit of line x

`pub fn tr7(&mut self) -> TR7_W`[src]

Bit 7 - Rising edge trigger event configuration bit of line x

`pub fn tr8(&mut self) -> TR8_W`[src]

Bit 8 - Rising edge trigger event configuration bit of line x

`pub fn tr9(&mut self) -> TR9_W`[src]

Bit 9 - Rising edge trigger event configuration bit of line x

`pub fn tr10(&mut self) -> TR10_W`[src]

Bit 10 - Rising edge trigger event configuration bit of line x

`pub fn tr11(&mut self) -> TR11_W`[src]

Bit 11 - Rising edge trigger event configuration bit of line x

`pub fn tr12(&mut self) -> TR12_W`[src]

Bit 12 - Rising edge trigger event configuration bit of line x

`pub fn tr13(&mut self) -> TR13_W`[src]

Bit 13 - Rising edge trigger event configuration bit of line x

`pub fn tr14(&mut self) -> TR14_W`[src]

Bit 14 - Rising edge trigger event configuration bit of line x

`pub fn tr15(&mut self) -> TR15_W`[src]

Bit 15 - Rising edge trigger event configuration bit of line x

`pub fn tr16(&mut self) -> TR16_W`[src]

Bit 16 - Rising edge trigger event configuration bit of line x

`pub fn tr17(&mut self) -> TR17_W`[src]

Bit 17 - Rising edge trigger event configuration bit of line x

`pub fn tr18(&mut self) -> TR18_W`[src]

Bit 18 - Rising edge trigger event configuration bit of line x

`pub fn tr19(&mut self) -> TR19_W`[src]

Bit 19 - Rising edge trigger event configuration bit of line x

`pub fn tr20(&mut self) -> TR20_W`[src]

Bit 20 - Rising edge trigger event configuration bit of line x

`pub fn tr21(&mut self) -> TR21_W`[src]

Bit 21 - Rising edge trigger event configuration bit of line x

`pub fn tr22(&mut self) -> TR22_W`[src]

Bit 22 - Rising edge trigger event configuration bit of line x

`impl W<u32, Reg<u32, _FTSR>>`[src]

`pub fn tr0(&mut self) -> TR0_W`[src]

Bit 0 - Falling edge trigger event configuration bit of line x

`pub fn tr1(&mut self) -> TR1_W`[src]

Bit 1 - Falling edge trigger event configuration bit of line x

`pub fn tr2(&mut self) -> TR2_W`[src]

Bit 2 - Falling edge trigger event configuration bit of line x

`pub fn tr3(&mut self) -> TR3_W`[src]

Bit 3 - Falling edge trigger event configuration bit of line x

`pub fn tr4(&mut self) -> TR4_W`[src]

Bit 4 - Falling edge trigger event configuration bit of line x

`pub fn tr5(&mut self) -> TR5_W`[src]

Bit 5 - Falling edge trigger event configuration bit of line x

`pub fn tr6(&mut self) -> TR6_W`[src]

Bit 6 - Falling edge trigger event configuration bit of line x

`pub fn tr7(&mut self) -> TR7_W`[src]

Bit 7 - Falling edge trigger event configuration bit of line x

`pub fn tr8(&mut self) -> TR8_W`[src]

Bit 8 - Falling edge trigger event configuration bit of line x

`pub fn tr9(&mut self) -> TR9_W`[src]

Bit 9 - Falling edge trigger event configuration bit of line x

`pub fn tr10(&mut self) -> TR10_W`[src]

Bit 10 - Falling edge trigger event configuration bit of line x

`pub fn tr11(&mut self) -> TR11_W`[src]

Bit 11 - Falling edge trigger event configuration bit of line x

`pub fn tr12(&mut self) -> TR12_W`[src]

Bit 12 - Falling edge trigger event configuration bit of line x

`pub fn tr13(&mut self) -> TR13_W`[src]

Bit 13 - Falling edge trigger event configuration bit of line x

`pub fn tr14(&mut self) -> TR14_W`[src]

Bit 14 - Falling edge trigger event configuration bit of line x

`pub fn tr15(&mut self) -> TR15_W`[src]

Bit 15 - Falling edge trigger event configuration bit of line x

`pub fn tr16(&mut self) -> TR16_W`[src]

Bit 16 - Falling edge trigger event configuration bit of line x

`pub fn tr17(&mut self) -> TR17_W`[src]

Bit 17 - Falling edge trigger event configuration bit of line x

`pub fn tr18(&mut self) -> TR18_W`[src]

Bit 18 - Falling edge trigger event configuration bit of line x

`pub fn tr19(&mut self) -> TR19_W`[src]

Bit 19 - Falling edge trigger event configuration bit of line x

`pub fn tr20(&mut self) -> TR20_W`[src]

Bit 20 - Falling edge trigger event configuration bit of line x

`pub fn tr21(&mut self) -> TR21_W`[src]

Bit 21 - Falling edge trigger event configuration bit of line x

`pub fn tr22(&mut self) -> TR22_W`[src]

Bit 22 - Falling edge trigger event configuration bit of line x

`impl W<u32, Reg<u32, _SWIER>>`[src]

`pub fn swier0(&mut self) -> SWIER0_W`[src]

Bit 0 - Software interrupt on line x

`pub fn swier1(&mut self) -> SWIER1_W`[src]

Bit 1 - Software interrupt on line x

`pub fn swier2(&mut self) -> SWIER2_W`[src]

Bit 2 - Software interrupt on line x

`pub fn swier3(&mut self) -> SWIER3_W`[src]

Bit 3 - Software interrupt on line x

`pub fn swier4(&mut self) -> SWIER4_W`[src]

Bit 4 - Software interrupt on line x

`pub fn swier5(&mut self) -> SWIER5_W`[src]

Bit 5 - Software interrupt on line x

`pub fn swier6(&mut self) -> SWIER6_W`[src]

Bit 6 - Software interrupt on line x

`pub fn swier7(&mut self) -> SWIER7_W`[src]

Bit 7 - Software interrupt on line x

`pub fn swier8(&mut self) -> SWIER8_W`[src]

Bit 8 - Software interrupt on line x

`pub fn swier9(&mut self) -> SWIER9_W`[src]

Bit 9 - Software interrupt on line x

`pub fn swier10(&mut self) -> SWIER10_W`[src]

Bit 10 - Software interrupt on line x

`pub fn swier11(&mut self) -> SWIER11_W`[src]

Bit 11 - Software interrupt on line x

`pub fn swier12(&mut self) -> SWIER12_W`[src]

Bit 12 - Software interrupt on line x

`pub fn swier13(&mut self) -> SWIER13_W`[src]

Bit 13 - Software interrupt on line x

`pub fn swier14(&mut self) -> SWIER14_W`[src]

Bit 14 - Software interrupt on line x

`pub fn swier15(&mut self) -> SWIER15_W`[src]

Bit 15 - Software interrupt on line x

`pub fn swier16(&mut self) -> SWIER16_W`[src]

Bit 16 - Software interrupt on line x

`pub fn swier17(&mut self) -> SWIER17_W`[src]

Bit 17 - Software interrupt on line x

`pub fn swier18(&mut self) -> SWIER18_W`[src]

Bit 18 - Software interrupt on line x

`pub fn swier19(&mut self) -> SWIER19_W`[src]

Bit 19 - Software interrupt on line x

`pub fn swier20(&mut self) -> SWIER20_W`[src]

Bit 20 - Software interrupt on line x

`pub fn swier21(&mut self) -> SWIER21_W`[src]

Bit 21 - Software interrupt on line x

`pub fn swier22(&mut self) -> SWIER22_W`[src]

Bit 22 - Software interrupt on line x

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn pr0(&mut self) -> PR0_W`[src]

Bit 0 - Pending bit

`pub fn pr1(&mut self) -> PR1_W`[src]

Bit 1 - Pending bit

`pub fn pr2(&mut self) -> PR2_W`[src]

Bit 2 - Pending bit

`pub fn pr3(&mut self) -> PR3_W`[src]

Bit 3 - Pending bit

`pub fn pr4(&mut self) -> PR4_W`[src]

Bit 4 - Pending bit

`pub fn pr5(&mut self) -> PR5_W`[src]

Bit 5 - Pending bit

`pub fn pr6(&mut self) -> PR6_W`[src]

Bit 6 - Pending bit

`pub fn pr7(&mut self) -> PR7_W`[src]

Bit 7 - Pending bit

`pub fn pr8(&mut self) -> PR8_W`[src]

Bit 8 - Pending bit

`pub fn pr9(&mut self) -> PR9_W`[src]

Bit 9 - Pending bit

`pub fn pr10(&mut self) -> PR10_W`[src]

Bit 10 - Pending bit

`pub fn pr11(&mut self) -> PR11_W`[src]

Bit 11 - Pending bit

`pub fn pr12(&mut self) -> PR12_W`[src]

Bit 12 - Pending bit

`pub fn pr13(&mut self) -> PR13_W`[src]

Bit 13 - Pending bit

`pub fn pr14(&mut self) -> PR14_W`[src]

Bit 14 - Pending bit

`pub fn pr15(&mut self) -> PR15_W`[src]

Bit 15 - Pending bit

`pub fn pr16(&mut self) -> PR16_W`[src]

Bit 16 - Pending bit

`pub fn pr17(&mut self) -> PR17_W`[src]

Bit 17 - Pending bit

`pub fn pr18(&mut self) -> PR18_W`[src]

Bit 18 - Pending bit

`pub fn pr19(&mut self) -> PR19_W`[src]

Bit 19 - Pending bit

`pub fn pr20(&mut self) -> PR20_W`[src]

Bit 20 - Pending bit

`pub fn pr21(&mut self) -> PR21_W`[src]

Bit 21 - Pending bit

`pub fn pr22(&mut self) -> PR22_W`[src]

Bit 22 - Pending bit

`impl W<u32, Reg<u32, _ACR>>`[src]

`pub fn latency(&mut self) -> LATENCY_W`[src]

Bit 0 - Latency

`pub fn prften(&mut self) -> PRFTEN_W`[src]

Bit 1 - Prefetch enable

`pub fn acc64(&mut self) -> ACC64_W`[src]

Bit 2 - 64-bit access

`pub fn sleep_pd(&mut self) -> SLEEP_PD_W`[src]

Bit 3 - Flash mode during Sleep

`pub fn run_pd(&mut self) -> RUN_PD_W`[src]

Bit 4 - Flash mode during Run

`impl W<u32, Reg<u32, _PECR>>`[src]

`pub fn pelock(&mut self) -> PELOCK_W`[src]

Bit 0 - FLASH_PECR and data EEPROM lock

`pub fn prglock(&mut self) -> PRGLOCK_W`[src]

Bit 1 - Program memory lock

`pub fn optlock(&mut self) -> OPTLOCK_W`[src]

Bit 2 - Option bytes block lock

`pub fn prog(&mut self) -> PROG_W`[src]

Bit 3 - Program memory selection

`pub fn data(&mut self) -> DATA_W`[src]

Bit 4 - Data EEPROM selection

`pub fn ftdw(&mut self) -> FTDW_W`[src]

Bit 8 - Fixed time data write for Byte, Half Word and Word programming

`pub fn erase(&mut self) -> ERASE_W`[src]

Bit 9 - Page or Double Word erase mode

`pub fn fprg(&mut self) -> FPRG_W`[src]

Bit 10 - Half Page/Double Word programming mode

`pub fn parallelbank(&mut self) -> PARALLELBANK_W`[src]

Bit 15 - Parallel bank mode

`pub fn eopie(&mut self) -> EOPIE_W`[src]

Bit 16 - End of programming interrupt enable

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 17 - Error interrupt enable

`pub fn obl_launch(&mut self) -> OBL_LAUNCH_W`[src]

Bit 18 - Launch the option byte loading

`impl W<u32, Reg<u32, _PDKEYR>>`[src]

`pub fn pdkeyr(&mut self) -> PDKEYR_W`[src]

Bits 0:31 - RUN_PD in FLASH_ACR key

`impl W<u32, Reg<u32, _PEKEYR>>`[src]

`pub fn pekeyr(&mut self) -> PEKEYR_W`[src]

Bits 0:31 - FLASH_PEC and data EEPROM key

`impl W<u32, Reg<u32, _PRGKEYR>>`[src]

`pub fn prgkeyr(&mut self) -> PRGKEYR_W`[src]

Bits 0:31 - Program memory key

`impl W<u32, Reg<u32, _OPTKEYR>>`[src]

`pub fn optkeyr(&mut self) -> OPTKEYR_W`[src]

Bits 0:31 - Option byte key

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn wrperr(&mut self) -> WRPERR_W`[src]

Bit 8 - Write protected error

`pub fn pgaerr(&mut self) -> PGAERR_W`[src]

Bit 9 - Programming alignment error

`pub fn sizerr(&mut self) -> SIZERR_W`[src]

Bit 10 - Size error

`pub fn optverr(&mut self) -> OPTVERR_W`[src]

Bit 11 - Option validity error

`pub fn optverrusr(&mut self) -> OPTVERRUSR_W`[src]

Bit 12 - Option UserValidity Error

`impl W<u32, Reg<u32, _WRPR1>>`[src]

`pub fn wrp1(&mut self) -> WRP1_W`[src]

Bits 0:31 - Write protection

`impl W<u32, Reg<u32, _WRPR2>>`[src]

`pub fn wrp2(&mut self) -> WRP2_W`[src]

Bits 0:31 - WRP2

`impl W<u32, Reg<u32, _WRPR3>>`[src]

`pub fn wrp3(&mut self) -> WRP3_W`[src]

Bits 0:31 - WRP3

`impl W<u32, Reg<u32, _BCR1>>`[src]

`pub fn cburstrw(&mut self) -> CBURSTRW_W`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&mut self) -> ASYNCWAIT_W`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&mut self) -> EXTMOD_W`[src]

Bit 14 - EXTMOD

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 13 - WAITEN

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 12 - WREN

`pub fn waitcfg(&mut self) -> WAITCFG_W`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&mut self) -> WRAPMOD_W`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&mut self) -> WAITPOL_W`[src]

Bit 9 - WAITPOL

`pub fn bursten(&mut self) -> BURSTEN_W`[src]

Bit 8 - BURSTEN

`pub fn faccen(&mut self) -> FACCEN_W`[src]

Bit 6 - FACCEN

`pub fn mwid(&mut self) -> MWID_W`[src]

Bits 4:5 - MWID

`pub fn mtyp(&mut self) -> MTYP_W`[src]

Bits 2:3 - MTYP

`pub fn muxen(&mut self) -> MUXEN_W`[src]

Bit 1 - MUXEN

`pub fn mbken(&mut self) -> MBKEN_W`[src]

Bit 0 - MBKEN

`pub fn cpsize(&mut self) -> CPSIZE_W`[src]

Bits 16:18 - CRAM page size

`impl W<u32, Reg<u32, _BTR>>`[src]

`pub fn accmod(&mut self) -> ACCMOD_W`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&mut self) -> DATLAT_W`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 20:23 - CLKDIV

`pub fn busturn(&mut self) -> BUSTURN_W`[src]

Bits 16:19 - BUSTURN

`pub fn datast(&mut self) -> DATAST_W`[src]

Bits 8:15 - DATAST

`pub fn addhld(&mut self) -> ADDHLD_W`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&mut self) -> ADDSET_W`[src]

Bits 0:3 - ADDSET

`impl W<u32, Reg<u32, _BCR>>`[src]

`pub fn cburstrw(&mut self) -> CBURSTRW_W`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&mut self) -> ASYNCWAIT_W`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&mut self) -> EXTMOD_W`[src]

Bit 14 - EXTMOD

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 13 - WAITEN

`pub fn wren(&mut self) -> WREN_W`[src]

Bit 12 - WREN

`pub fn waitcfg(&mut self) -> WAITCFG_W`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&mut self) -> WRAPMOD_W`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&mut self) -> WAITPOL_W`[src]

Bit 9 - WAITPOL

`pub fn bursten(&mut self) -> BURSTEN_W`[src]

Bit 8 - BURSTEN

`pub fn faccen(&mut self) -> FACCEN_W`[src]

Bit 6 - FACCEN

`pub fn mwid(&mut self) -> MWID_W`[src]

Bits 4:5 - MWID

`pub fn mtyp(&mut self) -> MTYP_W`[src]

Bits 2:3 - MTYP

`pub fn muxen(&mut self) -> MUXEN_W`[src]

Bit 1 - MUXEN

`pub fn mbken(&mut self) -> MBKEN_W`[src]

Bit 0 - MBKEN

`pub fn cpsize(&mut self) -> CPSIZE_W`[src]

Bits 16:18 - CRAM page size

`impl W<u32, Reg<u32, _BWTR>>`[src]

`pub fn accmod(&mut self) -> ACCMOD_W`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&mut self) -> DATLAT_W`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 20:23 - CLKDIV

`pub fn datast(&mut self) -> DATAST_W`[src]

Bits 8:15 - DATAST

`pub fn addhld(&mut self) -> ADDHLD_W`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&mut self) -> ADDSET_W`[src]

Bits 0:3 - ADDSET

`pub fn busturn(&mut self) -> BUSTURN_W`[src]

Bits 16:19 - Bus turnaround phase duration

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&mut self) -> MODER15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&mut self) -> MODER14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&mut self) -> MODER13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&mut self) -> MODER12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&mut self) -> MODER11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&mut self) -> MODER10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&mut self) -> MODER9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&mut self) -> MODER8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&mut self) -> MODER7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&mut self) -> MODER6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&mut self) -> MODER5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&mut self) -> MODER4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&mut self) -> MODER3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&mut self) -> MODER2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&mut self) -> MODER1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&mut self) -> MODER0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&mut self) -> OT15_W`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&mut self) -> OT14_W`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&mut self) -> OT13_W`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&mut self) -> OT12_W`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&mut self) -> OT11_W`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&mut self) -> OT10_W`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&mut self) -> OT9_W`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&mut self) -> OT8_W`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&mut self) -> OT7_W`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&mut self) -> OT6_W`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&mut self) -> OT5_W`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&mut self) -> OT4_W`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&mut self) -> OT3_W`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&mut self) -> OT2_W`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&mut self) -> OT1_W`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&mut self) -> OT0_W`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&mut self) -> OSPEEDR15_W`[src]

Bits 30:31 - OSPEEDR15

`pub fn ospeedr14(&mut self) -> OSPEEDR14_W`[src]

Bits 28:29 - OSPEEDR14

`pub fn ospeedr13(&mut self) -> OSPEEDR13_W`[src]

Bits 26:27 - OSPEEDR13

`pub fn ospeedr12(&mut self) -> OSPEEDR12_W`[src]

Bits 24:25 - OSPEEDR12

`pub fn ospeedr11(&mut self) -> OSPEEDR11_W`[src]

Bits 22:23 - OSPEEDR11

`pub fn ospeedr10(&mut self) -> OSPEEDR10_W`[src]

Bits 20:21 - OSPEEDR10

`pub fn ospeedr9(&mut self) -> OSPEEDR9_W`[src]

Bits 18:19 - OSPEEDR9

`pub fn ospeedr8(&mut self) -> OSPEEDR8_W`[src]

Bits 16:17 - OSPEEDR8

`pub fn ospeedr7(&mut self) -> OSPEEDR7_W`[src]

Bits 14:15 - OSPEEDR7

`pub fn ospeedr6(&mut self) -> OSPEEDR6_W`[src]

Bits 12:13 - OSPEEDR6

`pub fn ospeedr5(&mut self) -> OSPEEDR5_W`[src]

Bits 10:11 - OSPEEDR5

`pub fn ospeedr4(&mut self) -> OSPEEDR4_W`[src]

Bits 8:9 - OSPEEDR4

`pub fn ospeedr3(&mut self) -> OSPEEDR3_W`[src]

Bits 6:7 - OSPEEDR3

`pub fn ospeedr2(&mut self) -> OSPEEDR2_W`[src]

Bits 4:5 - OSPEEDR2

`pub fn ospeedr1(&mut self) -> OSPEEDR1_W`[src]

Bits 2:3 - OSPEEDR1

`pub fn ospeedr0(&mut self) -> OSPEEDR0_W`[src]

Bits 0:1 - OSPEEDR0

`impl W<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&mut self) -> PUPDR15_W`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&mut self) -> PUPDR14_W`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&mut self) -> PUPDR13_W`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&mut self) -> PUPDR12_W`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&mut self) -> PUPDR11_W`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&mut self) -> PUPDR10_W`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&mut self) -> PUPDR9_W`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&mut self) -> PUPDR8_W`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&mut self) -> PUPDR7_W`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&mut self) -> PUPDR6_W`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&mut self) -> PUPDR5_W`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&mut self) -> PUPDR4_W`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&mut self) -> PUPDR3_W`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&mut self) -> PUPDR2_W`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&mut self) -> PUPDR1_W`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&mut self) -> PUPDR0_W`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl W<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&mut self) -> ODR15_W`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&mut self) -> ODR14_W`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&mut self) -> ODR13_W`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&mut self) -> ODR12_W`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&mut self) -> ODR11_W`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&mut self) -> ODR10_W`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&mut self) -> ODR9_W`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&mut self) -> ODR8_W`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&mut self) -> ODR7_W`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&mut self) -> ODR6_W`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&mut self) -> ODR5_W`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&mut self) -> ODR4_W`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&mut self) -> ODR3_W`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&mut self) -> ODR2_W`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&mut self) -> ODR1_W`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&mut self) -> ODR0_W`[src]

Bit 0 - Port output data (y = 0..15)

`impl W<u32, Reg<u32, _BSRR>>`[src]

`pub fn br15(&mut self) -> BR15_W`[src]

Bit 31 - Port x reset bit y (y = 0..15)

`pub fn br14(&mut self) -> BR14_W`[src]

Bit 30 - Port x reset bit y (y = 0..15)

`pub fn br13(&mut self) -> BR13_W`[src]

Bit 29 - Port x reset bit y (y = 0..15)

`pub fn br12(&mut self) -> BR12_W`[src]

Bit 28 - Port x reset bit y (y = 0..15)

`pub fn br11(&mut self) -> BR11_W`[src]

Bit 27 - Port x reset bit y (y = 0..15)

`pub fn br10(&mut self) -> BR10_W`[src]

Bit 26 - Port x reset bit y (y = 0..15)

`pub fn br9(&mut self) -> BR9_W`[src]

Bit 25 - Port x reset bit y (y = 0..15)

`pub fn br8(&mut self) -> BR8_W`[src]

Bit 24 - Port x reset bit y (y = 0..15)

`pub fn br7(&mut self) -> BR7_W`[src]

Bit 23 - Port x reset bit y (y = 0..15)

`pub fn br6(&mut self) -> BR6_W`[src]

Bit 22 - Port x reset bit y (y = 0..15)

`pub fn br5(&mut self) -> BR5_W`[src]

Bit 21 - Port x reset bit y (y = 0..15)

`pub fn br4(&mut self) -> BR4_W`[src]

Bit 20 - Port x reset bit y (y = 0..15)

`pub fn br3(&mut self) -> BR3_W`[src]

Bit 19 - Port x reset bit y (y = 0..15)

`pub fn br2(&mut self) -> BR2_W`[src]

Bit 18 - Port x reset bit y (y = 0..15)

`pub fn br1(&mut self) -> BR1_W`[src]

Bit 17 - Port x reset bit y (y = 0..15)

`pub fn br0(&mut self) -> BR0_W`[src]

Bit 16 - Port x set bit y (y= 0..15)

`pub fn bs15(&mut self) -> BS15_W`[src]

Bit 15 - Port x set bit y (y= 0..15)

`pub fn bs14(&mut self) -> BS14_W`[src]

Bit 14 - Port x set bit y (y= 0..15)

`pub fn bs13(&mut self) -> BS13_W`[src]

Bit 13 - Port x set bit y (y= 0..15)

`pub fn bs12(&mut self) -> BS12_W`[src]

Bit 12 - Port x set bit y (y= 0..15)

`pub fn bs11(&mut self) -> BS11_W`[src]

Bit 11 - Port x set bit y (y= 0..15)

`pub fn bs10(&mut self) -> BS10_W`[src]

Bit 10 - Port x set bit y (y= 0..15)

`pub fn bs9(&mut self) -> BS9_W`[src]

Bit 9 - Port x set bit y (y= 0..15)

`pub fn bs8(&mut self) -> BS8_W`[src]

Bit 8 - Port x set bit y (y= 0..15)

`pub fn bs7(&mut self) -> BS7_W`[src]

Bit 7 - Port x set bit y (y= 0..15)

`pub fn bs6(&mut self) -> BS6_W`[src]

Bit 6 - Port x set bit y (y= 0..15)

`pub fn bs5(&mut self) -> BS5_W`[src]

Bit 5 - Port x set bit y (y= 0..15)

`pub fn bs4(&mut self) -> BS4_W`[src]

Bit 4 - Port x set bit y (y= 0..15)

`pub fn bs3(&mut self) -> BS3_W`[src]

Bit 3 - Port x set bit y (y= 0..15)

`pub fn bs2(&mut self) -> BS2_W`[src]

Bit 2 - Port x set bit y (y= 0..15)

`pub fn bs1(&mut self) -> BS1_W`[src]

Bit 1 - Port x set bit y (y= 0..15)

`pub fn bs0(&mut self) -> BS0_W`[src]

Bit 0 - Port x set bit y (y= 0..15)

`impl W<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&mut self) -> LCKK_W`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&mut self) -> LCK15_W`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&mut self) -> LCK14_W`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&mut self) -> LCK13_W`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&mut self) -> LCK12_W`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&mut self) -> LCK11_W`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&mut self) -> LCK10_W`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&mut self) -> LCK9_W`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&mut self) -> LCK8_W`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&mut self) -> LCK7_W`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&mut self) -> LCK6_W`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&mut self) -> LCK5_W`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&mut self) -> LCK4_W`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&mut self) -> LCK3_W`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&mut self) -> LCK2_W`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&mut self) -> LCK1_W`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&mut self) -> LCK0_W`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl W<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&mut self) -> AFRL7_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&mut self) -> AFRL6_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&mut self) -> AFRL5_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&mut self) -> AFRL4_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&mut self) -> AFRL3_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&mut self) -> AFRL2_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&mut self) -> AFRL1_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&mut self) -> AFRL0_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl W<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&mut self) -> AFRH15_W`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&mut self) -> AFRH14_W`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&mut self) -> AFRH13_W`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&mut self) -> AFRH12_W`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&mut self) -> AFRH11_W`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&mut self) -> AFRH10_W`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&mut self) -> AFRH9_W`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&mut self) -> AFRH8_W`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn swrst(&mut self) -> SWRST_W`[src]

Bit 15 - Software reset

`pub fn alert(&mut self) -> ALERT_W`[src]

Bit 13 - SMBus alert

`pub fn pec(&mut self) -> PEC_W`[src]

Bit 12 - Packet error checking

`pub fn pos(&mut self) -> POS_W`[src]

Bit 11 - Acknowledge/PEC Position (for data reception)

`pub fn ack(&mut self) -> ACK_W`[src]

Bit 10 - Acknowledge enable

`pub fn stop(&mut self) -> STOP_W`[src]

Bit 9 - Stop generation

`pub fn start(&mut self) -> START_W`[src]

Bit 8 - Start generation

`pub fn nostretch(&mut self) -> NOSTRETCH_W`[src]

Bit 7 - Clock stretching disable (Slave mode)

`pub fn engc(&mut self) -> ENGC_W`[src]

Bit 6 - General call enable

`pub fn enpec(&mut self) -> ENPEC_W`[src]

Bit 5 - PEC enable

`pub fn enarp(&mut self) -> ENARP_W`[src]

Bit 4 - ARP enable

`pub fn smbtype(&mut self) -> SMBTYPE_W`[src]

Bit 3 - SMBus type

`pub fn smbus(&mut self) -> SMBUS_W`[src]

Bit 1 - SMBus mode

`pub fn pe(&mut self) -> PE_W`[src]

Bit 0 - Peripheral enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn last(&mut self) -> LAST_W`[src]

Bit 12 - DMA last transfer

`pub fn dmaen(&mut self) -> DMAEN_W`[src]

Bit 11 - DMA requests enable

`pub fn itbufen(&mut self) -> ITBUFEN_W`[src]

Bit 10 - Buffer interrupt enable

`pub fn itevten(&mut self) -> ITEVTEN_W`[src]

Bit 9 - Event interrupt enable

`pub fn iterren(&mut self) -> ITERREN_W`[src]

Bit 8 - Error interrupt enable

`pub fn freq(&mut self) -> FREQ_W`[src]

Bits 0:5 - Peripheral clock frequency

`impl W<u32, Reg<u32, _OAR1>>`[src]

`pub fn addmode(&mut self) -> ADDMODE_W`[src]

Bit 15 - ADDMODE

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:9 - Interface address

`impl W<u32, Reg<u32, _OAR2>>`[src]

`pub fn add2(&mut self) -> ADD2_W`[src]

Bits 1:7 - Interface address

`pub fn endual(&mut self) -> ENDUAL_W`[src]

Bit 0 - Dual addressing mode enable

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:7 - -bit data register

`impl W<u32, Reg<u32, _SR1>>`[src]

`pub fn smbalert(&mut self) -> SMBALERT_W`[src]

Bit 15 - SMBus alert

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 14 - Timeout or Tlow error

`pub fn pecerr(&mut self) -> PECERR_W`[src]

Bit 12 - PEC Error in reception

`pub fn ovr(&mut self) -> OVR_W`[src]

Bit 11 - Overrun/Underrun

`pub fn af(&mut self) -> AF_W`[src]

Bit 10 - Acknowledge failure

`pub fn arlo(&mut self) -> ARLO_W`[src]

Bit 9 - Arbitration lost (master mode)

`pub fn berr(&mut self) -> BERR_W`[src]

Bit 8 - Bus error

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn f_s(&mut self) -> F_S_W`[src]

Bit 15 - I2C master mode selection

`pub fn duty(&mut self) -> DUTY_W`[src]

Bit 14 - Fast mode duty cycle

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)

`impl W<u32, Reg<u32, _TRISE>>`[src]

`pub fn trise(&mut self) -> TRISE_W`[src]

Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)

`impl W<u32, Reg<u32, _KR>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:15 - Key value (write only, read 0000h)

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn pr(&mut self) -> PR_W`[src]

Bits 0:2 - Prescaler divider

`impl W<u32, Reg<u32, _RLR>>`[src]

`pub fn rl(&mut self) -> RL_W`[src]

Bits 0:11 - Watchdog counter reload value

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn mux_seg(&mut self) -> MUX_SEG_W`[src]

Bit 7 - Mux segment enable

`pub fn bias(&mut self) -> BIAS_W`[src]

Bits 5:6 - Bias selector

`pub fn duty(&mut self) -> DUTY_W`[src]

Bits 2:4 - Duty selection

`pub fn vsel(&mut self) -> VSEL_W`[src]

Bit 1 - Voltage source selection

`pub fn lcden(&mut self) -> LCDEN_W`[src]

Bit 0 - LCD controller enable

`impl W<u32, Reg<u32, _FCR>>`[src]

`pub fn ps(&mut self) -> PS_W`[src]

Bits 22:25 - PS 16-bit prescaler

`pub fn div(&mut self) -> DIV_W`[src]

Bits 18:21 - DIV clock divider

`pub fn blink(&mut self) -> BLINK_W`[src]

Bits 16:17 - Blink mode selection

`pub fn blinkf(&mut self) -> BLINKF_W`[src]

Bits 13:15 - Blink frequency selection

`pub fn cc(&mut self) -> CC_W`[src]

Bits 10:12 - Contrast control

`pub fn dead(&mut self) -> DEAD_W`[src]

Bits 7:9 - Dead time duration

`pub fn pon(&mut self) -> PON_W`[src]

Bits 4:6 - Pulse ON duration

`pub fn uddie(&mut self) -> UDDIE_W`[src]

Bit 3 - Update display done interrupt enable

`pub fn sofie(&mut self) -> SOFIE_W`[src]

Bit 1 - Start of frame interrupt enable

`pub fn hd(&mut self) -> HD_W`[src]

Bit 0 - High drive enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn udr(&mut self) -> UDR_W`[src]

Bit 2 - Update display request

`impl W<u32, Reg<u32, _CLR>>`[src]

`pub fn uddc(&mut self) -> UDDC_W`[src]

Bit 3 - Update display done clear

`pub fn sofc(&mut self) -> SOFC_W`[src]

Bit 1 - Start of frame flag clear

`impl W<u32, Reg<u32, _RAM_COM0>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM1>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM2>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM3>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM4>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM5>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM6>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _RAM_COM7>>`[src]

`pub fn s31(&mut self) -> S31_W`[src]

Bit 31 - S31

`pub fn s30(&mut self) -> S30_W`[src]

Bit 30 - S30

`pub fn s29(&mut self) -> S29_W`[src]

Bit 29 - S29

`pub fn s28(&mut self) -> S28_W`[src]

Bit 28 - S28

`pub fn s27(&mut self) -> S27_W`[src]

Bit 27 - S27

`pub fn s26(&mut self) -> S26_W`[src]

Bit 26 - S26

`pub fn s25(&mut self) -> S25_W`[src]

Bit 25 - S25

`pub fn s24(&mut self) -> S24_W`[src]

Bit 24 - S24

`pub fn s23(&mut self) -> S23_W`[src]

Bit 23 - S23

`pub fn s22(&mut self) -> S22_W`[src]

Bit 22 - S22

`pub fn s21(&mut self) -> S21_W`[src]

Bit 21 - S21

`pub fn s20(&mut self) -> S20_W`[src]

Bit 20 - S20

`pub fn s19(&mut self) -> S19_W`[src]

Bit 19 - S19

`pub fn s18(&mut self) -> S18_W`[src]

Bit 18 - S18

`pub fn s17(&mut self) -> S17_W`[src]

Bit 17 - S17

`pub fn s16(&mut self) -> S16_W`[src]

Bit 16 - S16

`pub fn s15(&mut self) -> S15_W`[src]

Bit 15 - S15

`pub fn s14(&mut self) -> S14_W`[src]

Bit 14 - S14

`pub fn s13(&mut self) -> S13_W`[src]

Bit 13 - S13

`pub fn s12(&mut self) -> S12_W`[src]

Bit 12 - S12

`pub fn s11(&mut self) -> S11_W`[src]

Bit 11 - S11

`pub fn s10(&mut self) -> S10_W`[src]

Bit 10 - S10

`pub fn s09(&mut self) -> S09_W`[src]

Bit 9 - S09

`pub fn s08(&mut self) -> S08_W`[src]

Bit 8 - S08

`pub fn s07(&mut self) -> S07_W`[src]

Bit 7 - S07

`pub fn s06(&mut self) -> S06_W`[src]

Bit 6 - S06

`pub fn s05(&mut self) -> S05_W`[src]

Bit 5 - S05

`pub fn s04(&mut self) -> S04_W`[src]

Bit 4 - S04

`pub fn s03(&mut self) -> S03_W`[src]

Bit 3 - S03

`pub fn s02(&mut self) -> S02_W`[src]

Bit 2 - S02

`pub fn s01(&mut self) -> S01_W`[src]

Bit 1 - S01

`pub fn s00(&mut self) -> S00_W`[src]

Bit 0 - S00

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn opa3calout(&mut self) -> OPA3CALOUT_W`[src]

Bit 31 - OPAMP3 calibration output

`pub fn opa2calout(&mut self) -> OPA2CALOUT_W`[src]

Bit 30 - OPAMP2 calibration output

`pub fn opa1calout(&mut self) -> OPA1CALOUT_W`[src]

Bit 29 - OPAMP1 calibration output

`pub fn aop_range(&mut self) -> AOP_RANGE_W`[src]

Bit 28 - Power range selection

`pub fn s7sel2(&mut self) -> S7SEL2_W`[src]

Bit 27 - Switch 7 for OPAMP2 enable

`pub fn anawsel3(&mut self) -> ANAWSEL3_W`[src]

Bit 26 - Switch SanA enable for OPAMP3

`pub fn anawsel2(&mut self) -> ANAWSEL2_W`[src]

Bit 25 - Switch SanA enable for OPAMP2

`pub fn anawsel1(&mut self) -> ANAWSEL1_W`[src]

Bit 24 - Switch SanA enable for OPAMP1

`pub fn opa3lpm(&mut self) -> OPA3LPM_W`[src]

Bit 23 - OPAMP3 low power mode

`pub fn opa3cal_h(&mut self) -> OPA3CAL_H_W`[src]

Bit 22 - OPAMP3 offset calibration for N differential pair

`pub fn opa3cal_l(&mut self) -> OPA3CAL_L_W`[src]

Bit 21 - OPAMP3 offset Calibration for P differential pair

`pub fn s6sel3(&mut self) -> S6SEL3_W`[src]

Bit 20 - Switch 6 for OPAMP3 enable

`pub fn s5sel3(&mut self) -> S5SEL3_W`[src]

Bit 19 - Switch 5 for OPAMP3 enable

`pub fn s4sel3(&mut self) -> S4SEL3_W`[src]

Bit 18 - Switch 4 for OPAMP3 enable

`pub fn s3sel3(&mut self) -> S3SEL3_W`[src]

Bit 17 - Switch 3 for OPAMP3 Enable

`pub fn opa3pd(&mut self) -> OPA3PD_W`[src]

Bit 16 - OPAMP3 power down

`pub fn opa2lpm(&mut self) -> OPA2LPM_W`[src]

Bit 15 - OPAMP2 low power mode

`pub fn opa2cal_h(&mut self) -> OPA2CAL_H_W`[src]

Bit 14 - OPAMP2 offset calibration for N differential pair

`pub fn opa2cal_l(&mut self) -> OPA2CAL_L_W`[src]

Bit 13 - OPAMP2 offset Calibration for P differential pair

`pub fn s6sel2(&mut self) -> S6SEL2_W`[src]

Bit 12 - Switch 6 for OPAMP2 enable

`pub fn s5sel2(&mut self) -> S5SEL2_W`[src]

Bit 11 - Switch 5 for OPAMP2 enable

`pub fn s4sel2(&mut self) -> S4SEL2_W`[src]

Bit 10 - Switch 4 for OPAMP2 enable

`pub fn s3sel2(&mut self) -> S3SEL2_W`[src]

Bit 9 - Switch 3 for OPAMP2 enable

`pub fn opa2pd(&mut self) -> OPA2PD_W`[src]

Bit 8 - OPAMP2 power down

`pub fn opa1lpm(&mut self) -> OPA1LPM_W`[src]

Bit 7 - OPAMP1 low power mode

`pub fn opa1cal_h(&mut self) -> OPA1CAL_H_W`[src]

Bit 6 - OPAMP1 offset calibration for N differential pair

`pub fn opa1cal_l(&mut self) -> OPA1CAL_L_W`[src]

Bit 5 - OPAMP1 offset calibration for P differential pair

`pub fn s6sel1(&mut self) -> S6SEL1_W`[src]

Bit 4 - Switch 6 for OPAMP1 enable

`pub fn s5sel1(&mut self) -> S5SEL1_W`[src]

Bit 3 - Switch 5 for OPAMP1 enable

`pub fn s4sel1(&mut self) -> S4SEL1_W`[src]

Bit 2 - Switch 4 for OPAMP1 enable

`pub fn s3sel1(&mut self) -> S3SEL1_W`[src]

Bit 1 - Switch 3 for OPAMP1 enable

`pub fn opa1pd(&mut self) -> OPA1PD_W`[src]

Bit 0 - OPAMP1 power down

`impl W<u32, Reg<u32, _OTR>>`[src]

`pub fn ot_user(&mut self) -> OT_USER_W`[src]

Bit 31 - Select user or factory trimming value

`pub fn ao3_opt_offset_trim(&mut self) -> AO3_OPT_OFFSET_TRIM_W`[src]

Bits 20:29 - OPAMP3, 10-bit offset trim value for normal mode

`pub fn ao2_opt_offset_trim(&mut self) -> AO2_OPT_OFFSET_TRIM_W`[src]

Bits 10:19 - OPAMP2, 10-bit offset trim value for normal mode

`pub fn ao1_opt_offset_trim(&mut self) -> AO1_OPT_OFFSET_TRIM_W`[src]

Bits 0:9 - OPAMP1, 10-bit offset trim value for normal mode

`impl W<u32, Reg<u32, _LPOTR>>`[src]

`pub fn ao3_opt_offset_trim_lp(&mut self) -> AO3_OPT_OFFSET_TRIM_LP_W`[src]

Bits 20:29 - OPAMP3, 10-bit offset trim value for low power mode

`pub fn ao2_opt_offset_trim_lp(&mut self) -> AO2_OPT_OFFSET_TRIM_LP_W`[src]

Bits 10:19 - OPAMP2, 10-bit offset trim value for low power mode

`pub fn ao1_opt_offset_trim_lp(&mut self) -> AO1_OPT_OFFSET_TRIM_LP_W`[src]

Bits 0:9 - OPAMP1, 10-bit offset trim value for low power mode

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn lprun(&mut self) -> LPRUN_W`[src]

Bit 14 - Low power run mode

`pub fn vos(&mut self) -> VOS_W`[src]

Bits 11:12 - Voltage scaling range selection

`pub fn fwu(&mut self) -> FWU_W`[src]

Bit 10 - Fast wakeup

`pub fn ulp(&mut self) -> ULP_W`[src]

Bit 9 - Ultralow power mode

`pub fn dbp(&mut self) -> DBP_W`[src]

Bit 8 - Disable backup domain write protection

`pub fn pls(&mut self) -> PLS_W`[src]

Bits 5:7 - PVD level selection

`pub fn pvde(&mut self) -> PVDE_W`[src]

Bit 4 - Power voltage detector enable

`pub fn csbf(&mut self) -> CSBF_W`[src]

Bit 3 - Clear standby flag

`pub fn cwuf(&mut self) -> CWUF_W`[src]

Bit 2 - Clear wakeup flag

`pub fn pdds(&mut self) -> PDDS_W`[src]

Bit 1 - Power down deepsleep

`pub fn lpsdsr(&mut self) -> LPSDSR_W`[src]

Bit 0 - Low-power deep sleep

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn ewup3(&mut self) -> EWUP3_W`[src]

Bit 10 - Enable WKUP pin 3

`pub fn ewup2(&mut self) -> EWUP2_W`[src]

Bit 9 - Enable WKUP pin 2

`pub fn ewup1(&mut self) -> EWUP1_W`[src]

Bit 8 - Enable WKUP pin 1

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn rtcpre1(&mut self) -> RTCPRE1_W`[src]

Bit 30 - TC/LCD prescaler

`pub fn rtcpre0(&mut self) -> RTCPRE0_W`[src]

Bit 29 - RTCPRE0

`pub fn csson(&mut self) -> CSSON_W`[src]

Bit 28 - Clock security system enable

`pub fn pllon(&mut self) -> PLLON_W`[src]

Bit 24 - PLL enable

`pub fn hsebyp(&mut self) -> HSEBYP_W`[src]

Bit 18 - HSE clock bypass

`pub fn hseon(&mut self) -> HSEON_W`[src]

Bit 16 - HSE clock enable

`pub fn msion(&mut self) -> MSION_W`[src]

Bit 8 - MSI clock enable

`pub fn hsion(&mut self) -> HSION_W`[src]

Bit 0 - Internal high-speed clock enable

`impl W<u32, Reg<u32, _ICSCR>>`[src]

`pub fn msitrim(&mut self) -> MSITRIM_W`[src]

Bits 24:31 - MSI clock trimming

`pub fn msirange(&mut self) -> MSIRANGE_W`[src]

Bits 13:15 - MSI clock ranges

`pub fn hsitrim(&mut self) -> HSITRIM_W`[src]

Bits 8:12 - High speed internal clock trimming

`impl W<u32, Reg<u32, _CFGR>>`[src]

`pub fn mcopre(&mut self) -> MCOPRE_W`[src]

Bits 28:30 - Microcontroller clock output prescaler

`pub fn mcosel(&mut self) -> MCOSEL_W`[src]

Bits 24:26 - Microcontroller clock output selection

`pub fn plldiv(&mut self) -> PLLDIV_W`[src]

Bits 22:23 - PLL output division

`pub fn pllmul(&mut self) -> PLLMUL_W`[src]

Bits 18:21 - PLL multiplication factor

`pub fn pllsrc(&mut self) -> PLLSRC_W`[src]

Bit 16 - PLL entry clock source

`pub fn ppre2(&mut self) -> PPRE2_W`[src]

Bits 11:13 - APB high-speed prescaler (APB2)

`pub fn ppre1(&mut self) -> PPRE1_W`[src]

Bits 8:10 - APB low-speed prescaler (APB1)

`pub fn hpre(&mut self) -> HPRE_W`[src]

Bits 4:7 - AHB prescaler

`pub fn sw(&mut self) -> SW_W`[src]

Bits 0:1 - System clock switch

`impl W<u32, Reg<u32, _CIR>>`[src]

`pub fn cssc(&mut self) -> CSSC_W`[src]

Bit 23 - Clock security system interrupt clear

`pub fn msirdyc(&mut self) -> MSIRDYC_W`[src]

Bit 21 - MSI ready interrupt clear

`pub fn pllrdyc(&mut self) -> PLLRDYC_W`[src]

Bit 20 - PLL ready interrupt clear

`pub fn hserdyc(&mut self) -> HSERDYC_W`[src]

Bit 19 - HSE ready interrupt clear

`pub fn hsirdyc(&mut self) -> HSIRDYC_W`[src]

Bit 18 - HSI ready interrupt clear

`pub fn lserdyc(&mut self) -> LSERDYC_W`[src]

Bit 17 - LSE ready interrupt clear

`pub fn lsirdyc(&mut self) -> LSIRDYC_W`[src]

Bit 16 - LSI ready interrupt clear

`pub fn msirdyie(&mut self) -> MSIRDYIE_W`[src]

Bit 13 - MSI ready interrupt enable

`pub fn pllrdyie(&mut self) -> PLLRDYIE_W`[src]

Bit 12 - PLL ready interrupt enable

`pub fn hserdyie(&mut self) -> HSERDYIE_W`[src]

Bit 11 - HSE ready interrupt enable

`pub fn hsirdyie(&mut self) -> HSIRDYIE_W`[src]

Bit 10 - HSI ready interrupt enable

`pub fn lserdyie(&mut self) -> LSERDYIE_W`[src]

Bit 9 - LSE ready interrupt enable

`pub fn lsirdyie(&mut self) -> LSIRDYIE_W`[src]

Bit 8 - LSI ready interrupt enable

`impl W<u32, Reg<u32, _AHBRSTR>>`[src]

`pub fn fsmcrst(&mut self) -> FSMCRST_W`[src]

Bit 30 - FSMC reset

`pub fn dma2rst(&mut self) -> DMA2RST_W`[src]

Bit 25 - DMA2 reset

`pub fn dma1rst(&mut self) -> DMA1RST_W`[src]

Bit 24 - DMA1 reset

`pub fn flitfrst(&mut self) -> FLITFRST_W`[src]

Bit 15 - FLITF reset

`pub fn crcrst(&mut self) -> CRCRST_W`[src]

Bit 12 - CRC reset

`pub fn gpiogrst(&mut self) -> GPIOGRST_W`[src]

Bit 7 - IO port G reset

`pub fn gpiofrst(&mut self) -> GPIOFRST_W`[src]

Bit 6 - IO port F reset

`pub fn gpiohrst(&mut self) -> GPIOHRST_W`[src]

Bit 5 - IO port H reset

`pub fn gpioerst(&mut self) -> GPIOERST_W`[src]

Bit 4 - IO port E reset

`pub fn gpiodrst(&mut self) -> GPIODRST_W`[src]

Bit 3 - IO port D reset

`pub fn gpiocrst(&mut self) -> GPIOCRST_W`[src]

Bit 2 - IO port C reset

`pub fn gpiobrst(&mut self) -> GPIOBRST_W`[src]

Bit 1 - IO port B reset

`pub fn gpioarst(&mut self) -> GPIOARST_W`[src]

Bit 0 - IO port A reset

`impl W<u32, Reg<u32, _APB2RSTR>>`[src]

`pub fn usart1rst(&mut self) -> USART1RST_W`[src]

Bit 14 - USART1RST

`pub fn spi1rst(&mut self) -> SPI1RST_W`[src]

Bit 12 - SPI1RST

`pub fn sdiorst(&mut self) -> SDIORST_W`[src]

Bit 11 - SDIORST

`pub fn adc1rst(&mut self) -> ADC1RST_W`[src]

Bit 9 - ADC1RST

`pub fn tm11rst(&mut self) -> TM11RST_W`[src]

Bit 4 - TM11RST

`pub fn tm10rst(&mut self) -> TM10RST_W`[src]

Bit 3 - TM10RST

`pub fn tim9rst(&mut self) -> TIM9RST_W`[src]

Bit 2 - TIM9RST

`pub fn syscfgrst(&mut self) -> SYSCFGRST_W`[src]

Bit 0 - SYSCFGRST

`impl W<u32, Reg<u32, _APB1RSTR>>`[src]

`pub fn comprst(&mut self) -> COMPRST_W`[src]

Bit 31 - COMP interface reset

`pub fn dacrst(&mut self) -> DACRST_W`[src]

Bit 29 - DAC interface reset

`pub fn pwrrst(&mut self) -> PWRRST_W`[src]

Bit 28 - Power interface reset

`pub fn usbrst(&mut self) -> USBRST_W`[src]

Bit 23 - USB reset

`pub fn i2c2rst(&mut self) -> I2C2RST_W`[src]

Bit 22 - I2C 2 reset

`pub fn i2c1rst(&mut self) -> I2C1RST_W`[src]

Bit 21 - I2C 1 reset

`pub fn uart5rst(&mut self) -> UART5RST_W`[src]

Bit 20 - UART 5 reset

`pub fn uart4rst(&mut self) -> UART4RST_W`[src]

Bit 19 - UART 4 reset

`pub fn usart3rst(&mut self) -> USART3RST_W`[src]

Bit 18 - USART 3 reset

`pub fn usart2rst(&mut self) -> USART2RST_W`[src]

Bit 17 - USART 2 reset

`pub fn spi3rst(&mut self) -> SPI3RST_W`[src]

Bit 15 - SPI 3 reset

`pub fn spi2rst(&mut self) -> SPI2RST_W`[src]

Bit 14 - SPI 2 reset

`pub fn wwdrst(&mut self) -> WWDRST_W`[src]

Bit 11 - Window watchdog reset

`pub fn lcdrst(&mut self) -> LCDRST_W`[src]

Bit 9 - LCD reset

`pub fn tim7rst(&mut self) -> TIM7RST_W`[src]

Bit 5 - Timer 7 reset

`pub fn tim6rst(&mut self) -> TIM6RST_W`[src]

Bit 4 - Timer 6reset

`pub fn tim5rst(&mut self) -> TIM5RST_W`[src]

Bit 3 - Timer 5 reset

`pub fn tim4rst(&mut self) -> TIM4RST_W`[src]

Bit 2 - Timer 4 reset

`pub fn tim3rst(&mut self) -> TIM3RST_W`[src]

Bit 1 - Timer 3 reset

`pub fn tim2rst(&mut self) -> TIM2RST_W`[src]

Bit 0 - Timer 2 reset

`impl W<u32, Reg<u32, _AHBENR>>`[src]

`pub fn fsmcen(&mut self) -> FSMCEN_W`[src]

Bit 30 - FSMCEN

`pub fn dma2en(&mut self) -> DMA2EN_W`[src]

Bit 25 - DMA2 clock enable

`pub fn dma1en(&mut self) -> DMA1EN_W`[src]

Bit 24 - DMA1 clock enable

`pub fn flitfen(&mut self) -> FLITFEN_W`[src]

Bit 15 - FLITF clock enable

`pub fn crcen(&mut self) -> CRCEN_W`[src]

Bit 12 - CRC clock enable

`pub fn gpiopgen(&mut self) -> GPIOPGEN_W`[src]

Bit 7 - IO port G clock enable

`pub fn gpiopfen(&mut self) -> GPIOPFEN_W`[src]

Bit 6 - IO port F clock enable

`pub fn gpiophen(&mut self) -> GPIOPHEN_W`[src]

Bit 5 - IO port H clock enable

`pub fn gpiopeen(&mut self) -> GPIOPEEN_W`[src]

Bit 4 - IO port E clock enable

`pub fn gpiopden(&mut self) -> GPIOPDEN_W`[src]

Bit 3 - IO port D clock enable

`pub fn gpiopcen(&mut self) -> GPIOPCEN_W`[src]

Bit 2 - IO port C clock enable

`pub fn gpiopben(&mut self) -> GPIOPBEN_W`[src]

Bit 1 - IO port B clock enable

`pub fn gpiopaen(&mut self) -> GPIOPAEN_W`[src]

Bit 0 - IO port A clock enable

`impl W<u32, Reg<u32, _APB2ENR>>`[src]

`pub fn usart1en(&mut self) -> USART1EN_W`[src]

Bit 14 - USART1 clock enable

`pub fn spi1en(&mut self) -> SPI1EN_W`[src]

Bit 12 - SPI 1 clock enable

`pub fn sdioen(&mut self) -> SDIOEN_W`[src]

Bit 11 - SDIO clock enable

`pub fn adc1en(&mut self) -> ADC1EN_W`[src]

Bit 9 - ADC1 interface clock enable

`pub fn tim11en(&mut self) -> TIM11EN_W`[src]

Bit 4 - TIM11 timer clock enable

`pub fn tim10en(&mut self) -> TIM10EN_W`[src]

Bit 3 - TIM10 timer clock enable

`pub fn tim9en(&mut self) -> TIM9EN_W`[src]

Bit 2 - TIM9 timer clock enable

`pub fn syscfgen(&mut self) -> SYSCFGEN_W`[src]

Bit 0 - System configuration controller clock enable

`impl W<u32, Reg<u32, _APB1ENR>>`[src]

`pub fn compen(&mut self) -> COMPEN_W`[src]

Bit 31 - COMP interface clock enable

`pub fn dacen(&mut self) -> DACEN_W`[src]

Bit 29 - DAC interface clock enable

`pub fn pwren(&mut self) -> PWREN_W`[src]

Bit 28 - Power interface clock enable

`pub fn usben(&mut self) -> USBEN_W`[src]

Bit 23 - USB clock enable

`pub fn i2c2en(&mut self) -> I2C2EN_W`[src]

Bit 22 - I2C 2 clock enable

`pub fn i2c1en(&mut self) -> I2C1EN_W`[src]

Bit 21 - I2C 1 clock enable

`pub fn usart5en(&mut self) -> USART5EN_W`[src]

Bit 20 - UART 5 clock enable

`pub fn usart4en(&mut self) -> USART4EN_W`[src]

Bit 19 - UART 4 clock enable

`pub fn usart3en(&mut self) -> USART3EN_W`[src]

Bit 18 - USART 3 clock enable

`pub fn usart2en(&mut self) -> USART2EN_W`[src]

Bit 17 - USART 2 clock enable

`pub fn spi3en(&mut self) -> SPI3EN_W`[src]

Bit 15 - SPI 3 clock enable

`pub fn spi2en(&mut self) -> SPI2EN_W`[src]

Bit 14 - SPI 2 clock enable

`pub fn wwdgen(&mut self) -> WWDGEN_W`[src]

Bit 11 - Window watchdog clock enable

`pub fn lcden(&mut self) -> LCDEN_W`[src]

Bit 9 - LCD clock enable

`pub fn tim7en(&mut self) -> TIM7EN_W`[src]

Bit 5 - Timer 7 clock enable

`pub fn tim6en(&mut self) -> TIM6EN_W`[src]

Bit 4 - Timer 6 clock enable

`pub fn tim5en(&mut self) -> TIM5EN_W`[src]

Bit 3 - Timer 5 clock enable

`pub fn tim4en(&mut self) -> TIM4EN_W`[src]

Bit 2 - Timer 4 clock enable

`pub fn tim3en(&mut self) -> TIM3EN_W`[src]

Bit 1 - Timer 3 clock enable

`pub fn tim2en(&mut self) -> TIM2EN_W`[src]

Bit 0 - Timer 2 clock enable

`impl W<u32, Reg<u32, _AHBLPENR>>`[src]

`pub fn dma2lpen(&mut self) -> DMA2LPEN_W`[src]

Bit 25 - DMA2 clock enable during Sleep mode

`pub fn dma1lpen(&mut self) -> DMA1LPEN_W`[src]

Bit 24 - DMA1 clock enable during Sleep mode

`pub fn sramlpen(&mut self) -> SRAMLPEN_W`[src]

Bit 16 - SRAM clock enable during Sleep mode

`pub fn flitflpen(&mut self) -> FLITFLPEN_W`[src]

Bit 15 - FLITF clock enable during Sleep mode

`pub fn crclpen(&mut self) -> CRCLPEN_W`[src]

Bit 12 - CRC clock enable during Sleep mode

`pub fn gpioglpen(&mut self) -> GPIOGLPEN_W`[src]

Bit 7 - IO port G clock enable during Sleep mode

`pub fn gpioflpen(&mut self) -> GPIOFLPEN_W`[src]

Bit 6 - IO port F clock enable during Sleep mode

`pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W`[src]

Bit 5 - IO port H clock enable during Sleep mode

`pub fn gpioelpen(&mut self) -> GPIOELPEN_W`[src]

Bit 4 - IO port E clock enable during Sleep mode

`pub fn gpiodlpen(&mut self) -> GPIODLPEN_W`[src]

Bit 3 - IO port D clock enable during Sleep mode

`pub fn gpioclpen(&mut self) -> GPIOCLPEN_W`[src]

Bit 2 - IO port C clock enable during Sleep mode

`pub fn gpioblpen(&mut self) -> GPIOBLPEN_W`[src]

Bit 1 - IO port B clock enable during Sleep mode

`pub fn gpioalpen(&mut self) -> GPIOALPEN_W`[src]

Bit 0 - IO port A clock enable during Sleep mode

`impl W<u32, Reg<u32, _APB2LPENR>>`[src]

`pub fn usart1lpen(&mut self) -> USART1LPEN_W`[src]

Bit 14 - USART1 clock enable during Sleep mode

`pub fn spi1lpen(&mut self) -> SPI1LPEN_W`[src]

Bit 12 - SPI 1 clock enable during Sleep mode

`pub fn sdiolpen(&mut self) -> SDIOLPEN_W`[src]

Bit 11 - SDIO clock enable during Sleep mode

`pub fn adc1lpen(&mut self) -> ADC1LPEN_W`[src]

Bit 9 - ADC1 interface clock enable during Sleep mode

`pub fn tim11lpen(&mut self) -> TIM11LPEN_W`[src]

Bit 4 - TIM11 timer clock enable during Sleep mode

`pub fn tim10lpen(&mut self) -> TIM10LPEN_W`[src]

Bit 3 - TIM10 timer clock enable during Sleep mode

`pub fn tim9lpen(&mut self) -> TIM9LPEN_W`[src]

Bit 2 - TIM9 timer clock enable during Sleep mode

`pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W`[src]

Bit 0 - System configuration controller clock enable during Sleep mode

`impl W<u32, Reg<u32, _APB1LPENR>>`[src]

`pub fn complpen(&mut self) -> COMPLPEN_W`[src]

Bit 31 - COMP interface clock enable during Sleep mode

`pub fn daclpen(&mut self) -> DACLPEN_W`[src]

Bit 29 - DAC interface clock enable during Sleep mode

`pub fn pwrlpen(&mut self) -> PWRLPEN_W`[src]

Bit 28 - Power interface clock enable during Sleep mode

`pub fn usblpen(&mut self) -> USBLPEN_W`[src]

Bit 23 - USB clock enable during Sleep mode

`pub fn i2c2lpen(&mut self) -> I2C2LPEN_W`[src]

Bit 22 - I2C 2 clock enable during Sleep mode

`pub fn i2c1lpen(&mut self) -> I2C1LPEN_W`[src]

Bit 21 - I2C 1 clock enable during Sleep mode

`pub fn usart3lpen(&mut self) -> USART3LPEN_W`[src]

Bit 18 - USART 3 clock enable during Sleep mode

`pub fn usart2lpen(&mut self) -> USART2LPEN_W`[src]

Bit 17 - USART 2 clock enable during Sleep mode

`pub fn spi2lpen(&mut self) -> SPI2LPEN_W`[src]

Bit 14 - SPI 2 clock enable during Sleep mode

`pub fn wwdglpen(&mut self) -> WWDGLPEN_W`[src]

Bit 11 - Window watchdog clock enable during Sleep mode

`pub fn lcdlpen(&mut self) -> LCDLPEN_W`[src]

Bit 9 - LCD clock enable during Sleep mode

`pub fn tim7lpen(&mut self) -> TIM7LPEN_W`[src]

Bit 5 - Timer 7 clock enable during Sleep mode

`pub fn tim6lpen(&mut self) -> TIM6LPEN_W`[src]

Bit 4 - Timer 6 clock enable during Sleep mode

`pub fn tim4lpen(&mut self) -> TIM4LPEN_W`[src]

Bit 2 - Timer 4 clock enable during Sleep mode

`pub fn tim3lpen(&mut self) -> TIM3LPEN_W`[src]

Bit 1 - Timer 3 clock enable during Sleep mode

`pub fn tim2lpen(&mut self) -> TIM2LPEN_W`[src]

Bit 0 - Timer 2 clock enable during Sleep mode

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn lpwrstf(&mut self) -> LPWRSTF_W`[src]

Bit 31 - Low-power reset flag

`pub fn wwdgrstf(&mut self) -> WWDGRSTF_W`[src]

Bit 30 - Window watchdog reset flag

`pub fn iwdgrstf(&mut self) -> IWDGRSTF_W`[src]

Bit 29 - Independent watchdog reset flag

`pub fn sftrstf(&mut self) -> SFTRSTF_W`[src]

Bit 28 - Software reset flag

`pub fn porrstf(&mut self) -> PORRSTF_W`[src]

Bit 27 - POR/PDR reset flag

`pub fn pinrstf(&mut self) -> PINRSTF_W`[src]

Bit 26 - PIN reset flag

`pub fn rmvf(&mut self) -> RMVF_W`[src]

Bit 24 - Remove reset flag

`pub fn rtcrst(&mut self) -> RTCRST_W`[src]

Bit 23 - RTC software reset

`pub fn rtcen(&mut self) -> RTCEN_W`[src]

Bit 22 - RTC clock enable

`pub fn rtcsel(&mut self) -> RTCSEL_W`[src]

Bits 16:17 - RTC and LCD clock source selection

`pub fn lsebyp(&mut self) -> LSEBYP_W`[src]

Bit 10 - External low-speed oscillator bypass

`pub fn lseon(&mut self) -> LSEON_W`[src]

Bit 8 - External low-speed oscillator enable

`pub fn lsion(&mut self) -> LSION_W`[src]

Bit 0 - Internal low-speed oscillator enable

`impl W<u32, Reg<u32, _ICR>>`[src]

`pub fn ic4(&mut self) -> IC4_W`[src]

Bit 21 - IC4

`pub fn ic3(&mut self) -> IC3_W`[src]

Bit 20 - IC3

`pub fn ic2(&mut self) -> IC2_W`[src]

Bit 19 - IC2

`pub fn ic1(&mut self) -> IC1_W`[src]

Bit 18 - IC1

`pub fn tim(&mut self) -> TIM_W`[src]

Bits 16:17 - Timer select bits

`pub fn ic4ios(&mut self) -> IC4IOS_W`[src]

Bits 12:15 - Input capture 4 select bits

`pub fn ic3ios(&mut self) -> IC3IOS_W`[src]

Bits 8:11 - Input capture 3 select bits

`pub fn ic2ios(&mut self) -> IC2IOS_W`[src]

Bits 4:7 - Input capture 2 select bits

`pub fn ic1ios(&mut self) -> IC1IOS_W`[src]

Bits 0:3 - Input capture 1 select bits

`impl W<u32, Reg<u32, _ASCR1>>`[src]

`pub fn scm(&mut self) -> SCM_W`[src]

Bit 31 - Switch control mode

`pub fn ch30gr11_4(&mut self) -> CH30GR11_4_W`[src]

Bit 30 - Analog switch control

`pub fn ch29gr11_3(&mut self) -> CH29GR11_3_W`[src]

Bit 29 - Analog switch control

`pub fn ch28gr11_2(&mut self) -> CH28GR11_2_W`[src]

Bit 28 - Analog switch control

`pub fn ch27gr11_1(&mut self) -> CH27GR11_1_W`[src]

Bit 27 - Analog switch control

`pub fn vcomp(&mut self) -> VCOMP_W`[src]

Bit 26 - ADC analog switch selection for internal node to comparator 1

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Analog I/O switch control of channel CH25

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Analog I/O switch control of channel CH24

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Analog I/O switch control of channel CH23

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Analog I/O switch control of channel CH22

`pub fn ch21gr7_4(&mut self) -> CH21GR7_4_W`[src]

Bit 21 - Analog switch control

`pub fn ch20gr7_3(&mut self) -> CH20GR7_3_W`[src]

Bit 20 - Analog switch control

`pub fn ch19gr7_2(&mut self) -> CH19GR7_2_W`[src]

Bit 19 - Analog switch control

`pub fn ch18gr7_1(&mut self) -> CH18GR7_1_W`[src]

Bit 18 - Analog switch control

`pub fn ch31gr7_1(&mut self) -> CH31GR7_1_W`[src]

Bit 16 - Analog switch control

`pub fn ch15gr9_2(&mut self) -> CH15GR9_2_W`[src]

Bit 15 - Analog switch control

`pub fn ch14gr9_1(&mut self) -> CH14GR9_1_W`[src]

Bit 14 - Analog switch control

`pub fn ch13gr8_4(&mut self) -> CH13GR8_4_W`[src]

Bit 13 - Analog switch control

`pub fn ch12gr8_3(&mut self) -> CH12GR8_3_W`[src]

Bit 12 - Analog switch control

`pub fn ch11gr8_2(&mut self) -> CH11GR8_2_W`[src]

Bit 11 - Analog switch control

`pub fn ch10gr8_1(&mut self) -> CH10GR8_1_W`[src]

Bit 10 - Analog switch control

`pub fn ch9gr3_2(&mut self) -> CH9GR3_2_W`[src]

Bit 9 - Analog switch control

`pub fn ch8gr3_1(&mut self) -> CH8GR3_1_W`[src]

Bit 8 - Analog switch control

`pub fn ch7gr2_2(&mut self) -> CH7GR2_2_W`[src]

Bit 7 - Analog switch control

`pub fn ch6gr2_1(&mut self) -> CH6GR2_1_W`[src]

Bit 6 - Analog switch control

`pub fn comp1_sw1(&mut self) -> COMP1_SW1_W`[src]

Bit 5 - Comparator 1 analog switch

`pub fn ch31gr11_5(&mut self) -> CH31GR11_5_W`[src]

Bit 4 - Analog switch control

`pub fn ch3gr1_4(&mut self) -> CH3GR1_4_W`[src]

Bit 3 - Analog switch control

`pub fn ch2gr1_3(&mut self) -> CH2GR1_3_W`[src]

Bit 2 - Analog switch control

`pub fn ch1gr1_2(&mut self) -> CH1GR1_2_W`[src]

Bit 1 - Analog switch control

`pub fn ch0gr1_1(&mut self) -> CH0GR1_1_W`[src]

Bit 0 - Analog switch control

`impl W<u32, Reg<u32, _ASCR2>>`[src]

`pub fn gr5_4(&mut self) -> GR5_4_W`[src]

Bit 29 - GR5_4 analog switch control

`pub fn gr6_4(&mut self) -> GR6_4_W`[src]

Bit 28 - GR6_4 analog switch control

`pub fn gr6_3(&mut self) -> GR6_3_W`[src]

Bit 27 - GR6_3 analog switch control

`pub fn gr7_7(&mut self) -> GR7_7_W`[src]

Bit 26 - GR7_7 analog switch control

`pub fn gr7_6(&mut self) -> GR7_6_W`[src]

Bit 25 - GR7_6 analog switch control

`pub fn gr7_5(&mut self) -> GR7_5_W`[src]

Bit 24 - GR7_5 analog switch control

`pub fn gr2_5(&mut self) -> GR2_5_W`[src]

Bit 23 - GR2_5 analog switch control

`pub fn gr2_4(&mut self) -> GR2_4_W`[src]

Bit 22 - GR2_4 analog switch control

`pub fn gr2_3(&mut self) -> GR2_3_W`[src]

Bit 21 - GR2_3 analog switch control

`pub fn gr9_4(&mut self) -> GR9_4_W`[src]

Bit 20 - GR9_4 analog switch control

`pub fn gr9_3(&mut self) -> GR9_3_W`[src]

Bit 19 - GR9_3 analog switch control

`pub fn gr3_5(&mut self) -> GR3_5_W`[src]

Bit 18 - GR3_5 analog switch control

`pub fn gr3_4(&mut self) -> GR3_4_W`[src]

Bit 17 - GR3_4 analog switch control

`pub fn gr3_3(&mut self) -> GR3_3_W`[src]

Bit 16 - GR3_3 analog switch control

`pub fn gr4_3(&mut self) -> GR4_3_W`[src]

Bit 11 - GR4_3 analog switch control

`pub fn gr4_2(&mut self) -> GR4_2_W`[src]

Bit 10 - GR4_2 analog switch control

`pub fn gr4_1(&mut self) -> GR4_1_W`[src]

Bit 9 - GR4_1 analog switch control

`pub fn gr5_3(&mut self) -> GR5_3_W`[src]

Bit 8 - GR5_3 analog switch control

`pub fn gr5_2(&mut self) -> GR5_2_W`[src]

Bit 7 - GR5_2 analog switch control

`pub fn gr5_1(&mut self) -> GR5_1_W`[src]

Bit 6 - GR5_1 analog switch control

`pub fn gr6_2(&mut self) -> GR6_2_W`[src]

Bit 5 - GR6_2 analog switch control

`pub fn gr6_1(&mut self) -> GR6_1_W`[src]

Bit 4 - GR6_1 analog switch control

`pub fn gr10_4(&mut self) -> GR10_4_W`[src]

Bit 3 - GR10_4 analog switch control

`pub fn gr10_3(&mut self) -> GR10_3_W`[src]

Bit 2 - GR10_3 analog switch control

`pub fn gr10_2(&mut self) -> GR10_2_W`[src]

Bit 1 - GR10_2 analog switch control

`pub fn gr10_1(&mut self) -> GR10_1_W`[src]

Bit 0 - GR10_1 analog switch control

`impl W<u32, Reg<u32, _HYSCR1>>`[src]

`pub fn pb(&mut self) -> PB_W`[src]

Bits 16:31 - Port B hysteresis control on/off

`pub fn pa(&mut self) -> PA_W`[src]

Bits 0:15 - Port A hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR2>>`[src]

`pub fn pd(&mut self) -> PD_W`[src]

Bits 16:31 - Port D hysteresis control on/off

`pub fn pc(&mut self) -> PC_W`[src]

Bits 0:15 - Port C hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR3>>`[src]

`pub fn pf(&mut self) -> PF_W`[src]

Bits 16:31 - Port F hysteresis control on/off

`pub fn pe(&mut self) -> PE_W`[src]

Bits 0:15 - Port E hysteresis control on/off

`impl W<u32, Reg<u32, _HYSCR4>>`[src]

`pub fn pg(&mut self) -> PG_W`[src]

Bits 0:15 - Port G hysteresis control on/off

`impl W<u32, Reg<u32, _TR>>`[src]

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn yt(&mut self) -> YT_W`[src]

Bits 20:23 - Year tens in BCD format

`pub fn yu(&mut self) -> YU_W`[src]

Bits 16:19 - Year units in BCD format

`pub fn wdu(&mut self) -> WDU_W`[src]

Bits 13:15 - Week day units

`pub fn mt(&mut self) -> MT_W`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&mut self) -> MU_W`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&mut self) -> DT_W`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&mut self) -> DU_W`[src]

Bits 0:3 - Date units in BCD format

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn coe(&mut self) -> COE_W`[src]

Bit 23 - Calibration output enable

`pub fn osel(&mut self) -> OSEL_W`[src]

Bits 21:22 - Output selection

`pub fn pol(&mut self) -> POL_W`[src]

Bit 20 - Output polarity

`pub fn cosel(&mut self) -> COSEL_W`[src]

Bit 19 - Calibration output selection

`pub fn bkp(&mut self) -> BKP_W`[src]

Bit 18 - Backup

`pub fn sub1h(&mut self) -> SUB1H_W`[src]

Bit 17 - Subtract 1 hour

`pub fn add1h(&mut self) -> ADD1H_W`[src]

Bit 16 - Add 1 hour

`pub fn tsie(&mut self) -> TSIE_W`[src]

Bit 15 - Time-stamp interrupt enable

`pub fn wutie(&mut self) -> WUTIE_W`[src]

Bit 14 - Wakeup timer interrupt enable

`pub fn alrbie(&mut self) -> ALRBIE_W`[src]

Bit 13 - Alarm B interrupt enable

`pub fn alraie(&mut self) -> ALRAIE_W`[src]

Bit 12 - Alarm A interrupt enable

`pub fn tse(&mut self) -> TSE_W`[src]

Bit 11 - Time stamp enable

`pub fn wute(&mut self) -> WUTE_W`[src]

Bit 10 - Wakeup timer enable

`pub fn alrbe(&mut self) -> ALRBE_W`[src]

Bit 9 - Alarm B enable

`pub fn alrae(&mut self) -> ALRAE_W`[src]

Bit 8 - Alarm A enable

`pub fn dce(&mut self) -> DCE_W`[src]

Bit 7 - Coarse digital calibration enable

`pub fn fmt(&mut self) -> FMT_W`[src]

Bit 6 - Hour format

`pub fn bypshad(&mut self) -> BYPSHAD_W`[src]

Bit 5 - Bypass the shadow registers

`pub fn refckon(&mut self) -> REFCKON_W`[src]

Bit 4 - Reference clock detection enable

`pub fn tsedge(&mut self) -> TSEDGE_W`[src]

Bit 3 - Time-stamp event active edge

`pub fn wcksel(&mut self) -> WCKSEL_W`[src]

Bits 0:2 - WCKSEL

`impl W<u32, Reg<u32, _ISR>>`[src]

`pub fn tamp3f(&mut self) -> TAMP3F_W`[src]

Bit 15 - TAMPER3 detection flag

`pub fn tamp2f(&mut self) -> TAMP2F_W`[src]

Bit 14 - TAMPER2 detection flag

`pub fn tamp1f(&mut self) -> TAMP1F_W`[src]

Bit 13 - Tamper detection flag

`pub fn tsovf(&mut self) -> TSOVF_W`[src]

Bit 12 - Timestamp overflow flag

`pub fn tsf(&mut self) -> TSF_W`[src]

Bit 11 - Timestamp flag

`pub fn wutf(&mut self) -> WUTF_W`[src]

Bit 10 - Wakeup timer flag

`pub fn alrbf(&mut self) -> ALRBF_W`[src]

Bit 9 - Alarm B flag

`pub fn alraf(&mut self) -> ALRAF_W`[src]

Bit 8 - Alarm A flag

`pub fn init(&mut self) -> INIT_W`[src]

Bit 7 - Initialization mode

`pub fn initf(&mut self) -> INITF_W`[src]

Bit 6 - Initialization flag

`pub fn rsf(&mut self) -> RSF_W`[src]

Bit 5 - Registers synchronization flag

`pub fn shpf(&mut self) -> SHPF_W`[src]

Bit 3 - Shift operation pending

`impl W<u32, Reg<u32, _PRER>>`[src]

`pub fn prediv_a(&mut self) -> PREDIV_A_W`[src]

Bits 16:22 - Asynchronous prescaler factor

`pub fn prediv_s(&mut self) -> PREDIV_S_W`[src]

Bits 0:14 - Synchronous prescaler factor

`impl W<u32, Reg<u32, _WUTR>>`[src]

`pub fn wut(&mut self) -> WUT_W`[src]

Bits 0:15 - Wakeup auto-reload value bits

`impl W<u32, Reg<u32, _CALIBR>>`[src]

`pub fn dcs(&mut self) -> DCS_W`[src]

Bit 7 - Digital calibration sign

`pub fn dc(&mut self) -> DC_W`[src]

Bits 0:4 - Digital calibration

`impl W<u32, Reg<u32, _ALRMAR>>`[src]

`pub fn msk4(&mut self) -> MSK4_W`[src]

Bit 31 - Alarm A date mask

`pub fn wdsel(&mut self) -> WDSEL_W`[src]

Bit 30 - Week day selection

`pub fn dt(&mut self) -> DT_W`[src]

Bits 28:29 - Date tens in BCD format.

`pub fn du(&mut self) -> DU_W`[src]

Bits 24:27 - Date units or day in BCD format.

`pub fn msk3(&mut self) -> MSK3_W`[src]

Bit 23 - Alarm A hours mask

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format.

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format.

`pub fn msk2(&mut self) -> MSK2_W`[src]

Bit 15 - Alarm A minutes mask

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format.

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format.

`pub fn msk1(&mut self) -> MSK1_W`[src]

Bit 7 - Alarm A seconds mask

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format.

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format.

`impl W<u32, Reg<u32, _ALRMBR>>`[src]

`pub fn msk4(&mut self) -> MSK4_W`[src]

Bit 31 - Alarm B date mask

`pub fn wdsel(&mut self) -> WDSEL_W`[src]

Bit 30 - Week day selection

`pub fn dt(&mut self) -> DT_W`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&mut self) -> DU_W`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&mut self) -> MSK3_W`[src]

Bit 23 - Alarm B hours mask

`pub fn pm(&mut self) -> PM_W`[src]

Bit 22 - AM/PM notation

`pub fn ht(&mut self) -> HT_W`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&mut self) -> HU_W`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&mut self) -> MSK2_W`[src]

Bit 15 - Alarm B minutes mask

`pub fn mnt(&mut self) -> MNT_W`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&mut self) -> MNU_W`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&mut self) -> MSK1_W`[src]

Bit 7 - Alarm B seconds mask

`pub fn st(&mut self) -> ST_W`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&mut self) -> SU_W`[src]

Bits 0:3 - Second units in BCD format

`impl W<u32, Reg<u32, _WPR>>`[src]

`pub fn key(&mut self) -> KEY_W`[src]

Bits 0:7 - Write protection key

`impl W<u32, Reg<u32, _SHIFTR>>`[src]

`pub fn add1s(&mut self) -> ADD1S_W`[src]

Bit 31 - ADD1S

`pub fn subfs(&mut self) -> SUBFS_W`[src]

Bits 0:14 - Subtract a fraction of a second

`impl W<u32, Reg<u32, _CALR>>`[src]

`pub fn calp(&mut self) -> CALP_W`[src]

Bit 15 - Use an 8-second calibration cycle period

`pub fn calw8(&mut self) -> CALW8_W`[src]

Bit 14 - Use a 16-second calibration cycle period

`pub fn calw16(&mut self) -> CALW16_W`[src]

Bit 13 - CALW16

`pub fn calm(&mut self) -> CALM_W`[src]

Bits 0:8 - Calibration minus

`impl W<u32, Reg<u32, _TAFCR>>`[src]

`pub fn alarmouttype(&mut self) -> ALARMOUTTYPE_W`[src]

Bit 18 - AFO_ALARM output type

`pub fn tamppudis(&mut self) -> TAMPPUDIS_W`[src]

Bit 15 - TAMPER pull-up disable

`pub fn tampprch(&mut self) -> TAMPPRCH_W`[src]

Bits 13:14 - Tamper precharge duration

`pub fn tampflt(&mut self) -> TAMPFLT_W`[src]

Bits 11:12 - Tamper filter count

`pub fn tampfreq(&mut self) -> TAMPFREQ_W`[src]

Bits 8:10 - Tamper sampling frequency

`pub fn tampts(&mut self) -> TAMPTS_W`[src]

Bit 7 - Activate timestamp on tamper detection event

`pub fn tamp3trg(&mut self) -> TAMP3TRG_W`[src]

Bit 6 - TAMPER1 mapping

`pub fn tamp3e(&mut self) -> TAMP3E_W`[src]

Bit 5 - TIMESTAMP mapping

`pub fn tamp2trg(&mut self) -> TAMP2TRG_W`[src]

Bit 4 - Active level for tamper 2

`pub fn tamp2e(&mut self) -> TAMP2E_W`[src]

Bit 3 - Tamper 2 detection enable

`pub fn tampie(&mut self) -> TAMPIE_W`[src]

Bit 2 - Tamper interrupt enable

`pub fn tamp1etrg(&mut self) -> TAMP1ETRG_W`[src]

Bit 1 - Active level for tamper 1

`pub fn tamp1e(&mut self) -> TAMP1E_W`[src]

Bit 0 - Tamper 1 detection enable

`impl W<u32, Reg<u32, _ALRMASSR>>`[src]

`pub fn maskss(&mut self) -> MASKSS_W`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&mut self) -> SS_W`[src]

Bits 0:14 - Sub seconds value

`impl W<u32, Reg<u32, _ALRMBSSR>>`[src]

`pub fn maskss(&mut self) -> MASKSS_W`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&mut self) -> SS_W`[src]

Bits 0:14 - Sub seconds value

`impl W<u32, Reg<u32, _BKPR>>`[src]

`pub fn bkp(&mut self) -> BKP_W`[src]

Bits 0:31 - BKP

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn pwrctrl(&mut self) -> PWRCTRL_W`[src]

Bits 0:1 - Power supply control bits.

`impl W<u32, Reg<u32, _CLKCR>>`[src]

`pub fn hwfc_en(&mut self) -> HWFC_EN_W`[src]

Bit 14 - HW Flow Control enable

`pub fn negedge(&mut self) -> NEGEDGE_W`[src]

Bit 13 - SDIO_CK dephasing selection bit

`pub fn widbus(&mut self) -> WIDBUS_W`[src]

Bits 11:12 - Wide bus mode enable bit

`pub fn bypass(&mut self) -> BYPASS_W`[src]

Bit 10 - Clock divider bypass enable bit

`pub fn pwrsav(&mut self) -> PWRSAV_W`[src]

Bit 9 - Power saving configuration bit

`pub fn clken(&mut self) -> CLKEN_W`[src]

Bit 8 - Clock enable bit

`pub fn clkdiv(&mut self) -> CLKDIV_W`[src]

Bits 0:7 - Clock divide factor

`impl W<u32, Reg<u32, _ARG>>`[src]

`pub fn cmdarg(&mut self) -> CMDARG_W`[src]

Bits 0:31 - Command argument

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn ce_atacmd(&mut self) -> CE_ATACMD_W`[src]

Bit 14 - CE-ATA command

`pub fn n_ien(&mut self) -> NIEN_W`[src]

Bit 13 - not Interrupt Enable

`pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W`[src]

Bit 12 - Enable CMD completion

`pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W`[src]

Bit 11 - SD I/O suspend command

`pub fn cpsmen(&mut self) -> CPSMEN_W`[src]

Bit 10 - Command path state machine (CPSM) Enable bit

`pub fn waitpend(&mut self) -> WAITPEND_W`[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).

`pub fn waitint(&mut self) -> WAITINT_W`[src]

Bit 8 - CPSM waits for interrupt request

`pub fn waitresp(&mut self) -> WAITRESP_W`[src]

Bits 6:7 - Wait for response bits

`pub fn cmdindex(&mut self) -> CMDINDEX_W`[src]

Bits 0:5 - Command index

`impl W<u32, Reg<u32, _DTIMER>>`[src]

`pub fn datatime(&mut self) -> DATATIME_W`[src]

Bits 0:31 - Data timeout period

`impl W<u32, Reg<u32, _DLEN>>`[src]

`pub fn datalength(&mut self) -> DATALENGTH_W`[src]

Bits 0:24 - Data length value

`impl W<u32, Reg<u32, _DCTRL>>`[src]

`pub fn sdioen(&mut self) -> SDIOEN_W`[src]

Bit 11 - SD I/O enable functions

`pub fn rwmod(&mut self) -> RWMOD_W`[src]

Bit 10 - Read wait mode

`pub fn rwstop(&mut self) -> RWSTOP_W`[src]

Bit 9 - Read wait stop

`pub fn rwstart(&mut self) -> RWSTART_W`[src]

Bit 8 - Read wait start

`pub fn dblocksize(&mut self) -> DBLOCKSIZE_W`[src]

Bits 4:7 - Data block size

`pub fn dmaen(&mut self) -> DMAEN_W`[src]

Bit 3 - DMA enable bit

`pub fn dtmode(&mut self) -> DTMODE_W`[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

`pub fn dtdir(&mut self) -> DTDIR_W`[src]

Bit 1 - Data transfer direction selection

`pub fn dten(&mut self) -> DTEN_W`[src]

Bit 0 - Data transfer enabled bit

`impl W<u32, Reg<u32, _ICR>>`[src]

`pub fn ceataendc(&mut self) -> CEATAENDC_W`[src]

Bit 23 - CEATAEND flag clear bit

`pub fn sdioitc(&mut self) -> SDIOITC_W`[src]

Bit 22 - SDIOIT flag clear bit

`pub fn dbckendc(&mut self) -> DBCKENDC_W`[src]

Bit 10 - DBCKEND flag clear bit

`pub fn stbiterrc(&mut self) -> STBITERRC_W`[src]

Bit 9 - STBITERR flag clear bit

`pub fn dataendc(&mut self) -> DATAENDC_W`[src]

Bit 8 - DATAEND flag clear bit

`pub fn cmdsentc(&mut self) -> CMDSENTC_W`[src]

Bit 7 - CMDSENT flag clear bit

`pub fn cmdrendc(&mut self) -> CMDRENDC_W`[src]

Bit 6 - CMDREND flag clear bit

`pub fn rxoverrc(&mut self) -> RXOVERRC_W`[src]

Bit 5 - RXOVERR flag clear bit

`pub fn txunderrc(&mut self) -> TXUNDERRC_W`[src]

Bit 4 - TXUNDERR flag clear bit

`pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W`[src]

Bit 3 - DTIMEOUT flag clear bit

`pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W`[src]

Bit 2 - CTIMEOUT flag clear bit

`pub fn dcrcfailc(&mut self) -> DCRCFAILC_W`[src]

Bit 1 - DCRCFAIL flag clear bit

`pub fn ccrcfailc(&mut self) -> CCRCFAILC_W`[src]

Bit 0 - CCRCFAIL flag clear bit

`impl W<u32, Reg<u32, _MASK>>`[src]

`pub fn ceataendie(&mut self) -> CEATAENDIE_W`[src]

Bit 23 - CE-ATA command completion signal received interrupt enable

`pub fn sdioitie(&mut self) -> SDIOITIE_W`[src]

Bit 22 - SDIO mode interrupt received interrupt enable

`pub fn rxdavlie(&mut self) -> RXDAVLIE_W`[src]

Bit 21 - Data available in Rx FIFO interrupt enable

`pub fn txdavlie(&mut self) -> TXDAVLIE_W`[src]

Bit 20 - Data available in Tx FIFO interrupt enable

`pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W`[src]

Bit 19 - Rx FIFO empty interrupt enable

`pub fn txfifoeie(&mut self) -> TXFIFOEIE_W`[src]

Bit 18 - Tx FIFO empty interrupt enable

`pub fn rxfifofie(&mut self) -> RXFIFOFIE_W`[src]

Bit 17 - Rx FIFO full interrupt enable

`pub fn txfifofie(&mut self) -> TXFIFOFIE_W`[src]

Bit 16 - Tx FIFO full interrupt enable

`pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W`[src]

Bit 15 - Rx FIFO half full interrupt enable

`pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W`[src]

Bit 14 - Tx FIFO half empty interrupt enable

`pub fn rxactie(&mut self) -> RXACTIE_W`[src]

Bit 13 - Data receive acting interrupt enable

`pub fn txactie(&mut self) -> TXACTIE_W`[src]

Bit 12 - Data transmit acting interrupt enable

`pub fn cmdactie(&mut self) -> CMDACTIE_W`[src]

Bit 11 - Command acting interrupt enable

`pub fn dbckendie(&mut self) -> DBCKENDIE_W`[src]

Bit 10 - Data block end interrupt enable

`pub fn stbiterrie(&mut self) -> STBITERRIE_W`[src]

Bit 9 - Start bit error interrupt enable

`pub fn dataendie(&mut self) -> DATAENDIE_W`[src]

Bit 8 - Data end interrupt enable

`pub fn cmdsentie(&mut self) -> CMDSENTIE_W`[src]

Bit 7 - Command sent interrupt enable

`pub fn cmdrendie(&mut self) -> CMDRENDIE_W`[src]

Bit 6 - Command response received interrupt enable

`pub fn rxoverrie(&mut self) -> RXOVERRIE_W`[src]

Bit 5 - Rx FIFO overrun error interrupt enable

`pub fn txunderrie(&mut self) -> TXUNDERRIE_W`[src]

Bit 4 - Tx FIFO underrun error interrupt enable

`pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W`[src]

Bit 3 - Data timeout interrupt enable

`pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W`[src]

Bit 2 - Command timeout interrupt enable

`pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W`[src]

Bit 1 - Data CRC fail interrupt enable

`pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W`[src]

Bit 0 - Command CRC fail interrupt enable

`impl W<u32, Reg<u32, _FIFO>>`[src]

`pub fn fif0data(&mut self) -> FIF0DATA_W`[src]

Bits 0:31 - FIF0Data

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn bidimode(&mut self) -> BIDIMODE_W`[src]

Bit 15 - Bidirectional data mode enable

`pub fn bidioe(&mut self) -> BIDIOE_W`[src]

Bit 14 - Output enable in bidirectional mode

`pub fn crcen(&mut self) -> CRCEN_W`[src]

Bit 13 - Hardware CRC calculation enable

`pub fn crcnext(&mut self) -> CRCNEXT_W`[src]

Bit 12 - CRC transfer next

`pub fn dff(&mut self) -> DFF_W`[src]

Bit 11 - Data frame format

`pub fn rxonly(&mut self) -> RXONLY_W`[src]

Bit 10 - Receive only

`pub fn ssm(&mut self) -> SSM_W`[src]

Bit 9 - Software slave management

`pub fn ssi(&mut self) -> SSI_W`[src]

Bit 8 - Internal slave select

`pub fn lsbfirst(&mut self) -> LSBFIRST_W`[src]

Bit 7 - Frame format

`pub fn spe(&mut self) -> SPE_W`[src]

Bit 6 - SPI enable

`pub fn br(&mut self) -> BR_W`[src]

Bits 3:5 - Baud rate control

`pub fn mstr(&mut self) -> MSTR_W`[src]

Bit 2 - Master selection

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 1 - Clock polarity

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 0 - Clock phase

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn txeie(&mut self) -> TXEIE_W`[src]

Bit 7 - Tx buffer empty interrupt enable

`pub fn rxneie(&mut self) -> RXNEIE_W`[src]

Bit 6 - RX buffer not empty interrupt enable

`pub fn errie(&mut self) -> ERRIE_W`[src]

Bit 5 - Error interrupt enable

`pub fn frf(&mut self) -> FRF_W`[src]

Bit 4 - Frame format

`pub fn ssoe(&mut self) -> SSOE_W`[src]

Bit 2 - SS output enable

`pub fn txdmaen(&mut self) -> TXDMAEN_W`[src]

Bit 1 - Tx buffer DMA enable

`pub fn rxdmaen(&mut self) -> RXDMAEN_W`[src]

Bit 0 - Rx buffer DMA enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn crcerr(&mut self) -> CRCERR_W`[src]

Bit 4 - CRC error flag

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:15 - Data register

`impl W<u32, Reg<u32, _CRCPR>>`[src]

`pub fn crcpoly(&mut self) -> CRCPOLY_W`[src]

Bits 0:15 - CRC polynomial register

`impl W<u32, Reg<u32, _I2SCFGR>>`[src]

`pub fn i2smod(&mut self) -> I2SMOD_W`[src]

Bit 11 - I2S mode selection

`pub fn i2se(&mut self) -> I2SE_W`[src]

Bit 10 - I2S Enable

`pub fn i2scfg(&mut self) -> I2SCFG_W`[src]

Bits 8:9 - I2S configuration mode

`pub fn pcmsync(&mut self) -> PCMSYNC_W`[src]

Bit 7 - PCM frame synchronization

`pub fn i2sstd(&mut self) -> I2SSTD_W`[src]

Bits 4:5 - I2S standard selection

`pub fn ckpol(&mut self) -> CKPOL_W`[src]

Bit 3 - Steady state clock polarity

`pub fn datlen(&mut self) -> DATLEN_W`[src]

Bits 1:2 - Data length to be transferred

`pub fn chlen(&mut self) -> CHLEN_W`[src]

Bit 0 - Channel length (number of bits per audio channel)

`impl W<u32, Reg<u32, _I2SPR>>`[src]

`pub fn mckoe(&mut self) -> MCKOE_W`[src]

Bit 9 - Master clock output enable

`pub fn odd(&mut self) -> ODD_W`[src]

Bit 8 - Odd factor for the prescaler

`pub fn i2sdiv(&mut self) -> I2SDIV_W`[src]

Bits 0:7 - I2S Linear prescaler

`impl W<u32, Reg<u32, _MEMRMP>>`[src]

`pub fn mem_mode(&mut self) -> MEM_MODE_W`[src]

Bits 0:1 - MEM_MODE

`impl W<u32, Reg<u32, _PMC>>`[src]

`pub fn usb_pu(&mut self) -> USB_PU_W`[src]

Bit 0 - USB pull-up

`pub fn lcd_capa(&mut self) -> LCD_CAPA_W`[src]

Bits 1:5 - decoupling capacitance connection

`impl W<u32, Reg<u32, _EXTICR1>>`[src]

`pub fn exti3(&mut self) -> EXTI3_W`[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

`pub fn exti2(&mut self) -> EXTI2_W`[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

`pub fn exti1(&mut self) -> EXTI1_W`[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

`pub fn exti0(&mut self) -> EXTI0_W`[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

`impl W<u32, Reg<u32, _EXTICR2>>`[src]

`pub fn exti7(&mut self) -> EXTI7_W`[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

`pub fn exti6(&mut self) -> EXTI6_W`[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

`pub fn exti5(&mut self) -> EXTI5_W`[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

`pub fn exti4(&mut self) -> EXTI4_W`[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

`impl W<u32, Reg<u32, _EXTICR3>>`[src]

`pub fn exti11(&mut self) -> EXTI11_W`[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

`pub fn exti10(&mut self) -> EXTI10_W`[src]

Bits 8:11 - EXTI10

`pub fn exti9(&mut self) -> EXTI9_W`[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

`pub fn exti8(&mut self) -> EXTI8_W`[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

`impl W<u32, Reg<u32, _EXTICR4>>`[src]

`pub fn exti15(&mut self) -> EXTI15_W`[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

`pub fn exti14(&mut self) -> EXTI14_W`[src]

Bits 8:11 - EXTI14

`pub fn exti13(&mut self) -> EXTI13_W`[src]

Bits 4:7 - EXTI13

`pub fn exti12(&mut self) -> EXTI12_W`[src]

Bits 0:3 - EXTI12

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM10 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - TIM11 Input 1 remapping capability

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&mut self) -> CMS_W`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Direction

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn ti1s(&mut self) -> TI1S_W`[src]

Bit 7 - TI1 selection

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&mut self) -> CCDS_W`[src]

Bit 3 - Capture/compare DMA selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&mut self) -> ETP_W`[src]

Bit 15 - External trigger polarity

`pub fn ece(&mut self) -> ECE_W`[src]

Bit 14 - External clock enable

`pub fn etps(&mut self) -> ETPS_W`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&mut self) -> ETF_W`[src]

Bits 8:11 - External trigger filter

`pub fn msm(&mut self) -> MSM_W`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&mut self) -> TS_W`[src]

Bits 4:6 - Trigger selection

`pub fn occs(&mut self) -> OCCS_W`[src]

Bit 3 - OCREF clear selection

`pub fn sms(&mut self) -> SMS_W`[src]

Bits 0:2 - Slave mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn tde(&mut self) -> TDE_W`[src]

Bit 14 - Trigger DMA request enable

`pub fn cc4de(&mut self) -> CC4DE_W`[src]

Bit 12 - Capture/Compare 4 DMA request enable

`pub fn cc3de(&mut self) -> CC3DE_W`[src]

Bit 11 - Capture/Compare 3 DMA request enable

`pub fn cc2de(&mut self) -> CC2DE_W`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&mut self) -> CC1DE_W`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&mut self) -> UDE_W`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&mut self) -> TIE_W`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&mut self) -> CC4IE_W`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&mut self) -> CC3IE_W`[src]

Bit 3 - Capture/Compare 3 interrupt enable

`pub fn cc2ie(&mut self) -> CC2IE_W`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc4of(&mut self) -> CC4OF_W`[src]

Bit 12 - Capture/compare 1 overcapture flag

`pub fn cc3of(&mut self) -> CC3OF_W`[src]

Bit 11 - Capture/compare 3 overcapture flag

`pub fn cc2of(&mut self) -> CC2OF_W`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn tif(&mut self) -> TIF_W`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&mut self) -> CC4IF_W`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&mut self) -> CC3IF_W`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&mut self) -> CC2IF_W`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn tg(&mut self) -> TG_W`[src]

Bit 6 - Trigger generation

`pub fn cc4g(&mut self) -> CC4G_W`[src]

Bit 4 - Capture/compare 4 generation

`pub fn cc3g(&mut self) -> CC3G_W`[src]

Bit 3 - Capture/compare 3 generation

`pub fn cc2g(&mut self) -> CC2G_W`[src]

Bit 2 - Capture/compare 2 generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&mut self) -> OC2CE_W`[src]

Bit 15 - Output compare 2 clear enable

`pub fn oc2m(&mut self) -> OC2M_W`[src]

Bits 12:14 - Output compare 2 mode

`pub fn oc2pe(&mut self) -> OC2PE_W`[src]

Bit 11 - Output compare 2 preload enable

`pub fn oc2fe(&mut self) -> OC2FE_W`[src]

Bit 10 - Output compare 2 fast enable

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bit 8 - Capture/Compare 2 selection

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&mut self) -> IC2F_W`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&mut self) -> IC2PSC_W`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&mut self) -> OC4CE_W`[src]

Bit 15 - Output compare 4 clear enable

`pub fn oc4m(&mut self) -> OC4M_W`[src]

Bits 12:14 - Output compare 4 mode

`pub fn oc4pe(&mut self) -> OC4PE_W`[src]

Bit 11 - Output compare 4 preload enable

`pub fn oc4fe(&mut self) -> OC4FE_W`[src]

Bit 10 - Output compare 4 fast enable

`pub fn cc4s(&mut self) -> CC4S_W`[src]

Bit 8 - Capture/Compare 4 selection

`pub fn oc3ce(&mut self) -> OC3CE_W`[src]

Bit 7 - Output compare 3 clear enable

`pub fn oc3m(&mut self) -> OC3M_W`[src]

Bits 4:6 - Output compare 3 mode

`pub fn oc3pe(&mut self) -> OC3PE_W`[src]

Bit 3 - Output compare 3 preload enable

`pub fn oc3fe(&mut self) -> OC3FE_W`[src]

Bit 2 - Output compare 3 fast enable

`pub fn cc3s(&mut self) -> CC3S_W`[src]

Bits 0:1 - Capture/Compare 3 selection

`impl W<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&mut self) -> IC4F_W`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&mut self) -> IC4PSC_W`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&mut self) -> CC4S_W`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&mut self) -> IC3F_W`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&mut self) -> IC3PSC_W`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&mut self) -> CC3S_W`[src]

Bits 0:1 - Capture/compare 3 selection

`impl W<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&mut self) -> CC4NP_W`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&mut self) -> CC4P_W`[src]

Bit 13 - Capture/Compare 4 output Polarity

`pub fn cc4e(&mut self) -> CC4E_W`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&mut self) -> CC3NP_W`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&mut self) -> CC3P_W`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&mut self) -> CC3E_W`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&mut self) -> CC2NP_W`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&mut self) -> CC2P_W`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&mut self) -> CC2E_W`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&mut self) -> CC1NP_W`[src]

Bit 3 - Capture/Compare 1 complementary output Polarity

`pub fn cc1p(&mut self) -> CC1P_W`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&mut self) -> CC1E_W`[src]

Bit 0 - Capture/Compare 1 output enable

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM2 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM2 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&mut self) -> DBL_W`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&mut self) -> DBA_W`[src]

Bits 0:4 - DMA base address

`impl W<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&mut self) -> DMAB_W`[src]

Bits 0:15 - DMA register for burst accesses

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn ude(&mut self) -> UDE_W`[src]

Bit 8 - Update DMA request enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - CNT

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Prescaler value

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&mut self) -> CKD_W`[src]

Bits 8:9 - Clock division

`pub fn arpe(&mut self) -> ARPE_W`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&mut self) -> OPM_W`[src]

Bit 3 - One-pulse mode

`pub fn urs(&mut self) -> URS_W`[src]

Bit 2 - Update request source

`pub fn udis(&mut self) -> UDIS_W`[src]

Bit 1 - Update disable

`pub fn cen(&mut self) -> CEN_W`[src]

Bit 0 - Counter enable

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&mut self) -> MMS_W`[src]

Bits 4:6 - Master mode selection

`impl W<u32, Reg<u32, _SMCR>>`[src]

`pub fn msm(&mut self) -> MSM_W`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&mut self) -> TS_W`[src]

Bits 4:6 - Trigger selection

`pub fn sms(&mut self) -> SMS_W`[src]

Bits 0:2 - Slave mode selection

`impl W<u32, Reg<u32, _DIER>>`[src]

`pub fn tie(&mut self) -> TIE_W`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc2ie(&mut self) -> CC2IE_W`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&mut self) -> CC1IE_W`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&mut self) -> UIE_W`[src]

Bit 0 - Update interrupt enable

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cc2of(&mut self) -> CC2OF_W`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&mut self) -> CC1OF_W`[src]

Bit 9 - Capture/compare 1 overcapture flag

`pub fn tif(&mut self) -> TIF_W`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc2if(&mut self) -> CC2IF_W`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&mut self) -> CC1IF_W`[src]

Bit 1 - Capture/Compare 1 interrupt flag

`pub fn uif(&mut self) -> UIF_W`[src]

Bit 0 - Update interrupt flag

`impl W<u32, Reg<u32, _EGR>>`[src]

`pub fn tg(&mut self) -> TG_W`[src]

Bit 6 - Trigger generation

`pub fn cc2g(&mut self) -> CC2G_W`[src]

Bit 2 - Capture/Compare 2 generation

`pub fn cc1g(&mut self) -> CC1G_W`[src]

Bit 1 - Capture/Compare 1 generation

`pub fn ug(&mut self) -> UG_W`[src]

Bit 0 - Update generation

`impl W<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&mut self) -> OC2CE_W`[src]

Bit 15 - Output compare 2 clear enable

`pub fn oc2m(&mut self) -> OC2M_W`[src]

Bits 12:14 - Output compare 2 mode

`pub fn oc2pe(&mut self) -> OC2PE_W`[src]

Bit 11 - Output compare 2 preload enable

`pub fn oc2fe(&mut self) -> OC2FE_W`[src]

Bit 10 - Output compare 2 fast enable

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bit 8 - Capture/Compare 2 selection

`pub fn oc1ce(&mut self) -> OC1CE_W`[src]

Bit 7 - Output compare 1 clear enable

`pub fn oc1m(&mut self) -> OC1M_W`[src]

Bits 4:6 - Output compare 1 mode

`pub fn oc1pe(&mut self) -> OC1PE_W`[src]

Bit 3 - Output compare 1 preload enable

`pub fn oc1fe(&mut self) -> OC1FE_W`[src]

Bit 2 - Output compare 1 fast enable

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&mut self) -> IC2F_W`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&mut self) -> IC2PSC_W`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&mut self) -> CC2S_W`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&mut self) -> IC1F_W`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&mut self) -> IC1PSC_W`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&mut self) -> CC1S_W`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl W<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&mut self) -> CNT_W`[src]

Bits 0:15 - TIM9 counter

`impl W<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:15 - TIM9 prescaler

`impl W<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&mut self) -> ARR_W`[src]

Bits 0:15 - Auto-reload value

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&mut self) -> CCR_W`[src]

Bits 0:15 - Capture/Compare 1 value

`impl W<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&mut self) -> TI1_RMP_W`[src]

Bits 0:1 - TIM9 Input 1 remapping capability

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 9 - CTS flag

`pub fn lbd(&mut self) -> LBD_W`[src]

Bit 8 - LIN break detection flag

`pub fn tc(&mut self) -> TC_W`[src]

Bit 6 - Transmission complete

`pub fn rxne(&mut self) -> RXNE_W`[src]

Bit 5 - Read data register not empty

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

Bits 0:8 - Data value

`impl W<u32, Reg<u32, _BRR>>`[src]

`pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W`[src]

Bits 4:15 - mantissa of USARTDIV

`pub fn div_fraction(&mut self) -> DIV_FRACTION_W`[src]

Bits 0:3 - fraction of USARTDIV

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn over8(&mut self) -> OVER8_W`[src]

Bit 15 - Oversampling mode

`pub fn ue(&mut self) -> UE_W`[src]

Bit 13 - USART enable

`pub fn m(&mut self) -> M_W`[src]

Bit 12 - Word length

`pub fn wake(&mut self) -> WAKE_W`[src]

Bit 11 - Wakeup method

`pub fn pce(&mut self) -> PCE_W`[src]

Bit 10 - Parity control enable

`pub fn ps(&mut self) -> PS_W`[src]

Bit 9 - Parity selection

`pub fn peie(&mut self) -> PEIE_W`[src]

Bit 8 - PE interrupt enable

`pub fn txeie(&mut self) -> TXEIE_W`[src]

Bit 7 - TXE interrupt enable

`pub fn tcie(&mut self) -> TCIE_W`[src]

Bit 6 - Transmission complete interrupt enable

`pub fn rxneie(&mut self) -> RXNEIE_W`[src]

Bit 5 - RXNE interrupt enable

`pub fn idleie(&mut self) -> IDLEIE_W`[src]

Bit 4 - IDLE interrupt enable

`pub fn te(&mut self) -> TE_W`[src]

Bit 3 - Transmitter enable

`pub fn re(&mut self) -> RE_W`[src]

Bit 2 - Receiver enable

`pub fn rwu(&mut self) -> RWU_W`[src]

Bit 1 - Receiver wakeup

`pub fn sbk(&mut self) -> SBK_W`[src]

Bit 0 - Send break

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn linen(&mut self) -> LINEN_W`[src]

Bit 14 - LIN mode enable

`pub fn stop(&mut self) -> STOP_W`[src]

Bits 12:13 - STOP bits

`pub fn clken(&mut self) -> CLKEN_W`[src]

Bit 11 - Clock enable

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 10 - Clock polarity

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 9 - Clock phase

`pub fn lbcl(&mut self) -> LBCL_W`[src]

Bit 8 - Last bit clock pulse

`pub fn lbdie(&mut self) -> LBDIE_W`[src]

Bit 6 - LIN break detection interrupt enable

`pub fn lbdl(&mut self) -> LBDL_W`[src]

Bit 5 - lin break detection length

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:3 - Address of the USART node

`impl W<u32, Reg<u32, _CR3>>`[src]

`pub fn onebit(&mut self) -> ONEBIT_W`[src]

Bit 11 - One sample bit method enable

`pub fn ctsie(&mut self) -> CTSIE_W`[src]

Bit 10 - CTS interrupt enable

`pub fn ctse(&mut self) -> CTSE_W`[src]

Bit 9 - CTS enable

`pub fn rtse(&mut self) -> RTSE_W`[src]

Bit 8 - RTS enable

`pub fn dmat(&mut self) -> DMAT_W`[src]

Bit 7 - DMA enable transmitter

`pub fn dmar(&mut self) -> DMAR_W`[src]

Bit 6 - DMA enable receiver

`pub fn scen(&mut self) -> SCEN_W`[src]

Bit 5 - Smartcard mode enable

`pub fn nack(&mut self) -> NACK_W`[src]

Bit 4 - Smartcard NACK enable

`pub fn hdsel(&mut self) -> HDSEL_W`[src]

Bit 3 - Half-duplex selection

`pub fn irlp(&mut self) -> IRLP_W`[src]

Bit 2 - IrDA low-power

`pub fn iren(&mut self) -> IREN_W`[src]

Bit 1 - IrDA mode enable

`pub fn eie(&mut self) -> EIE_W`[src]

Bit 0 - Error interrupt enable

`impl W<u32, Reg<u32, _GTPR>>`[src]

`pub fn gt(&mut self) -> GT_W`[src]

Bits 8:15 - Guard time value

`pub fn psc(&mut self) -> PSC_W`[src]

Bits 0:7 - Prescaler value

`impl W<u32, Reg<u32, _EP0R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP1R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP2R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP3R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP4R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP5R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP6R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _EP7R>>`[src]

`pub fn ea(&mut self) -> EA_W`[src]

Bits 0:3 - Endpoint address

`pub fn stat_tx(&mut self) -> STAT_TX_W`[src]

Bits 4:5 - Status bits, for transmission transfers

`pub fn dtog_tx(&mut self) -> DTOG_TX_W`[src]

Bit 6 - Data Toggle, for transmission transfers

`pub fn ctr_tx(&mut self) -> CTR_TX_W`[src]

Bit 7 - Correct Transfer for transmission

`pub fn ep_kind(&mut self) -> EP_KIND_W`[src]

Bit 8 - Endpoint kind

`pub fn ep_type(&mut self) -> EP_TYPE_W`[src]

Bits 9:10 - Endpoint type

`pub fn setup(&mut self) -> SETUP_W`[src]

Bit 11 - Setup transaction completed

`pub fn stat_rx(&mut self) -> STAT_RX_W`[src]

Bits 12:13 - Status bits, for reception transfers

`pub fn dtog_rx(&mut self) -> DTOG_RX_W`[src]

Bit 14 - Data Toggle, for reception transfers

`pub fn ctr_rx(&mut self) -> CTR_RX_W`[src]

Bit 15 - Correct transfer for reception

`impl W<u32, Reg<u32, _CNTR>>`[src]

`pub fn fres(&mut self) -> FRES_W`[src]

Bit 0 - Force USB Reset

`pub fn pdwn(&mut self) -> PDWN_W`[src]

Bit 1 - Power down

`pub fn lpmode(&mut self) -> LPMODE_W`[src]

Bit 2 - Low-power mode

`pub fn fsusp(&mut self) -> FSUSP_W`[src]

Bit 3 - Force suspend

`pub fn resume(&mut self) -> RESUME_W`[src]

Bit 4 - Resume request

`pub fn esofm(&mut self) -> ESOFM_W`[src]

Bit 8 - Expected start of frame interrupt mask

`pub fn sofm(&mut self) -> SOFM_W`[src]

Bit 9 - Start of frame interrupt mask

`pub fn resetm(&mut self) -> RESETM_W`[src]

Bit 10 - USB reset interrupt mask

`pub fn suspm(&mut self) -> SUSPM_W`[src]

Bit 11 - Suspend mode interrupt mask

`pub fn wkupm(&mut self) -> WKUPM_W`[src]

Bit 12 - Wakeup interrupt mask

`pub fn errm(&mut self) -> ERRM_W`[src]

Bit 13 - Error interrupt mask

`pub fn pmaovrm(&mut self) -> PMAOVRM_W`[src]

Bit 14 - Packet memory area over / underrun interrupt mask

`pub fn ctrm(&mut self) -> CTRM_W`[src]

Bit 15 - Correct transfer interrupt mask

`impl W<u32, Reg<u32, _ISTR>>`[src]

`pub fn ep_id(&mut self) -> EP_ID_W`[src]

Bits 0:3 - Endpoint Identifier

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 4 - Direction of transaction

`pub fn esof(&mut self) -> ESOF_W`[src]

Bit 8 - Expected start frame

`pub fn sof(&mut self) -> SOF_W`[src]

Bit 9 - start of frame

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 10 - reset request

`pub fn susp(&mut self) -> SUSP_W`[src]

Bit 11 - Suspend mode request

`pub fn wkup(&mut self) -> WKUP_W`[src]

Bit 12 - Wakeup

`pub fn err(&mut self) -> ERR_W`[src]

Bit 13 - Error

`pub fn pmaovr(&mut self) -> PMAOVR_W`[src]

Bit 14 - Packet memory area over / underrun

`pub fn ctr(&mut self) -> CTR_W`[src]

Bit 15 - Correct transfer

`impl W<u32, Reg<u32, _DADDR>>`[src]

`pub fn add(&mut self) -> ADD_W`[src]

Bits 0:6 - Device address

`pub fn ef(&mut self) -> EF_W`[src]

Bit 7 - Enable function

`impl W<u32, Reg<u32, _BTABLE>>`[src]

`pub fn btable(&mut self) -> BTABLE_W`[src]

Bits 3:15 - Buffer table

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn wdga(&mut self) -> WDGA_W`[src]

Bit 7 - Activation bit

`pub fn t(&mut self) -> T_W`[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

`impl W<u32, Reg<u32, _CFR>>`[src]

`pub fn ewi(&mut self) -> EWI_W`[src]

Bit 9 - Early wakeup interrupt

`pub fn w(&mut self) -> W_W`[src]

Bits 0:6 - 7-bit window value

`pub fn wdgtb(&mut self) -> WDGTB_W`[src]

Bits 7:8 - Timer base

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn ewif(&mut self) -> EWIF_W`[src]

Bit 0 - EWIF

`impl W<u32, Reg<u32, _SR>>`[src]

`pub fn ovr(&mut self) -> OVR_W`[src]

Bit 5 - Overrun

`pub fn strt(&mut self) -> STRT_W`[src]

Bit 4 - Regular channel start flag

`pub fn jstrt(&mut self) -> JSTRT_W`[src]

Bit 3 - Injected channel start flag

`pub fn jeoc(&mut self) -> JEOC_W`[src]

Bit 2 - Injected channel end of conversion

`pub fn eoc(&mut self) -> EOC_W`[src]

Bit 1 - Regular channel end of conversion

`pub fn awd(&mut self) -> AWD_W`[src]

Bit 0 - Analog watchdog flag

`impl W<u32, Reg<u32, _CR1>>`[src]

`pub fn ovrie(&mut self) -> OVRIE_W`[src]

Bit 26 - Overrun interrupt enable

`pub fn res(&mut self) -> RES_W`[src]

Bits 24:25 - Resolution

`pub fn awden(&mut self) -> AWDEN_W`[src]

Bit 23 - Analog watchdog enable on regular channels

`pub fn jawden(&mut self) -> JAWDEN_W`[src]

Bit 22 - Analog watchdog enable on injected channels

`pub fn pdi(&mut self) -> PDI_W`[src]

Bit 17 - Power down during the idle phase

`pub fn pdd(&mut self) -> PDD_W`[src]

Bit 16 - Power down during the delay phase

`pub fn discnum(&mut self) -> DISCNUM_W`[src]

Bits 13:15 - Discontinuous mode channel count

`pub fn jdiscen(&mut self) -> JDISCEN_W`[src]

Bit 12 - Discontinuous mode on injected channels

`pub fn discen(&mut self) -> DISCEN_W`[src]

Bit 11 - Discontinuous mode on regular channels

`pub fn jauto(&mut self) -> JAUTO_W`[src]

Bit 10 - Automatic injected group conversion

`pub fn awdsgl(&mut self) -> AWDSGL_W`[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

`pub fn scan(&mut self) -> SCAN_W`[src]

Bit 8 - Scan mode

`pub fn jeocie(&mut self) -> JEOCIE_W`[src]

Bit 7 - Interrupt enable for injected channels

`pub fn awdie(&mut self) -> AWDIE_W`[src]

Bit 6 - Analog watchdog interrupt enable

`pub fn eocie(&mut self) -> EOCIE_W`[src]

Bit 5 - Interrupt enable for EOC

`pub fn awdch(&mut self) -> AWDCH_W`[src]

Bits 0:4 - Analog watchdog channel select bits

`impl W<u32, Reg<u32, _CR2>>`[src]

`pub fn swstart(&mut self) -> SWSTART_W`[src]

Bit 30 - Start conversion of regular channels

`pub fn exten(&mut self) -> EXTEN_W`[src]

Bits 28:29 - External trigger enable for regular channels

`pub fn extsel(&mut self) -> EXTSEL_W`[src]

Bits 24:27 - External event select for regular group

`pub fn jswstart(&mut self) -> JSWSTART_W`[src]

Bit 22 - Start conversion of injected channels

`pub fn jexten(&mut self) -> JEXTEN_W`[src]

Bits 20:21 - External trigger enable for injected channels

`pub fn jextsel(&mut self) -> JEXTSEL_W`[src]

Bits 16:19 - External event select for injected group

`pub fn align(&mut self) -> ALIGN_W`[src]

Bit 11 - Data alignment

`pub fn eocs(&mut self) -> EOCS_W`[src]

Bit 10 - End of conversion selection

`pub fn dds(&mut self) -> DDS_W`[src]

Bit 9 - DMA disable selection

`pub fn dma(&mut self) -> DMA_W`[src]

Bit 8 - Direct memory access mode

`pub fn dels(&mut self) -> DELS_W`[src]

Bits 4:6 - Delay selection

`pub fn adc_cfg(&mut self) -> ADC_CFG_W`[src]

Bit 2 - ADC configuration

`pub fn cont(&mut self) -> CONT_W`[src]

Bit 1 - Continuous conversion

`pub fn adon(&mut self) -> ADON_W`[src]

Bit 0 - A/D Converter ON / OFF

`impl W<u32, Reg<u32, _SMPR1>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel sampling time selection

`impl W<u32, Reg<u32, _SMPR2>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel sampling time selection

`impl W<u32, Reg<u32, _SMPR3>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:29 - Channel Sample time selection

`impl W<u32, Reg<u32, _JOFR1>>`[src]

`pub fn joffset1(&mut self) -> JOFFSET1_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR2>>`[src]

`pub fn joffset2(&mut self) -> JOFFSET2_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR3>>`[src]

`pub fn joffset3(&mut self) -> JOFFSET3_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _JOFR4>>`[src]

`pub fn joffset4(&mut self) -> JOFFSET4_W`[src]

Bits 0:11 - Data offset for injected channel x

`impl W<u32, Reg<u32, _HTR>>`[src]

`pub fn ht(&mut self) -> HT_W`[src]

Bits 0:11 - Analog watchdog higher threshold

`impl W<u32, Reg<u32, _LTR>>`[src]

`pub fn lt(&mut self) -> LT_W`[src]

Bits 0:11 - Analog watchdog lower threshold

`impl W<u32, Reg<u32, _SQR1>>`[src]

`pub fn l(&mut self) -> L_W`[src]

Bits 20:23 - Regular channel sequence length

`pub fn sq28(&mut self) -> SQ28_W`[src]

Bits 15:19 - 28th conversion in regular sequence

`pub fn sq27(&mut self) -> SQ27_W`[src]

Bits 10:14 - 27th conversion in regular sequence

`pub fn sq26(&mut self) -> SQ26_W`[src]

Bits 5:9 - 26th conversion in regular sequence

`pub fn sq25(&mut self) -> SQ25_W`[src]

Bits 0:4 - 25th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR2>>`[src]

`pub fn sq24(&mut self) -> SQ24_W`[src]

Bits 25:29 - 24th conversion in regular sequence

`pub fn sq23(&mut self) -> SQ23_W`[src]

Bits 20:24 - 23rd conversion in regular sequence

`pub fn sq22(&mut self) -> SQ22_W`[src]

Bits 15:19 - 22nd conversion in regular sequence

`pub fn sq21(&mut self) -> SQ21_W`[src]

Bits 10:14 - 21st conversion in regular sequence

`pub fn sq20(&mut self) -> SQ20_W`[src]

Bits 5:9 - 20th conversion in regular sequence

`pub fn sq19(&mut self) -> SQ19_W`[src]

Bits 0:4 - 19th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR3>>`[src]

`pub fn sq18(&mut self) -> SQ18_W`[src]

Bits 25:29 - 18th conversion in regular sequence

`pub fn sq17(&mut self) -> SQ17_W`[src]

Bits 20:24 - 17th conversion in regular sequence

`pub fn sq16(&mut self) -> SQ16_W`[src]

Bits 15:19 - 16th conversion in regular sequence

`pub fn sq15(&mut self) -> SQ15_W`[src]

Bits 10:14 - 15th conversion in regular sequence

`pub fn sq14(&mut self) -> SQ14_W`[src]

Bits 5:9 - 14th conversion in regular sequence

`pub fn sq13(&mut self) -> SQ13_W`[src]

Bits 0:4 - 13th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR4>>`[src]

`pub fn sq12(&mut self) -> SQ12_W`[src]

Bits 25:29 - 12th conversion in regular sequence

`pub fn sq11(&mut self) -> SQ11_W`[src]

Bits 20:24 - 11th conversion in regular sequence

`pub fn sq10(&mut self) -> SQ10_W`[src]

Bits 15:19 - 10th conversion in regular sequence

`pub fn sq9(&mut self) -> SQ9_W`[src]

Bits 10:14 - 9th conversion in regular sequence

`pub fn sq8(&mut self) -> SQ8_W`[src]

Bits 5:9 - 8th conversion in regular sequence

`pub fn sq7(&mut self) -> SQ7_W`[src]

Bits 0:4 - 7th conversion in regular sequence

`impl W<u32, Reg<u32, _SQR5>>`[src]

`pub fn sq6(&mut self) -> SQ6_W`[src]

Bits 25:29 - 6th conversion in regular sequence

`pub fn sq5(&mut self) -> SQ5_W`[src]

Bits 20:24 - 5th conversion in regular sequence

`pub fn sq4(&mut self) -> SQ4_W`[src]

Bits 15:19 - 4th conversion in regular sequence

`pub fn sq3(&mut self) -> SQ3_W`[src]

Bits 10:14 - 3rd conversion in regular sequence

`pub fn sq2(&mut self) -> SQ2_W`[src]

Bits 5:9 - 2nd conversion in regular sequence

`pub fn sq1(&mut self) -> SQ1_W`[src]

Bits 0:4 - 1st conversion in regular sequence

`impl W<u32, Reg<u32, _JSQR>>`[src]

`pub fn jl(&mut self) -> JL_W`[src]

Bits 20:21 - Injected sequence length

`pub fn jsq4(&mut self) -> JSQ4_W`[src]

Bits 15:19 - 4th conversion in injected sequence

`pub fn jsq3(&mut self) -> JSQ3_W`[src]

Bits 10:14 - 3rd conversion in injected sequence

`pub fn jsq2(&mut self) -> JSQ2_W`[src]

Bits 5:9 - 2nd conversion in injected sequence

`pub fn jsq1(&mut self) -> JSQ1_W`[src]

Bits 0:4 - 1st conversion in injected sequence

`impl W<u32, Reg<u32, _SMPR0>>`[src]

`pub fn smp(&mut self) -> SMP_W`[src]

Bits 0:5 - Channel Sample time selection

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn adcpre(&mut self) -> ADCPRE_W`[src]

Bits 16:17 - ADC prescaler

`pub fn tsvrefe(&mut self) -> TSVREFE_W`[src]

Bit 23 - Temperature sensor and VREFINT enable

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W`[src]

Bit 0 - Debug Sleep mode

`pub fn dbg_stop(&mut self) -> DBG_STOP_W`[src]

Bit 1 - Debug Stop mode

`pub fn dbg_standby(&mut self) -> DBG_STANDBY_W`[src]

Bit 2 - Debug Standby mode

`pub fn trace_ioen(&mut self) -> TRACE_IOEN_W`[src]

Bit 5 - Trace pin assignment control

`pub fn trace_mode(&mut self) -> TRACE_MODE_W`[src]

Bits 6:7 - Trace pin assignment control

`impl W<u32, Reg<u32, _APB1_FZ>>`[src]

`pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W`[src]

Bit 0 - TIM2 counter stopped when core is halted

`pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W`[src]

Bit 1 - TIM3 counter stopped when core is halted

`pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W`[src]

Bit 2 - TIM4 counter stopped when core is halted

`pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W`[src]

Bit 3 - TIM5 counter stopped when core is halted

`pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W`[src]

Bit 4 - TIM6 counter stopped when core is halted

`pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W`[src]

Bit 5 - TIM7 counter stopped when core is halted

`pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W`[src]

Bit 10 - Debug RTC stopped when core is halted

`pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W`[src]

Bit 11 - Debug window watchdog stopped when core is halted

`pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W`[src]

Bit 12 - Debug independent watchdog stopped when core is halted

`pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W`[src]

Bit 21 - SMBUS timeout mode stopped when core is halted

`pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W`[src]

Bit 22 - SMBUS timeout mode stopped when core is halted

`impl W<u32, Reg<u32, _APB2_FZ>>`[src]

`pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W`[src]

Bit 2 - TIM counter stopped when core is halted

`pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W`[src]

Bit 3 - TIM counter stopped when core is halted

`pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W`[src]

Bit 4 - TIM counter stopped when core is halted

`impl W<u32, Reg<u32, _ACTRL>>`[src]

`pub fn disfold(&mut self) -> DISFOLD_W`[src]

Bit 2 - DISFOLD

`pub fn fpexcodis(&mut self) -> FPEXCODIS_W`[src]

Bit 10 - FPEXCODIS

`pub fn disramode(&mut self) -> DISRAMODE_W`[src]

Bit 11 - DISRAMODE

`pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W`[src]

Bit 12 - DISITMATBFLUSH

`impl W<u32, Reg<u32, _STIR>>`[src]

`pub fn intid(&mut self) -> INTID_W`[src]

Bits 0:8 - Software generated interrupt ID

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Counter enable

`pub fn tickint(&mut self) -> TICKINT_W`[src]

Bit 1 - SysTick exception request enable

`pub fn clksource(&mut self) -> CLKSOURCE_W`[src]

Bit 2 - Clock source selection

`pub fn countflag(&mut self) -> COUNTFLAG_W`[src]

Bit 16 - COUNTFLAG

`impl W<u32, Reg<u32, _LOAD_>>`[src]

`pub fn reload(&mut self) -> RELOAD_W`[src]

Bits 0:23 - RELOAD value

`impl W<u32, Reg<u32, _VAL>>`[src]

`pub fn current(&mut self) -> CURRENT_W`[src]

Bits 0:23 - Current counter value

`impl W<u32, Reg<u32, _CALIB>>`[src]

`pub fn tenms(&mut self) -> TENMS_W`[src]

Bits 0:23 - Calibration value

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,`

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,`

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Same<T> for T`

`type Output = T`

Should always be Self

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct stm32l1::W

Methods

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

impl W<u32, Reg<u32, _CR>>[src]

pub fn dmaouten(&mut self) -> DMAOUTEN_W[src]

pub fn dmainen(&mut self) -> DMAINEN_W[src]

pub fn errie(&mut self) -> ERRIE_W[src]

pub fn ccfie(&mut self) -> CCFIE_W[src]

pub fn errc(&mut self) -> ERRC_W[src]

pub fn ccfc(&mut self) -> CCFC_W[src]

pub fn chmod(&mut self) -> CHMOD_W[src]

pub fn mode(&mut self) -> MODE_W[src]

pub fn datatype(&mut self) -> DATATYPE_W[src]

pub fn en(&mut self) -> EN_W[src]

impl W<u32, Reg<u32, _DINR>>[src]

pub fn dinr(&mut self) -> DINR_W[src]

impl W<u32, Reg<u32, _KEYR0>>[src]

pub fn keyr0(&mut self) -> KEYR0_W[src]

impl W<u32, Reg<u32, _KEYR1>>[src]

pub fn keyr1(&mut self) -> KEYR1_W[src]

impl W<u32, Reg<u32, _KEYR2>>[src]

pub fn keyr2(&mut self) -> KEYR2_W[src]

impl W<u32, Reg<u32, _KEYR3>>[src]

pub fn keyr3(&mut self) -> KEYR3_W[src]

impl W<u32, Reg<u32, _IVR0>>[src]

pub fn ivr0(&mut self) -> IVR0_W[src]

impl W<u32, Reg<u32, _IVR1>>[src]

pub fn ivr1(&mut self) -> IVR1_W[src]

impl W<u32, Reg<u32, _IVR2>>[src]

pub fn ivr2(&mut self) -> IVR2_W[src]

impl W<u32, Reg<u32, _IVR3>>[src]

pub fn ivr3(&mut self) -> IVR3_W[src]

impl W<u32, Reg<u32, _CSR>>[src]

pub fn tsusp(&mut self) -> TSUSP_W[src]

pub fn caie(&mut self) -> CAIE_W[src]

pub fn rch13(&mut self) -> RCH13_W[src]

pub fn fch8(&mut self) -> FCH8_W[src]

pub fn fch3(&mut self) -> FCH3_W[src]

pub fn outsel(&mut self) -> OUTSEL_W[src]

pub fn insel(&mut self) -> INSEL_W[src]

pub fn wndwe(&mut self) -> WNDWE_W[src]

pub fn vrefouten(&mut self) -> VREFOUTEN_W[src]

pub fn speed(&mut self) -> SPEED_W[src]

pub fn sw1(&mut self) -> SW1_W[src]

pub fn cmp1en(&mut self) -> CMP1EN_W[src]

pub fn pd400k(&mut self) -> PD400K_W[src]

pub fn pd10k(&mut self) -> PD10K_W[src]

pub fn pu400k(&mut self) -> PU400K_W[src]

pub fn pu10k(&mut self) -> PU10K_W[src]

impl W<u32, Reg<u32, _DR>>[src]

pub fn dr(&mut self) -> DR_W[src]

impl W<u32, Reg<u32, _IDR>>[src]

pub fn idr(&mut self) -> IDR_W[src]

impl W<u32, Reg<u32, _CR>>[src]

pub fn reset(&mut self) -> RESET_W[src]

impl W<u32, Reg<u32, _CR>>[src]

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W[src]

pub fn dmaen2(&mut self) -> DMAEN2_W[src]

pub fn mamp2(&mut self) -> MAMP2_W[src]

pub fn wave2(&mut self) -> WAVE2_W[src]

pub fn tsel2(&mut self) -> TSEL2_W[src]

pub fn ten2(&mut self) -> TEN2_W[src]

pub fn boff2(&mut self) -> BOFF2_W[src]

pub fn en2(&mut self) -> EN2_W[src]

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W[src]

pub fn dmaen1(&mut self) -> DMAEN1_W[src]

pub fn mamp1(&mut self) -> MAMP1_W[src]

pub fn wave1(&mut self) -> WAVE1_W[src]

pub fn tsel1(&mut self) -> TSEL1_W[src]

pub fn ten1(&mut self) -> TEN1_W[src]

pub fn boff1(&mut self) -> BOFF1_W[src]

pub fn en1(&mut self) -> EN1_W[src]

impl W<u32, Reg<u32, _SWTRIGR>>[src]

pub fn swtrig2(&mut self) -> SWTRIG2_W[src]

pub fn swtrig1(&mut self) -> SWTRIG1_W[src]

impl W<u32, Reg<u32, _DHR12R1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W[src]

impl W<u32, Reg<u32, _DHR12L1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W[src]

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaouten(&mut self) -> DMAOUTEN_W`[src]

`pub fn dmainen(&mut self) -> DMAINEN_W`[src]

`pub fn errie(&mut self) -> ERRIE_W`[src]

`pub fn ccfie(&mut self) -> CCFIE_W`[src]

`pub fn errc(&mut self) -> ERRC_W`[src]

`pub fn ccfc(&mut self) -> CCFC_W`[src]

`pub fn chmod(&mut self) -> CHMOD_W`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

`pub fn datatype(&mut self) -> DATATYPE_W`[src]

`pub fn en(&mut self) -> EN_W`[src]

`impl W<u32, Reg<u32, _DINR>>`[src]

`pub fn dinr(&mut self) -> DINR_W`[src]

`impl W<u32, Reg<u32, _KEYR0>>`[src]

`pub fn keyr0(&mut self) -> KEYR0_W`[src]

`impl W<u32, Reg<u32, _KEYR1>>`[src]

`pub fn keyr1(&mut self) -> KEYR1_W`[src]

`impl W<u32, Reg<u32, _KEYR2>>`[src]

`pub fn keyr2(&mut self) -> KEYR2_W`[src]

`impl W<u32, Reg<u32, _KEYR3>>`[src]

`pub fn keyr3(&mut self) -> KEYR3_W`[src]

`impl W<u32, Reg<u32, _IVR0>>`[src]

`pub fn ivr0(&mut self) -> IVR0_W`[src]

`impl W<u32, Reg<u32, _IVR1>>`[src]

`pub fn ivr1(&mut self) -> IVR1_W`[src]

`impl W<u32, Reg<u32, _IVR2>>`[src]

`pub fn ivr2(&mut self) -> IVR2_W`[src]

`impl W<u32, Reg<u32, _IVR3>>`[src]

`pub fn ivr3(&mut self) -> IVR3_W`[src]

`impl W<u32, Reg<u32, _CSR>>`[src]

`pub fn tsusp(&mut self) -> TSUSP_W`[src]

`pub fn caie(&mut self) -> CAIE_W`[src]

`pub fn rch13(&mut self) -> RCH13_W`[src]

`pub fn fch8(&mut self) -> FCH8_W`[src]

`pub fn fch3(&mut self) -> FCH3_W`[src]

`pub fn outsel(&mut self) -> OUTSEL_W`[src]

`pub fn insel(&mut self) -> INSEL_W`[src]

`pub fn wndwe(&mut self) -> WNDWE_W`[src]

`pub fn vrefouten(&mut self) -> VREFOUTEN_W`[src]

`pub fn speed(&mut self) -> SPEED_W`[src]

`pub fn sw1(&mut self) -> SW1_W`[src]

`pub fn cmp1en(&mut self) -> CMP1EN_W`[src]

`pub fn pd400k(&mut self) -> PD400K_W`[src]

`pub fn pd10k(&mut self) -> PD10K_W`[src]

`pub fn pu400k(&mut self) -> PU400K_W`[src]

`pub fn pu10k(&mut self) -> PU10K_W`[src]

`impl W<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&mut self) -> DR_W`[src]

`impl W<u32, Reg<u32, _IDR>>`[src]

`pub fn idr(&mut self) -> IDR_W`[src]

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn reset(&mut self) -> RESET_W`[src]

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W`[src]

`pub fn dmaen2(&mut self) -> DMAEN2_W`[src]

`pub fn mamp2(&mut self) -> MAMP2_W`[src]

`pub fn wave2(&mut self) -> WAVE2_W`[src]

`pub fn tsel2(&mut self) -> TSEL2_W`[src]

`pub fn ten2(&mut self) -> TEN2_W`[src]

`pub fn boff2(&mut self) -> BOFF2_W`[src]

`pub fn en2(&mut self) -> EN2_W`[src]

`pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W`[src]

`pub fn dmaen1(&mut self) -> DMAEN1_W`[src]

`pub fn mamp1(&mut self) -> MAMP1_W`[src]

`pub fn wave1(&mut self) -> WAVE1_W`[src]

`pub fn tsel1(&mut self) -> TSEL1_W`[src]

`pub fn ten1(&mut self) -> TEN1_W`[src]

`pub fn boff1(&mut self) -> BOFF1_W`[src]

`pub fn en1(&mut self) -> EN1_W`[src]

`impl W<u32, Reg<u32, _SWTRIGR>>`[src]

`pub fn swtrig2(&mut self) -> SWTRIG2_W`[src]

`pub fn swtrig1(&mut self) -> SWTRIG1_W`[src]

`impl W<u32, Reg<u32, _DHR12R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

`impl W<u32, Reg<u32, _DHR12L1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]

`impl W<u32, Reg<u32, _DHR8R1>>`[src]

`pub fn dacc1dhr(&mut self) -> DACC1DHR_W`[src]