stm32l0x1/syscfg_comp/cfgr1/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CFGR1 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct BOOT_MODER {
47    bits: u8,
48}
49impl BOOT_MODER {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct MEM_MODER {
58    bits: u8,
59}
60impl MEM_MODER {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bits(&self) -> u8 {
64        self.bits
65    }
66}
67#[doc = r" Proxy"]
68pub struct _MEM_MODEW<'a> {
69    w: &'a mut W,
70}
71impl<'a> _MEM_MODEW<'a> {
72    #[doc = r" Writes raw bits to the field"]
73    #[inline]
74    pub unsafe fn bits(self, value: u8) -> &'a mut W {
75        const MASK: u8 = 3;
76        const OFFSET: u8 = 0;
77        self.w.bits &= !((MASK as u32) << OFFSET);
78        self.w.bits |= ((value & MASK) as u32) << OFFSET;
79        self.w
80    }
81}
82impl R {
83    #[doc = r" Value of the register as raw bits"]
84    #[inline]
85    pub fn bits(&self) -> u32 {
86        self.bits
87    }
88    #[doc = "Bits 8:9 - Boot mode selected by the boot pins status bits"]
89    #[inline]
90    pub fn boot_mode(&self) -> BOOT_MODER {
91        let bits = {
92            const MASK: u8 = 3;
93            const OFFSET: u8 = 8;
94            ((self.bits >> OFFSET) & MASK as u32) as u8
95        };
96        BOOT_MODER { bits }
97    }
98    #[doc = "Bits 0:1 - Memory mapping selection bits"]
99    #[inline]
100    pub fn mem_mode(&self) -> MEM_MODER {
101        let bits = {
102            const MASK: u8 = 3;
103            const OFFSET: u8 = 0;
104            ((self.bits >> OFFSET) & MASK as u32) as u8
105        };
106        MEM_MODER { bits }
107    }
108}
109impl W {
110    #[doc = r" Reset value of the register"]
111    #[inline]
112    pub fn reset_value() -> W {
113        W { bits: 0 }
114    }
115    #[doc = r" Writes raw bits to the register"]
116    #[inline]
117    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
118        self.bits = bits;
119        self
120    }
121    #[doc = "Bits 0:1 - Memory mapping selection bits"]
122    #[inline]
123    pub fn mem_mode(&mut self) -> _MEM_MODEW {
124        _MEM_MODEW { w: self }
125    }
126}
stm32l0x1/syscfg_comp/cfgr1/mod.rs

stm32l0x1/syscfg_comp/cfgr1/
mod.rs
