stm32l0/stm32l0x3/tsc/
iogcsr.rs

1///Register `IOGCSR` reader
2pub type R = crate::R<IOGCSRrs>;
3///Register `IOGCSR` writer
4pub type W = crate::W<IOGCSRrs>;
5/**Analog I/O group x enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum G1E {
11    ///0: Acquisition on analog I/O group x disabled
12    Disabled = 0,
13    ///1: Acquisition on analog I/O group x enabled
14    Enabled = 1,
15}
16impl From<G1E> for bool {
17    #[inline(always)]
18    fn from(variant: G1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `GE(1-8)` reader - Analog I/O group x enable
23pub type GE_R = crate::BitReader<G1E>;
24impl GE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> G1E {
28        match self.bits {
29            false => G1E::Disabled,
30            true => G1E::Enabled,
31        }
32    }
33    ///Acquisition on analog I/O group x disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == G1E::Disabled
37    }
38    ///Acquisition on analog I/O group x enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == G1E::Enabled
42    }
43}
44///Field `GE(1-8)` writer - Analog I/O group x enable
45pub type GE_W<'a, REG> = crate::BitWriter<'a, REG, G1E>;
46impl<'a, REG> GE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Acquisition on analog I/O group x disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(G1E::Disabled)
54    }
55    ///Acquisition on analog I/O group x enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(G1E::Enabled)
59    }
60}
61/**Analog I/O group x status
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum G1S {
67    ///0: Acquisition on analog I/O group x is ongoing or not started
68    Ongoing = 0,
69    ///1: Acquisition on analog I/O group x is complete
70    Complete = 1,
71}
72impl From<G1S> for bool {
73    #[inline(always)]
74    fn from(variant: G1S) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `GS(1-8)` reader - Analog I/O group x status
79pub type GS_R = crate::BitReader<G1S>;
80impl GS_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> G1S {
84        match self.bits {
85            false => G1S::Ongoing,
86            true => G1S::Complete,
87        }
88    }
89    ///Acquisition on analog I/O group x is ongoing or not started
90    #[inline(always)]
91    pub fn is_ongoing(&self) -> bool {
92        *self == G1S::Ongoing
93    }
94    ///Acquisition on analog I/O group x is complete
95    #[inline(always)]
96    pub fn is_complete(&self) -> bool {
97        *self == G1S::Complete
98    }
99}
100impl R {
101    ///Analog I/O group x enable
102    ///
103    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `G1E` field.</div>
104    #[inline(always)]
105    pub fn ge(&self, n: u8) -> GE_R {
106        #[allow(clippy::no_effect)]
107        [(); 8][n as usize];
108        GE_R::new(((self.bits >> n) & 1) != 0)
109    }
110    ///Iterator for array of:
111    ///Analog I/O group x enable
112    #[inline(always)]
113    pub fn ge_iter(&self) -> impl Iterator<Item = GE_R> + '_ {
114        (0..8).map(move |n| GE_R::new(((self.bits >> n) & 1) != 0))
115    }
116    ///Bit 0 - Analog I/O group x enable
117    #[inline(always)]
118    pub fn g1e(&self) -> GE_R {
119        GE_R::new((self.bits & 1) != 0)
120    }
121    ///Bit 1 - Analog I/O group x enable
122    #[inline(always)]
123    pub fn g2e(&self) -> GE_R {
124        GE_R::new(((self.bits >> 1) & 1) != 0)
125    }
126    ///Bit 2 - Analog I/O group x enable
127    #[inline(always)]
128    pub fn g3e(&self) -> GE_R {
129        GE_R::new(((self.bits >> 2) & 1) != 0)
130    }
131    ///Bit 3 - Analog I/O group x enable
132    #[inline(always)]
133    pub fn g4e(&self) -> GE_R {
134        GE_R::new(((self.bits >> 3) & 1) != 0)
135    }
136    ///Bit 4 - Analog I/O group x enable
137    #[inline(always)]
138    pub fn g5e(&self) -> GE_R {
139        GE_R::new(((self.bits >> 4) & 1) != 0)
140    }
141    ///Bit 5 - Analog I/O group x enable
142    #[inline(always)]
143    pub fn g6e(&self) -> GE_R {
144        GE_R::new(((self.bits >> 5) & 1) != 0)
145    }
146    ///Bit 6 - Analog I/O group x enable
147    #[inline(always)]
148    pub fn g7e(&self) -> GE_R {
149        GE_R::new(((self.bits >> 6) & 1) != 0)
150    }
151    ///Bit 7 - Analog I/O group x enable
152    #[inline(always)]
153    pub fn g8e(&self) -> GE_R {
154        GE_R::new(((self.bits >> 7) & 1) != 0)
155    }
156    ///Analog I/O group x status
157    ///
158    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `G1S` field.</div>
159    #[inline(always)]
160    pub fn gs(&self, n: u8) -> GS_R {
161        #[allow(clippy::no_effect)]
162        [(); 8][n as usize];
163        GS_R::new(((self.bits >> (n + 16)) & 1) != 0)
164    }
165    ///Iterator for array of:
166    ///Analog I/O group x status
167    #[inline(always)]
168    pub fn gs_iter(&self) -> impl Iterator<Item = GS_R> + '_ {
169        (0..8).map(move |n| GS_R::new(((self.bits >> (n + 16)) & 1) != 0))
170    }
171    ///Bit 16 - Analog I/O group x status
172    #[inline(always)]
173    pub fn g1s(&self) -> GS_R {
174        GS_R::new(((self.bits >> 16) & 1) != 0)
175    }
176    ///Bit 17 - Analog I/O group x status
177    #[inline(always)]
178    pub fn g2s(&self) -> GS_R {
179        GS_R::new(((self.bits >> 17) & 1) != 0)
180    }
181    ///Bit 18 - Analog I/O group x status
182    #[inline(always)]
183    pub fn g3s(&self) -> GS_R {
184        GS_R::new(((self.bits >> 18) & 1) != 0)
185    }
186    ///Bit 19 - Analog I/O group x status
187    #[inline(always)]
188    pub fn g4s(&self) -> GS_R {
189        GS_R::new(((self.bits >> 19) & 1) != 0)
190    }
191    ///Bit 20 - Analog I/O group x status
192    #[inline(always)]
193    pub fn g5s(&self) -> GS_R {
194        GS_R::new(((self.bits >> 20) & 1) != 0)
195    }
196    ///Bit 21 - Analog I/O group x status
197    #[inline(always)]
198    pub fn g6s(&self) -> GS_R {
199        GS_R::new(((self.bits >> 21) & 1) != 0)
200    }
201    ///Bit 22 - Analog I/O group x status
202    #[inline(always)]
203    pub fn g7s(&self) -> GS_R {
204        GS_R::new(((self.bits >> 22) & 1) != 0)
205    }
206    ///Bit 23 - Analog I/O group x status
207    #[inline(always)]
208    pub fn g8s(&self) -> GS_R {
209        GS_R::new(((self.bits >> 23) & 1) != 0)
210    }
211}
212impl core::fmt::Debug for R {
213    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
214        f.debug_struct("IOGCSR")
215            .field("g1s", &self.g1s())
216            .field("g2s", &self.g2s())
217            .field("g3s", &self.g3s())
218            .field("g4s", &self.g4s())
219            .field("g5s", &self.g5s())
220            .field("g6s", &self.g6s())
221            .field("g7s", &self.g7s())
222            .field("g8s", &self.g8s())
223            .field("g1e", &self.g1e())
224            .field("g2e", &self.g2e())
225            .field("g3e", &self.g3e())
226            .field("g4e", &self.g4e())
227            .field("g5e", &self.g5e())
228            .field("g6e", &self.g6e())
229            .field("g7e", &self.g7e())
230            .field("g8e", &self.g8e())
231            .finish()
232    }
233}
234impl W {
235    ///Analog I/O group x enable
236    ///
237    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `G1E` field.</div>
238    #[inline(always)]
239    pub fn ge(&mut self, n: u8) -> GE_W<IOGCSRrs> {
240        #[allow(clippy::no_effect)]
241        [(); 8][n as usize];
242        GE_W::new(self, n)
243    }
244    ///Bit 0 - Analog I/O group x enable
245    #[inline(always)]
246    pub fn g1e(&mut self) -> GE_W<IOGCSRrs> {
247        GE_W::new(self, 0)
248    }
249    ///Bit 1 - Analog I/O group x enable
250    #[inline(always)]
251    pub fn g2e(&mut self) -> GE_W<IOGCSRrs> {
252        GE_W::new(self, 1)
253    }
254    ///Bit 2 - Analog I/O group x enable
255    #[inline(always)]
256    pub fn g3e(&mut self) -> GE_W<IOGCSRrs> {
257        GE_W::new(self, 2)
258    }
259    ///Bit 3 - Analog I/O group x enable
260    #[inline(always)]
261    pub fn g4e(&mut self) -> GE_W<IOGCSRrs> {
262        GE_W::new(self, 3)
263    }
264    ///Bit 4 - Analog I/O group x enable
265    #[inline(always)]
266    pub fn g5e(&mut self) -> GE_W<IOGCSRrs> {
267        GE_W::new(self, 4)
268    }
269    ///Bit 5 - Analog I/O group x enable
270    #[inline(always)]
271    pub fn g6e(&mut self) -> GE_W<IOGCSRrs> {
272        GE_W::new(self, 5)
273    }
274    ///Bit 6 - Analog I/O group x enable
275    #[inline(always)]
276    pub fn g7e(&mut self) -> GE_W<IOGCSRrs> {
277        GE_W::new(self, 6)
278    }
279    ///Bit 7 - Analog I/O group x enable
280    #[inline(always)]
281    pub fn g8e(&mut self) -> GE_W<IOGCSRrs> {
282        GE_W::new(self, 7)
283    }
284}
285/**I/O group control status register
286
287You can [`read`](crate::Reg::read) this register and get [`iogcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iogcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
288
289See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x3.html#TSC:IOGCSR)*/
290pub struct IOGCSRrs;
291impl crate::RegisterSpec for IOGCSRrs {
292    type Ux = u32;
293}
294///`read()` method returns [`iogcsr::R`](R) reader structure
295impl crate::Readable for IOGCSRrs {}
296///`write(|w| ..)` method takes [`iogcsr::W`](W) writer structure
297impl crate::Writable for IOGCSRrs {
298    type Safety = crate::Unsafe;
299}
300///`reset()` method sets IOGCSR to value 0
301impl crate::Resettable for IOGCSRrs {}
stm32l0/stm32l0x3/tsc/iogcsr.rs

stm32l0/stm32l0x3/tsc/
iogcsr.rs
