#[doc = "Register `MODER` reader"]
pub struct R(crate::R<MODER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MODER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MODER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MODER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MODER` writer"]
pub struct W(crate::W<MODER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MODER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MODER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MODER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE15_A = MODE0_A;
#[doc = "Field `MODE15` reader - Port x configuration bits (y = 0..15)"]
pub type MODE15_R = MODE0_R;
#[doc = "Field `MODE15` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE15_W<'a> {
w: &'a mut W,
}
impl<'a> MODE15_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE15_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE15_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE15_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE15_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE15_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE14_A = MODE0_A;
#[doc = "Field `MODE14` reader - Port x configuration bits (y = 0..15)"]
pub type MODE14_R = MODE0_R;
#[doc = "Field `MODE14` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE14_W<'a> {
w: &'a mut W,
}
impl<'a> MODE14_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE14_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE14_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE14_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE14_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE14_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE13_A = MODE0_A;
#[doc = "Field `MODE13` reader - Port x configuration bits (y = 0..15)"]
pub type MODE13_R = MODE0_R;
#[doc = "Field `MODE13` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE13_W<'a> {
w: &'a mut W,
}
impl<'a> MODE13_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE13_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE13_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE13_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE13_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE13_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE12_A = MODE0_A;
#[doc = "Field `MODE12` reader - Port x configuration bits (y = 0..15)"]
pub type MODE12_R = MODE0_R;
#[doc = "Field `MODE12` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE12_W<'a> {
w: &'a mut W,
}
impl<'a> MODE12_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE12_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE12_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE12_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE12_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE12_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE11_A = MODE0_A;
#[doc = "Field `MODE11` reader - Port x configuration bits (y = 0..15)"]
pub type MODE11_R = MODE0_R;
#[doc = "Field `MODE11` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE11_W<'a> {
w: &'a mut W,
}
impl<'a> MODE11_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE11_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE11_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE11_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE11_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE11_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE10_A = MODE0_A;
#[doc = "Field `MODE10` reader - Port x configuration bits (y = 0..15)"]
pub type MODE10_R = MODE0_R;
#[doc = "Field `MODE10` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE10_W<'a> {
w: &'a mut W,
}
impl<'a> MODE10_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE10_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE10_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE10_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE10_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE10_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE9_A = MODE0_A;
#[doc = "Field `MODE9` reader - Port x configuration bits (y = 0..15)"]
pub type MODE9_R = MODE0_R;
#[doc = "Field `MODE9` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE9_W<'a> {
w: &'a mut W,
}
impl<'a> MODE9_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE9_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE9_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE9_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE9_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE9_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE8_A = MODE0_A;
#[doc = "Field `MODE8` reader - Port x configuration bits (y = 0..15)"]
pub type MODE8_R = MODE0_R;
#[doc = "Field `MODE8` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE8_W<'a> {
w: &'a mut W,
}
impl<'a> MODE8_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE8_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE8_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE8_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE8_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE8_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE7_A = MODE0_A;
#[doc = "Field `MODE7` reader - Port x configuration bits (y = 0..15)"]
pub type MODE7_R = MODE0_R;
#[doc = "Field `MODE7` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE7_W<'a> {
w: &'a mut W,
}
impl<'a> MODE7_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE7_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE7_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE7_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE7_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE7_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE6_A = MODE0_A;
#[doc = "Field `MODE6` reader - Port x configuration bits (y = 0..15)"]
pub type MODE6_R = MODE0_R;
#[doc = "Field `MODE6` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE6_W<'a> {
w: &'a mut W,
}
impl<'a> MODE6_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE6_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE6_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE6_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE6_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE6_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE5_A = MODE0_A;
#[doc = "Field `MODE5` reader - Port x configuration bits (y = 0..15)"]
pub type MODE5_R = MODE0_R;
#[doc = "Field `MODE5` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE5_W<'a> {
w: &'a mut W,
}
impl<'a> MODE5_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE5_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE5_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE5_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE5_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE5_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE4_A = MODE0_A;
#[doc = "Field `MODE4` reader - Port x configuration bits (y = 0..15)"]
pub type MODE4_R = MODE0_R;
#[doc = "Field `MODE4` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE4_W<'a> {
w: &'a mut W,
}
impl<'a> MODE4_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE4_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE4_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE4_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE4_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE4_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE3_A = MODE0_A;
#[doc = "Field `MODE3` reader - Port x configuration bits (y = 0..15)"]
pub type MODE3_R = MODE0_R;
#[doc = "Field `MODE3` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE3_W<'a> {
w: &'a mut W,
}
impl<'a> MODE3_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE3_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE3_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE3_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE3_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE3_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE2_A = MODE0_A;
#[doc = "Field `MODE2` reader - Port x configuration bits (y = 0..15)"]
pub type MODE2_R = MODE0_R;
#[doc = "Field `MODE2` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE2_W<'a> {
w: &'a mut W,
}
impl<'a> MODE2_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE2_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE2_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE2_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE2_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE2_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type MODE1_A = MODE0_A;
#[doc = "Field `MODE1` reader - Port x configuration bits (y = 0..15)"]
pub type MODE1_R = MODE0_R;
#[doc = "Field `MODE1` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE1_W<'a> {
w: &'a mut W,
}
impl<'a> MODE1_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE1_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE1_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE1_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE1_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE1_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)\n\nValue on reset: 3"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum MODE0_A {
#[doc = "0: Input mode (reset state)"]
INPUT = 0,
#[doc = "1: General purpose output mode"]
OUTPUT = 1,
#[doc = "2: Alternate function mode"]
ALTERNATE = 2,
#[doc = "3: Analog mode"]
ANALOG = 3,
}
impl From<MODE0_A> for u8 {
#[inline(always)]
fn from(variant: MODE0_A) -> Self {
variant as _
}
}
#[doc = "Field `MODE0` reader - Port x configuration bits (y = 0..15)"]
pub struct MODE0_R(crate::FieldReader<u8, MODE0_A>);
impl MODE0_R {
pub(crate) fn new(bits: u8) -> Self {
MODE0_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> MODE0_A {
match self.bits {
0 => MODE0_A::INPUT,
1 => MODE0_A::OUTPUT,
2 => MODE0_A::ALTERNATE,
3 => MODE0_A::ANALOG,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `INPUT`"]
#[inline(always)]
pub fn is_input(&self) -> bool {
**self == MODE0_A::INPUT
}
#[doc = "Checks if the value of the field is `OUTPUT`"]
#[inline(always)]
pub fn is_output(&self) -> bool {
**self == MODE0_A::OUTPUT
}
#[doc = "Checks if the value of the field is `ALTERNATE`"]
#[inline(always)]
pub fn is_alternate(&self) -> bool {
**self == MODE0_A::ALTERNATE
}
#[doc = "Checks if the value of the field is `ANALOG`"]
#[inline(always)]
pub fn is_analog(&self) -> bool {
**self == MODE0_A::ANALOG
}
}
impl core::ops::Deref for MODE0_R {
type Target = crate::FieldReader<u8, MODE0_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `MODE0` writer - Port x configuration bits (y = 0..15)"]
pub struct MODE0_W<'a> {
w: &'a mut W,
}
impl<'a> MODE0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MODE0_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(MODE0_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(MODE0_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(MODE0_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(MODE0_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
self.w
}
}
impl R {
#[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode15(&self) -> MODE15_R {
MODE15_R::new(((self.bits >> 30) & 0x03) as u8)
}
#[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode14(&self) -> MODE14_R {
MODE14_R::new(((self.bits >> 28) & 0x03) as u8)
}
#[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode13(&self) -> MODE13_R {
MODE13_R::new(((self.bits >> 26) & 0x03) as u8)
}
#[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode12(&self) -> MODE12_R {
MODE12_R::new(((self.bits >> 24) & 0x03) as u8)
}
#[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode11(&self) -> MODE11_R {
MODE11_R::new(((self.bits >> 22) & 0x03) as u8)
}
#[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode10(&self) -> MODE10_R {
MODE10_R::new(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode9(&self) -> MODE9_R {
MODE9_R::new(((self.bits >> 18) & 0x03) as u8)
}
#[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode8(&self) -> MODE8_R {
MODE8_R::new(((self.bits >> 16) & 0x03) as u8)
}
#[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode7(&self) -> MODE7_R {
MODE7_R::new(((self.bits >> 14) & 0x03) as u8)
}
#[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode6(&self) -> MODE6_R {
MODE6_R::new(((self.bits >> 12) & 0x03) as u8)
}
#[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode5(&self) -> MODE5_R {
MODE5_R::new(((self.bits >> 10) & 0x03) as u8)
}
#[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode4(&self) -> MODE4_R {
MODE4_R::new(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode3(&self) -> MODE3_R {
MODE3_R::new(((self.bits >> 6) & 0x03) as u8)
}
#[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode2(&self) -> MODE2_R {
MODE2_R::new(((self.bits >> 4) & 0x03) as u8)
}
#[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode1(&self) -> MODE1_R {
MODE1_R::new(((self.bits >> 2) & 0x03) as u8)
}
#[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode0(&self) -> MODE0_R {
MODE0_R::new((self.bits & 0x03) as u8)
}
}
impl W {
#[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode15(&mut self) -> MODE15_W {
MODE15_W { w: self }
}
#[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode14(&mut self) -> MODE14_W {
MODE14_W { w: self }
}
#[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode13(&mut self) -> MODE13_W {
MODE13_W { w: self }
}
#[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode12(&mut self) -> MODE12_W {
MODE12_W { w: self }
}
#[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode11(&mut self) -> MODE11_W {
MODE11_W { w: self }
}
#[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode10(&mut self) -> MODE10_W {
MODE10_W { w: self }
}
#[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode9(&mut self) -> MODE9_W {
MODE9_W { w: self }
}
#[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode8(&mut self) -> MODE8_W {
MODE8_W { w: self }
}
#[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode7(&mut self) -> MODE7_W {
MODE7_W { w: self }
}
#[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode6(&mut self) -> MODE6_W {
MODE6_W { w: self }
}
#[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode5(&mut self) -> MODE5_W {
MODE5_W { w: self }
}
#[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode4(&mut self) -> MODE4_W {
MODE4_W { w: self }
}
#[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode3(&mut self) -> MODE3_W {
MODE3_W { w: self }
}
#[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode2(&mut self) -> MODE2_W {
MODE2_W { w: self }
}
#[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode1(&mut self) -> MODE1_W {
MODE1_W { w: self }
}
#[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn mode0(&mut self) -> MODE0_W {
MODE0_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "GPIO port mode register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [moder](index.html) module"]
pub struct MODER_SPEC;
impl crate::RegisterSpec for MODER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [moder::R](R) reader structure"]
impl crate::Readable for MODER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [moder::W](W) writer structure"]
impl crate::Writable for MODER_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets MODER to value 0xffff_ffff"]
impl crate::Resettable for MODER_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0xffff_ffff
}
}