Struct stm32h7xx_hal::stm32::ethernet_mac::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 90 fields
    pub maccr: Reg<MACCR_SPEC>,
    pub macecr: Reg<MACECR_SPEC>,
    pub macpfr: Reg<MACPFR_SPEC>,
    pub macwtr: Reg<MACWTR_SPEC>,
    pub macht0r: Reg<MACHT0R_SPEC>,
    pub macht1r: Reg<MACHT1R_SPEC>,
    pub macvtr: Reg<MACVTR_SPEC>,
    pub macvhtr: Reg<MACVHTR_SPEC>,
    pub macvir: Reg<MACVIR_SPEC>,
    pub macivir: Reg<MACIVIR_SPEC>,
    pub macqtx_fcr: Reg<MACQTXFCR_SPEC>,
    pub macrx_fcr: Reg<MACRXFCR_SPEC>,
    pub macisr: Reg<MACISR_SPEC>,
    pub macier: Reg<MACIER_SPEC>,
    pub macrx_tx_sr: Reg<MACRXTXSR_SPEC>,
    pub macpcsr: Reg<MACPCSR_SPEC>,
    pub macrwkpfr: Reg<MACRWKPFR_SPEC>,
    pub maclcsr: Reg<MACLCSR_SPEC>,
    pub macltcr: Reg<MACLTCR_SPEC>,
    pub macletr: Reg<MACLETR_SPEC>,
    pub mac1ustcr: Reg<MAC1USTCR_SPEC>,
    pub macvr: Reg<MACVR_SPEC>,
    pub macdr: Reg<MACDR_SPEC>,
    pub machwf1r: Reg<MACHWF1R_SPEC>,
    pub machwf2r: Reg<MACHWF2R_SPEC>,
    pub macmdioar: Reg<MACMDIOAR_SPEC>,
    pub macmdiodr: Reg<MACMDIODR_SPEC>,
    pub maca0hr: Reg<MACA0HR_SPEC>,
    pub maca0lr: Reg<MACA0LR_SPEC>,
    pub maca1hr: Reg<MACA1HR_SPEC>,
    pub maca1lr: Reg<MACA1LR_SPEC>,
    pub maca2hr: Reg<MACA2HR_SPEC>,
    pub maca2lr: Reg<MACA2LR_SPEC>,
    pub maca3hr: Reg<MACA3HR_SPEC>,
    pub maca3lr: Reg<MACA3LR_SPEC>,
    pub mmc_control: Reg<MMC_CONTROL_SPEC>,
    pub mmc_rx_interrupt: Reg<MMC_RX_INTERRUPT_SPEC>,
    pub mmc_tx_interrupt: Reg<MMC_TX_INTERRUPT_SPEC>,
    pub mmc_rx_interrupt_mask: Reg<MMC_RX_INTERRUPT_MASK_SPEC>,
    pub mmc_tx_interrupt_mask: Reg<MMC_TX_INTERRUPT_MASK_SPEC>,
    pub tx_single_collision_good_packets: Reg<TX_SINGLE_COLLISION_GOOD_PACKETS_SPEC>,
    pub tx_multiple_collision_good_packets: Reg<TX_MULTIPLE_COLLISION_GOOD_PACKETS_SPEC>,
    pub tx_packet_count_good: Reg<TX_PACKET_COUNT_GOOD_SPEC>,
    pub rx_crc_error_packets: Reg<RX_CRC_ERROR_PACKETS_SPEC>,
    pub rx_alignment_error_packets: Reg<RX_ALIGNMENT_ERROR_PACKETS_SPEC>,
    pub rx_unicast_packets_good: Reg<RX_UNICAST_PACKETS_GOOD_SPEC>,
    pub tx_lpi_usec_cntr: Reg<TX_LPI_USEC_CNTR_SPEC>,
    pub tx_lpi_tran_cntr: Reg<TX_LPI_TRAN_CNTR_SPEC>,
    pub rx_lpi_usec_cntr: Reg<RX_LPI_USEC_CNTR_SPEC>,
    pub rx_lpi_tran_cntr: Reg<RX_LPI_TRAN_CNTR_SPEC>,
    pub macl3l4c0r: Reg<MACL3L4C0R_SPEC>,
    pub macl4a0r: Reg<MACL4A0R_SPEC>,
    pub macl3a00r: Reg<MACL3A00R_SPEC>,
    pub macl3a10r: Reg<MACL3A10R_SPEC>,
    pub macl3a20: Reg<MACL3A20_SPEC>,
    pub macl3a30: Reg<MACL3A30_SPEC>,
    pub macl3l4c1r: Reg<MACL3L4C1R_SPEC>,
    pub macl4a1r: Reg<MACL4A1R_SPEC>,
    pub macl3a01r: Reg<MACL3A01R_SPEC>,
    pub macl3a11r: Reg<MACL3A11R_SPEC>,
    pub macl3a21r: Reg<MACL3A21R_SPEC>,
    pub macl3a31r: Reg<MACL3A31R_SPEC>,
    pub macarpar: Reg<MACARPAR_SPEC>,
    pub mactscr: Reg<MACTSCR_SPEC>,
    pub macssir: Reg<MACSSIR_SPEC>,
    pub macstsr: Reg<MACSTSR_SPEC>,
    pub macstnr: Reg<MACSTNR_SPEC>,
    pub macstsur: Reg<MACSTSUR_SPEC>,
    pub macstnur: Reg<MACSTNUR_SPEC>,
    pub mactsar: Reg<MACTSAR_SPEC>,
    pub mactssr: Reg<MACTSSR_SPEC>,
    pub mactx_tssnr: Reg<MACTXTSSNR_SPEC>,
    pub mactx_tsssr: Reg<MACTXTSSSR_SPEC>,
    pub macacr: Reg<MACACR_SPEC>,
    pub macatsnr: Reg<MACATSNR_SPEC>,
    pub macatssr: Reg<MACATSSR_SPEC>,
    pub mactsiacr: Reg<MACTSIACR_SPEC>,
    pub mactseacr: Reg<MACTSEACR_SPEC>,
    pub mactsicnr: Reg<MACTSICNR_SPEC>,
    pub mactsecnr: Reg<MACTSECNR_SPEC>,
    pub macppscr: Reg<MACPPSCR_SPEC>,
    pub macppsttsr: Reg<MACPPSTTSR_SPEC>,
    pub macppsttnr: Reg<MACPPSTTNR_SPEC>,
    pub macppsir: Reg<MACPPSIR_SPEC>,
    pub macppswr: Reg<MACPPSWR_SPEC>,
    pub macpocr: Reg<MACPOCR_SPEC>,
    pub macspi0r: Reg<MACSPI0R_SPEC>,
    pub macspi1r: Reg<MACSPI1R_SPEC>,
    pub macspi2r: Reg<MACSPI2R_SPEC>,
    pub maclmir: Reg<MACLMIR_SPEC>,
    /* private fields */
}

Expand description

Register block

Fields§

§maccr: Reg<MACCR_SPEC>

0x00 - Operating mode configuration register

§macecr: Reg<MACECR_SPEC>

0x04 - Extended operating mode configuration register

§macpfr: Reg<MACPFR_SPEC>

0x08 - Packet filtering control register

§macwtr: Reg<MACWTR_SPEC>

0x0c - Watchdog timeout register

§macht0r: Reg<MACHT0R_SPEC>

0x10 - Hash Table 0 register

§macht1r: Reg<MACHT1R_SPEC>

0x14 - Hash Table 1 register

§macvtr: Reg<MACVTR_SPEC>

0x50 - VLAN tag register

§macvhtr: Reg<MACVHTR_SPEC>

0x58 - VLAN Hash table register

§macvir: Reg<MACVIR_SPEC>

0x60 - VLAN inclusion register

§macivir: Reg<MACIVIR_SPEC>

0x64 - Inner VLAN inclusion register

§macqtx_fcr: Reg<MACQTXFCR_SPEC>

0x70 - Tx Queue flow control register

§macrx_fcr: Reg<MACRXFCR_SPEC>

0x90 - Rx flow control register

§macisr: Reg<MACISR_SPEC>

0xb0 - Interrupt status register

§macier: Reg<MACIER_SPEC>

0xb4 - Interrupt enable register

§macrx_tx_sr: Reg<MACRXTXSR_SPEC>

0xb8 - Rx Tx status register

§macpcsr: Reg<MACPCSR_SPEC>

0xc0 - PMT control status register

§macrwkpfr: Reg<MACRWKPFR_SPEC>

0xc4 - Remove wakeup packet filter register

§maclcsr: Reg<MACLCSR_SPEC>

0xd0 - LPI control status register

§macltcr: Reg<MACLTCR_SPEC>

0xd4 - LPI timers control register

§macletr: Reg<MACLETR_SPEC>

0xd8 - LPI entry timer register

§mac1ustcr: Reg<MAC1USTCR_SPEC>

0xdc - 1-microsecond-tick counter register

§macvr: Reg<MACVR_SPEC>

0x110 - Version register

§macdr: Reg<MACDR_SPEC>

0x114 - Debug register

§machwf1r: Reg<MACHWF1R_SPEC>

0x120 - HW feature 1 register

§machwf2r: Reg<MACHWF2R_SPEC>

0x124 - HW feature 2 register

§macmdioar: Reg<MACMDIOAR_SPEC>

0x200 - MDIO address register

§macmdiodr: Reg<MACMDIODR_SPEC>

0x204 - MDIO data register

§maca0hr: Reg<MACA0HR_SPEC>

0x300 - Address 0 high register

§maca0lr: Reg<MACA0LR_SPEC>

0x304 - Address 0 low register

§maca1hr: Reg<MACA1HR_SPEC>

0x308 - Address 1 high register

§maca1lr: Reg<MACA1LR_SPEC>

0x30c - Address 1 low register

§maca2hr: Reg<MACA2HR_SPEC>

0x310 - Address 2 high register

§maca2lr: Reg<MACA2LR_SPEC>

0x314 - Address 2 low register

§maca3hr: Reg<MACA3HR_SPEC>

0x318 - Address 3 high register

§maca3lr: Reg<MACA3LR_SPEC>

0x31c - Address 3 low register

§mmc_control: Reg<MMC_CONTROL_SPEC>

0x700 - MMC control register

§mmc_rx_interrupt: Reg<MMC_RX_INTERRUPT_SPEC>

0x704 - MMC Rx interrupt register

§mmc_tx_interrupt: Reg<MMC_TX_INTERRUPT_SPEC>

0x708 - MMC Tx interrupt register

§mmc_rx_interrupt_mask: Reg<MMC_RX_INTERRUPT_MASK_SPEC>

0x70c - MMC Rx interrupt mask register

§mmc_tx_interrupt_mask: Reg<MMC_TX_INTERRUPT_MASK_SPEC>

0x710 - MMC Tx interrupt mask register

§tx_single_collision_good_packets: Reg<TX_SINGLE_COLLISION_GOOD_PACKETS_SPEC>

0x74c - Tx single collision good packets register

§tx_multiple_collision_good_packets: Reg<TX_MULTIPLE_COLLISION_GOOD_PACKETS_SPEC>

0x750 - Tx multiple collision good packets register

§tx_packet_count_good: Reg<TX_PACKET_COUNT_GOOD_SPEC>

0x768 - Tx packet count good register

§rx_crc_error_packets: Reg<RX_CRC_ERROR_PACKETS_SPEC>

0x794 - Rx CRC error packets register

§rx_alignment_error_packets: Reg<RX_ALIGNMENT_ERROR_PACKETS_SPEC>

0x798 - Rx alignment error packets register

§rx_unicast_packets_good: Reg<RX_UNICAST_PACKETS_GOOD_SPEC>

0x7c4 - Rx unicast packets good register

§tx_lpi_usec_cntr: Reg<TX_LPI_USEC_CNTR_SPEC>

0x7ec - Tx LPI microsecond timer register

§tx_lpi_tran_cntr: Reg<TX_LPI_TRAN_CNTR_SPEC>

0x7f0 - Tx LPI transition counter register

§rx_lpi_usec_cntr: Reg<RX_LPI_USEC_CNTR_SPEC>

0x7f4 - Rx LPI microsecond counter register

§rx_lpi_tran_cntr: Reg<RX_LPI_TRAN_CNTR_SPEC>

0x7f8 - Rx LPI transition counter register

§macl3l4c0r: Reg<MACL3L4C0R_SPEC>

0x900 - L3 and L4 control 0 register

§macl4a0r: Reg<MACL4A0R_SPEC>

0x904 - Layer4 address filter 0 register

§macl3a00r: Reg<MACL3A00R_SPEC>

0x910 - MACL3A00R

§macl3a10r: Reg<MACL3A10R_SPEC>

0x914 - Layer3 address 1 filter 0 register

§macl3a20: Reg<MACL3A20_SPEC>

0x918 - Layer3 Address 2 filter 0 register

§macl3a30: Reg<MACL3A30_SPEC>

0x91c - Layer3 Address 3 filter 0 register

§macl3l4c1r: Reg<MACL3L4C1R_SPEC>

0x930 - L3 and L4 control 1 register

§macl4a1r: Reg<MACL4A1R_SPEC>

0x934 - Layer 4 address filter 1 register

§macl3a01r: Reg<MACL3A01R_SPEC>

0x940 - Layer3 address 0 filter 1 Register

§macl3a11r: Reg<MACL3A11R_SPEC>

0x944 - Layer3 address 1 filter 1 register

§macl3a21r: Reg<MACL3A21R_SPEC>

0x948 - Layer3 address 2 filter 1 Register

§macl3a31r: Reg<MACL3A31R_SPEC>

0x94c - Layer3 address 3 filter 1 register

§macarpar: Reg<MACARPAR_SPEC>

0xae0 - ARP address register

§mactscr: Reg<MACTSCR_SPEC>

0xb00 - Timestamp control Register

§macssir: Reg<MACSSIR_SPEC>

0xb04 - Sub-second increment register

§macstsr: Reg<MACSTSR_SPEC>

0xb08 - System time seconds register

§macstnr: Reg<MACSTNR_SPEC>

0xb0c - System time nanoseconds register

§macstsur: Reg<MACSTSUR_SPEC>

0xb10 - System time seconds update register

§macstnur: Reg<MACSTNUR_SPEC>

0xb14 - System time nanoseconds update register

§mactsar: Reg<MACTSAR_SPEC>

0xb18 - Timestamp addend register

§mactssr: Reg<MACTSSR_SPEC>

0xb20 - Timestamp status register

§mactx_tssnr: Reg<MACTXTSSNR_SPEC>

0xb30 - Tx timestamp status nanoseconds register

§mactx_tsssr: Reg<MACTXTSSSR_SPEC>

0xb34 - Tx timestamp status seconds register

§macacr: Reg<MACACR_SPEC>

0xb40 - Auxiliary control register

§macatsnr: Reg<MACATSNR_SPEC>

0xb48 - Auxiliary timestamp nanoseconds register

§macatssr: Reg<MACATSSR_SPEC>

0xb4c - Auxiliary timestamp seconds register

§mactsiacr: Reg<MACTSIACR_SPEC>

0xb50 - Timestamp Ingress asymmetric correction register

§mactseacr: Reg<MACTSEACR_SPEC>

0xb54 - Timestamp Egress asymmetric correction register

§mactsicnr: Reg<MACTSICNR_SPEC>

0xb58 - Timestamp Ingress correction nanosecond register

§mactsecnr: Reg<MACTSECNR_SPEC>

0xb5c - Timestamp Egress correction nanosecond register

§macppscr: Reg<MACPPSCR_SPEC>

0xb70 - PPS control register

§macppsttsr: Reg<MACPPSTTSR_SPEC>

0xb80 - PPS target time seconds register

§macppsttnr: Reg<MACPPSTTNR_SPEC>

0xb84 - PPS target time nanoseconds register

§macppsir: Reg<MACPPSIR_SPEC>

0xb88 - PPS interval register

§macppswr: Reg<MACPPSWR_SPEC>

0xb8c - PPS width register

§macpocr: Reg<MACPOCR_SPEC>

0xbc0 - PTP Offload control register

§macspi0r: Reg<MACSPI0R_SPEC>

0xbc4 - PTP Source Port Identity 0 Register

§macspi1r: Reg<MACSPI1R_SPEC>

0xbc8 - PTP Source port identity 1 register

§macspi2r: Reg<MACSPI2R_SPEC>

0xbcc - PTP Source port identity 2 register

§maclmir: Reg<MACLMIR_SPEC>

0xbd0 - Log message interval register

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

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impl<T> BorrowMut<T> for T
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fn borrow_mut(&mut self) -> &mut T

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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom for T
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type Error = Infallible

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fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for T
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type Error = >::Error

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fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct stm32h7xx_hal::stm32::ethernet_mac::RegisterBlock

Fields§

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct stm32h7xx_hal::stm32::ethernet_mac::RegisterBlock

Fields§

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<T> Any for T
where T: 'static + ?Sized,

impl<T> Borrow<T> for T
where T: ?Sized,

impl<T> BorrowMut<T> for T
where T: ?Sized,

impl<T, U> Into<U> for T
where U: From<T>,

impl<T, U> TryFrom<U> for T
where U: Into<T>,

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,