pub enum TXIS_A {
NotEmpty = 0,
Empty = 1,
}
Expand description
Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0.
Value on reset: 0
Variants§
NotEmpty = 0
0: The TXDR register is not empty
Empty = 1
1: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Trait Implementations§
source§impl PartialEq for TXIS_A
impl PartialEq for TXIS_A
impl Copy for TXIS_A
impl StructuralPartialEq for TXIS_A
Auto Trait Implementations§
impl Freeze for TXIS_A
impl RefUnwindSafe for TXIS_A
impl Send for TXIS_A
impl Sync for TXIS_A
impl Unpin for TXIS_A
impl UnwindSafe for TXIS_A
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more