Struct stm32h7xx_hal::device::quadspi::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 13 fields
    pub cr: Reg<CR_SPEC>,
    pub dcr: Reg<DCR_SPEC>,
    pub sr: Reg<SR_SPEC>,
    pub fcr: Reg<FCR_SPEC>,
    pub dlr: Reg<DLR_SPEC>,
    pub ccr: Reg<CCR_SPEC>,
    pub ar: Reg<AR_SPEC>,
    pub abr: Reg<ABR_SPEC>,
    pub dr: Reg<DR_SPEC>,
    pub psmkr: Reg<PSMKR_SPEC>,
    pub psmar: Reg<PSMAR_SPEC>,
    pub pir: Reg<PIR_SPEC>,
    pub lptr: Reg<LPTR_SPEC>,

}
Expand description

Register block

Fields§

§cr: Reg<CR_SPEC>

0x00 - QUADSPI control register

§dcr: Reg<DCR_SPEC>

0x04 - QUADSPI device configuration register

§sr: Reg<SR_SPEC>

0x08 - QUADSPI status register

§fcr: Reg<FCR_SPEC>

0x0c - QUADSPI flag clear register

§dlr: Reg<DLR_SPEC>

0x10 - QUADSPI data length register

§ccr: Reg<CCR_SPEC>

0x14 - QUADSPI communication configuration register

§ar: Reg<AR_SPEC>

0x18 - QUADSPI address register

§abr: Reg<ABR_SPEC>

0x1c - QUADSPI alternate bytes registers

§dr: Reg<DR_SPEC>

0x20 - QUADSPI data register

§psmkr: Reg<PSMKR_SPEC>

0x24 - QUADSPI polling status mask register

§psmar: Reg<PSMAR_SPEC>

0x28 - QUADSPI polling status match register

§pir: Reg<PIR_SPEC>

0x2c - QUADSPI polling interval register

§lptr: Reg<LPTR_SPEC>

0x30 - QUADSPI low-power timeout register

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