stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231

///Register `PRESC` reader
pub type R = crate::R<PRESCrs>;
///Register `PRESC` writer
pub type W = crate::W<PRESCrs>;
/**Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PRESCALER {
    ///0: Input clock divided by 1
    Div1 = 0,
    ///1: Input clock divided by 2
    Div2 = 1,
    ///2: Input clock divided by 4
    Div4 = 2,
    ///3: Input clock divided by 6
    Div6 = 3,
    ///4: Input clock divided by 8
    Div8 = 4,
    ///5: Input clock divided by 10
    Div10 = 5,
    ///6: Input clock divided by 12
    Div12 = 6,
    ///7: Input clock divided by 16
    Div16 = 7,
    ///8: Input clock divided by 32
    Div32 = 8,
    ///9: Input clock divided by 64
    Div64 = 9,
    ///10: Input clock divided by 128
    Div128 = 10,
    ///11: Input clock divided by 256
    Div256 = 11,
}
impl From<PRESCALER> for u8 {
    #[inline(always)]
    fn from(variant: PRESCALER) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for PRESCALER {
    type Ux = u8;
}
impl crate::IsEnum for PRESCALER {}
///Field `PRESCALER` reader - Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256.
pub type PRESCALER_R = crate::FieldReader<PRESCALER>;
impl PRESCALER_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<PRESCALER> {
        match self.bits {
            0 => Some(PRESCALER::Div1),
            1 => Some(PRESCALER::Div2),
            2 => Some(PRESCALER::Div4),
            3 => Some(PRESCALER::Div6),
            4 => Some(PRESCALER::Div8),
            5 => Some(PRESCALER::Div10),
            6 => Some(PRESCALER::Div12),
            7 => Some(PRESCALER::Div16),
            8 => Some(PRESCALER::Div32),
            9 => Some(PRESCALER::Div64),
            10 => Some(PRESCALER::Div128),
            11 => Some(PRESCALER::Div256),
            _ => None,
        }
    }
    ///Input clock divided by 1
    #[inline(always)]
    pub fn is_div1(&self) -> bool {
        *self == PRESCALER::Div1
    }
    ///Input clock divided by 2
    #[inline(always)]
    pub fn is_div2(&self) -> bool {
        *self == PRESCALER::Div2
    }
    ///Input clock divided by 4
    #[inline(always)]
    pub fn is_div4(&self) -> bool {
        *self == PRESCALER::Div4
    }
    ///Input clock divided by 6
    #[inline(always)]
    pub fn is_div6(&self) -> bool {
        *self == PRESCALER::Div6
    }
    ///Input clock divided by 8
    #[inline(always)]
    pub fn is_div8(&self) -> bool {
        *self == PRESCALER::Div8
    }
    ///Input clock divided by 10
    #[inline(always)]
    pub fn is_div10(&self) -> bool {
        *self == PRESCALER::Div10
    }
    ///Input clock divided by 12
    #[inline(always)]
    pub fn is_div12(&self) -> bool {
        *self == PRESCALER::Div12
    }
    ///Input clock divided by 16
    #[inline(always)]
    pub fn is_div16(&self) -> bool {
        *self == PRESCALER::Div16
    }
    ///Input clock divided by 32
    #[inline(always)]
    pub fn is_div32(&self) -> bool {
        *self == PRESCALER::Div32
    }
    ///Input clock divided by 64
    #[inline(always)]
    pub fn is_div64(&self) -> bool {
        *self == PRESCALER::Div64
    }
    ///Input clock divided by 128
    #[inline(always)]
    pub fn is_div128(&self) -> bool {
        *self == PRESCALER::Div128
    }
    ///Input clock divided by 256
    #[inline(always)]
    pub fn is_div256(&self) -> bool {
        *self == PRESCALER::Div256
    }
}
///Field `PRESCALER` writer - Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256.
pub type PRESCALER_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PRESCALER>;
impl<'a, REG> PRESCALER_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///Input clock divided by 1
    #[inline(always)]
    pub fn div1(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div1)
    }
    ///Input clock divided by 2
    #[inline(always)]
    pub fn div2(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div2)
    }
    ///Input clock divided by 4
    #[inline(always)]
    pub fn div4(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div4)
    }
    ///Input clock divided by 6
    #[inline(always)]
    pub fn div6(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div6)
    }
    ///Input clock divided by 8
    #[inline(always)]
    pub fn div8(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div8)
    }
    ///Input clock divided by 10
    #[inline(always)]
    pub fn div10(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div10)
    }
    ///Input clock divided by 12
    #[inline(always)]
    pub fn div12(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div12)
    }
    ///Input clock divided by 16
    #[inline(always)]
    pub fn div16(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div16)
    }
    ///Input clock divided by 32
    #[inline(always)]
    pub fn div32(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div32)
    }
    ///Input clock divided by 64
    #[inline(always)]
    pub fn div64(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div64)
    }
    ///Input clock divided by 128
    #[inline(always)]
    pub fn div128(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div128)
    }
    ///Input clock divided by 256
    #[inline(always)]
    pub fn div256(self) -> &'a mut crate::W<REG> {
        self.variant(PRESCALER::Div256)
    }
}
impl R {
    ///Bits 0:3 - Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256.
    #[inline(always)]
    pub fn prescaler(&self) -> PRESCALER_R {
        PRESCALER_R::new((self.bits & 0x0f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PRESC").field("prescaler", &self.prescaler()).finish()
    }
}
impl W {
    ///Bits 0:3 - Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is equal to 1011 i.e. input clock divided by 256.
    #[inline(always)]
    pub fn prescaler(&mut self) -> PRESCALER_W<PRESCrs> {
        PRESCALER_W::new(self, 0)
    }
}
/**USART prescaler register

You can [`read`](crate::Reg::read) this register and get [`presc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`presc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct PRESCrs;
impl crate::RegisterSpec for PRESCrs {
    type Ux = u32;
}
///`read()` method returns [`presc::R`](R) reader structure
impl crate::Readable for PRESCrs {}
///`write(|w| ..)` method takes [`presc::W`](W) writer structure
impl crate::Writable for PRESCrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets PRESC to value 0
impl crate::Resettable for PRESCrs {}