stm32h7 0.16.0

///Register `CR1` reader
pub type R = crate::R<CR1rs>;
///Register `CR1` writer
pub type W = crate::W<CR1rs>;
/**Serial Peripheral Enable

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SPE {
    ///0: Peripheral disabled
    Disabled = 0,
    ///1: Peripheral enabled
    Enabled = 1,
}
impl From<SPE> for bool {
    #[inline(always)]
    fn from(variant: SPE) -> Self {
        variant as u8 != 0
    }
}
///Field `SPE` reader - Serial Peripheral Enable
pub type SPE_R = crate::BitReader<SPE>;
impl SPE_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> SPE {
        match self.bits {
            false => SPE::Disabled,
            true => SPE::Enabled,
        }
    }
    ///Peripheral disabled
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == SPE::Disabled
    }
    ///Peripheral enabled
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == SPE::Enabled
    }
}
///Field `SPE` writer - Serial Peripheral Enable
pub type SPE_W<'a, REG> = crate::BitWriter<'a, REG, SPE>;
impl<'a, REG> SPE_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Peripheral disabled
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(SPE::Disabled)
    }
    ///Peripheral enabled
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(SPE::Enabled)
    }
}
/**Master automatic SUSP in Receive mode

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MASRX {
    ///0: Automatic suspend in master receive-only mode disabled
    Disabled = 0,
    ///1: Automatic suspend in master receive-only mode enabled
    Enabled = 1,
}
impl From<MASRX> for bool {
    #[inline(always)]
    fn from(variant: MASRX) -> Self {
        variant as u8 != 0
    }
}
///Field `MASRX` reader - Master automatic SUSP in Receive mode
pub type MASRX_R = crate::BitReader<MASRX>;
impl MASRX_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> MASRX {
        match self.bits {
            false => MASRX::Disabled,
            true => MASRX::Enabled,
        }
    }
    ///Automatic suspend in master receive-only mode disabled
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == MASRX::Disabled
    }
    ///Automatic suspend in master receive-only mode enabled
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == MASRX::Enabled
    }
}
///Field `MASRX` writer - Master automatic SUSP in Receive mode
pub type MASRX_W<'a, REG> = crate::BitWriter<'a, REG, MASRX>;
impl<'a, REG> MASRX_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Automatic suspend in master receive-only mode disabled
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(MASRX::Disabled)
    }
    ///Automatic suspend in master receive-only mode enabled
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(MASRX::Enabled)
    }
}
/**Master transfer start

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CSTART {
    ///0: Do not start master transfer
    NotStarted = 0,
    ///1: Start master transfer
    Started = 1,
}
impl From<CSTART> for bool {
    #[inline(always)]
    fn from(variant: CSTART) -> Self {
        variant as u8 != 0
    }
}
///Field `CSTART` reader - Master transfer start
pub type CSTART_R = crate::BitReader<CSTART>;
impl CSTART_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> CSTART {
        match self.bits {
            false => CSTART::NotStarted,
            true => CSTART::Started,
        }
    }
    ///Do not start master transfer
    #[inline(always)]
    pub fn is_not_started(&self) -> bool {
        *self == CSTART::NotStarted
    }
    ///Start master transfer
    #[inline(always)]
    pub fn is_started(&self) -> bool {
        *self == CSTART::Started
    }
}
///Field `CSTART` writer - Master transfer start
pub type CSTART_W<'a, REG> = crate::BitWriter<'a, REG, CSTART>;
impl<'a, REG> CSTART_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Do not start master transfer
    #[inline(always)]
    pub fn not_started(self) -> &'a mut crate::W<REG> {
        self.variant(CSTART::NotStarted)
    }
    ///Start master transfer
    #[inline(always)]
    pub fn started(self) -> &'a mut crate::W<REG> {
        self.variant(CSTART::Started)
    }
}
/**Master SUSPend request

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CSUSPW {
    ///0: Do not request master suspend
    NotRequested = 0,
    ///1: Request master suspend
    Requested = 1,
}
impl From<CSUSPW> for bool {
    #[inline(always)]
    fn from(variant: CSUSPW) -> Self {
        variant as u8 != 0
    }
}
///Field `CSUSP` writer - Master SUSPend request
pub type CSUSP_W<'a, REG> = crate::BitWriter<'a, REG, CSUSPW>;
impl<'a, REG> CSUSP_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Do not request master suspend
    #[inline(always)]
    pub fn not_requested(self) -> &'a mut crate::W<REG> {
        self.variant(CSUSPW::NotRequested)
    }
    ///Request master suspend
    #[inline(always)]
    pub fn requested(self) -> &'a mut crate::W<REG> {
        self.variant(CSUSPW::Requested)
    }
}
/**Rx/Tx direction at Half-duplex mode

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum HDDIR {
    ///0: Receiver in half duplex mode
    Receiver = 0,
    ///1: Transmitter in half duplex mode
    Transmitter = 1,
}
impl From<HDDIR> for bool {
    #[inline(always)]
    fn from(variant: HDDIR) -> Self {
        variant as u8 != 0
    }
}
///Field `HDDIR` reader - Rx/Tx direction at Half-duplex mode
pub type HDDIR_R = crate::BitReader<HDDIR>;
impl HDDIR_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> HDDIR {
        match self.bits {
            false => HDDIR::Receiver,
            true => HDDIR::Transmitter,
        }
    }
    ///Receiver in half duplex mode
    #[inline(always)]
    pub fn is_receiver(&self) -> bool {
        *self == HDDIR::Receiver
    }
    ///Transmitter in half duplex mode
    #[inline(always)]
    pub fn is_transmitter(&self) -> bool {
        *self == HDDIR::Transmitter
    }
}
///Field `HDDIR` writer - Rx/Tx direction at Half-duplex mode
pub type HDDIR_W<'a, REG> = crate::BitWriter<'a, REG, HDDIR>;
impl<'a, REG> HDDIR_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Receiver in half duplex mode
    #[inline(always)]
    pub fn receiver(self) -> &'a mut crate::W<REG> {
        self.variant(HDDIR::Receiver)
    }
    ///Transmitter in half duplex mode
    #[inline(always)]
    pub fn transmitter(self) -> &'a mut crate::W<REG> {
        self.variant(HDDIR::Transmitter)
    }
}
/**Internal SS signal input level

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SSI {
    ///0: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
    SlaveSelected = 0,
    ///1: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored
    SlaveNotSelected = 1,
}
impl From<SSI> for bool {
    #[inline(always)]
    fn from(variant: SSI) -> Self {
        variant as u8 != 0
    }
}
///Field `SSI` reader - Internal SS signal input level
pub type SSI_R = crate::BitReader<SSI>;
impl SSI_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> SSI {
        match self.bits {
            false => SSI::SlaveSelected,
            true => SSI::SlaveNotSelected,
        }
    }
    ///0 is forced onto the SS signal and the I/O value of the SS pin is ignored
    #[inline(always)]
    pub fn is_slave_selected(&self) -> bool {
        *self == SSI::SlaveSelected
    }
    ///1 is forced onto the SS signal and the I/O value of the SS pin is ignored
    #[inline(always)]
    pub fn is_slave_not_selected(&self) -> bool {
        *self == SSI::SlaveNotSelected
    }
}
///Field `SSI` writer - Internal SS signal input level
pub type SSI_W<'a, REG> = crate::BitWriter<'a, REG, SSI>;
impl<'a, REG> SSI_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///0 is forced onto the SS signal and the I/O value of the SS pin is ignored
    #[inline(always)]
    pub fn slave_selected(self) -> &'a mut crate::W<REG> {
        self.variant(SSI::SlaveSelected)
    }
    ///1 is forced onto the SS signal and the I/O value of the SS pin is ignored
    #[inline(always)]
    pub fn slave_not_selected(self) -> &'a mut crate::W<REG> {
        self.variant(SSI::SlaveNotSelected)
    }
}
/**32-bit CRC polynomial configuration

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CRC33_17 {
    ///0: Full size (33/17 bit) CRC polynomial is not used
    Disabled = 0,
    ///1: Full size (33/17 bit) CRC polynomial is used
    Enabled = 1,
}
impl From<CRC33_17> for bool {
    #[inline(always)]
    fn from(variant: CRC33_17) -> Self {
        variant as u8 != 0
    }
}
///Field `CRC33_17` reader - 32-bit CRC polynomial configuration
pub type CRC33_17_R = crate::BitReader<CRC33_17>;
impl CRC33_17_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> CRC33_17 {
        match self.bits {
            false => CRC33_17::Disabled,
            true => CRC33_17::Enabled,
        }
    }
    ///Full size (33/17 bit) CRC polynomial is not used
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == CRC33_17::Disabled
    }
    ///Full size (33/17 bit) CRC polynomial is used
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == CRC33_17::Enabled
    }
}
///Field `CRC33_17` writer - 32-bit CRC polynomial configuration
pub type CRC33_17_W<'a, REG> = crate::BitWriter<'a, REG, CRC33_17>;
impl<'a, REG> CRC33_17_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Full size (33/17 bit) CRC polynomial is not used
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(CRC33_17::Disabled)
    }
    ///Full size (33/17 bit) CRC polynomial is used
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(CRC33_17::Enabled)
    }
}
/**CRC calculation initialization pattern control for receiver

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RCRCINI {
    ///0: All zeros RX CRC initialization pattern
    AllZeros = 0,
    ///1: All ones RX CRC initialization pattern
    AllOnes = 1,
}
impl From<RCRCINI> for bool {
    #[inline(always)]
    fn from(variant: RCRCINI) -> Self {
        variant as u8 != 0
    }
}
///Field `RCRCINI` reader - CRC calculation initialization pattern control for receiver
pub type RCRCINI_R = crate::BitReader<RCRCINI>;
impl RCRCINI_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> RCRCINI {
        match self.bits {
            false => RCRCINI::AllZeros,
            true => RCRCINI::AllOnes,
        }
    }
    ///All zeros RX CRC initialization pattern
    #[inline(always)]
    pub fn is_all_zeros(&self) -> bool {
        *self == RCRCINI::AllZeros
    }
    ///All ones RX CRC initialization pattern
    #[inline(always)]
    pub fn is_all_ones(&self) -> bool {
        *self == RCRCINI::AllOnes
    }
}
///Field `RCRCINI` writer - CRC calculation initialization pattern control for receiver
pub type RCRCINI_W<'a, REG> = crate::BitWriter<'a, REG, RCRCINI>;
impl<'a, REG> RCRCINI_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///All zeros RX CRC initialization pattern
    #[inline(always)]
    pub fn all_zeros(self) -> &'a mut crate::W<REG> {
        self.variant(RCRCINI::AllZeros)
    }
    ///All ones RX CRC initialization pattern
    #[inline(always)]
    pub fn all_ones(self) -> &'a mut crate::W<REG> {
        self.variant(RCRCINI::AllOnes)
    }
}
/**CRC calculation initialization pattern control for transmitter

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TCRCINI {
    ///0: All zeros TX CRC initialization pattern
    AllZeros = 0,
    ///1: All ones TX CRC initialization pattern
    AllOnes = 1,
}
impl From<TCRCINI> for bool {
    #[inline(always)]
    fn from(variant: TCRCINI) -> Self {
        variant as u8 != 0
    }
}
///Field `TCRCINI` reader - CRC calculation initialization pattern control for transmitter
pub type TCRCINI_R = crate::BitReader<TCRCINI>;
impl TCRCINI_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> TCRCINI {
        match self.bits {
            false => TCRCINI::AllZeros,
            true => TCRCINI::AllOnes,
        }
    }
    ///All zeros TX CRC initialization pattern
    #[inline(always)]
    pub fn is_all_zeros(&self) -> bool {
        *self == TCRCINI::AllZeros
    }
    ///All ones TX CRC initialization pattern
    #[inline(always)]
    pub fn is_all_ones(&self) -> bool {
        *self == TCRCINI::AllOnes
    }
}
///Field `TCRCINI` writer - CRC calculation initialization pattern control for transmitter
pub type TCRCINI_W<'a, REG> = crate::BitWriter<'a, REG, TCRCINI>;
impl<'a, REG> TCRCINI_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///All zeros TX CRC initialization pattern
    #[inline(always)]
    pub fn all_zeros(self) -> &'a mut crate::W<REG> {
        self.variant(TCRCINI::AllZeros)
    }
    ///All ones TX CRC initialization pattern
    #[inline(always)]
    pub fn all_ones(self) -> &'a mut crate::W<REG> {
        self.variant(TCRCINI::AllOnes)
    }
}
/**Locking the AF configuration of associated IOs

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum IOLOCK {
    ///0: IO configuration unlocked
    Unlocked = 0,
    ///1: IO configuration locked
    Locked = 1,
}
impl From<IOLOCK> for bool {
    #[inline(always)]
    fn from(variant: IOLOCK) -> Self {
        variant as u8 != 0
    }
}
///Field `IOLOCK` reader - Locking the AF configuration of associated IOs
pub type IOLOCK_R = crate::BitReader<IOLOCK>;
impl IOLOCK_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> IOLOCK {
        match self.bits {
            false => IOLOCK::Unlocked,
            true => IOLOCK::Locked,
        }
    }
    ///IO configuration unlocked
    #[inline(always)]
    pub fn is_unlocked(&self) -> bool {
        *self == IOLOCK::Unlocked
    }
    ///IO configuration locked
    #[inline(always)]
    pub fn is_locked(&self) -> bool {
        *self == IOLOCK::Locked
    }
}
///Field `IOLOCK` writer - Locking the AF configuration of associated IOs
pub type IOLOCK_W<'a, REG> = crate::BitWriter<'a, REG, IOLOCK>;
impl<'a, REG> IOLOCK_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///IO configuration unlocked
    #[inline(always)]
    pub fn unlocked(self) -> &'a mut crate::W<REG> {
        self.variant(IOLOCK::Unlocked)
    }
    ///IO configuration locked
    #[inline(always)]
    pub fn locked(self) -> &'a mut crate::W<REG> {
        self.variant(IOLOCK::Locked)
    }
}
impl R {
    ///Bit 0 - Serial Peripheral Enable
    #[inline(always)]
    pub fn spe(&self) -> SPE_R {
        SPE_R::new((self.bits & 1) != 0)
    }
    ///Bit 8 - Master automatic SUSP in Receive mode
    #[inline(always)]
    pub fn masrx(&self) -> MASRX_R {
        MASRX_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - Master transfer start
    #[inline(always)]
    pub fn cstart(&self) -> CSTART_R {
        CSTART_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 11 - Rx/Tx direction at Half-duplex mode
    #[inline(always)]
    pub fn hddir(&self) -> HDDIR_R {
        HDDIR_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - Internal SS signal input level
    #[inline(always)]
    pub fn ssi(&self) -> SSI_R {
        SSI_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - 32-bit CRC polynomial configuration
    #[inline(always)]
    pub fn crc33_17(&self) -> CRC33_17_R {
        CRC33_17_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - CRC calculation initialization pattern control for receiver
    #[inline(always)]
    pub fn rcrcini(&self) -> RCRCINI_R {
        RCRCINI_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - CRC calculation initialization pattern control for transmitter
    #[inline(always)]
    pub fn tcrcini(&self) -> TCRCINI_R {
        TCRCINI_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - Locking the AF configuration of associated IOs
    #[inline(always)]
    pub fn iolock(&self) -> IOLOCK_R {
        IOLOCK_R::new(((self.bits >> 16) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CR1")
            .field("iolock", &self.iolock())
            .field("tcrcini", &self.tcrcini())
            .field("rcrcini", &self.rcrcini())
            .field("crc33_17", &self.crc33_17())
            .field("ssi", &self.ssi())
            .field("hddir", &self.hddir())
            .field("cstart", &self.cstart())
            .field("masrx", &self.masrx())
            .field("spe", &self.spe())
            .finish()
    }
}
impl W {
    ///Bit 0 - Serial Peripheral Enable
    #[inline(always)]
    pub fn spe(&mut self) -> SPE_W<CR1rs> {
        SPE_W::new(self, 0)
    }
    ///Bit 8 - Master automatic SUSP in Receive mode
    #[inline(always)]
    pub fn masrx(&mut self) -> MASRX_W<CR1rs> {
        MASRX_W::new(self, 8)
    }
    ///Bit 9 - Master transfer start
    #[inline(always)]
    pub fn cstart(&mut self) -> CSTART_W<CR1rs> {
        CSTART_W::new(self, 9)
    }
    ///Bit 10 - Master SUSPend request
    #[inline(always)]
    pub fn csusp(&mut self) -> CSUSP_W<CR1rs> {
        CSUSP_W::new(self, 10)
    }
    ///Bit 11 - Rx/Tx direction at Half-duplex mode
    #[inline(always)]
    pub fn hddir(&mut self) -> HDDIR_W<CR1rs> {
        HDDIR_W::new(self, 11)
    }
    ///Bit 12 - Internal SS signal input level
    #[inline(always)]
    pub fn ssi(&mut self) -> SSI_W<CR1rs> {
        SSI_W::new(self, 12)
    }
    ///Bit 13 - 32-bit CRC polynomial configuration
    #[inline(always)]
    pub fn crc33_17(&mut self) -> CRC33_17_W<CR1rs> {
        CRC33_17_W::new(self, 13)
    }
    ///Bit 14 - CRC calculation initialization pattern control for receiver
    #[inline(always)]
    pub fn rcrcini(&mut self) -> RCRCINI_W<CR1rs> {
        RCRCINI_W::new(self, 14)
    }
    ///Bit 15 - CRC calculation initialization pattern control for transmitter
    #[inline(always)]
    pub fn tcrcini(&mut self) -> TCRCINI_W<CR1rs> {
        TCRCINI_W::new(self, 15)
    }
    ///Bit 16 - Locking the AF configuration of associated IOs
    #[inline(always)]
    pub fn iolock(&mut self) -> IOLOCK_W<CR1rs> {
        IOLOCK_W::new(self, 16)
    }
}
/**control register 1

You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CR1rs;
impl crate::RegisterSpec for CR1rs {
    type Ux = u32;
}
///`read()` method returns [`cr1::R`](R) reader structure
impl crate::Readable for CR1rs {}
///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
impl crate::Writable for CR1rs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CR1 to value 0
impl crate::Resettable for CR1rs {}