stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `ALR%sBINR` reader
pub type R = crate::R<ALRBINRrs>;
///Register `ALR%sBINR` writer
pub type W = crate::W<ALRBINRrs>;
///Field `SS` reader - Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS\[14:0\] is the mirror of SS\[14:0\] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR.
pub type SS_R = crate::FieldReader<u32>;
///Field `SS` writer - Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS\[14:0\] is the mirror of SS\[14:0\] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR.
pub type SS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
    ///Bits 0:31 - Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS\[14:0\] is the mirror of SS\[14:0\] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR.
    #[inline(always)]
    pub fn ss(&self) -> SS_R {
        SS_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ALRBINR").field("ss", &self.ss()).finish()
    }
}
impl W {
    ///Bits 0:31 - Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS\[14:0\] is the mirror of SS\[14:0\] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR.
    #[inline(always)]
    pub fn ss(&mut self) -> SS_W<ALRBINRrs> {
        SS_W::new(self, 0)
    }
}
/**Alarm %s binary mode register

You can [`read`](crate::Reg::read) this register and get [`alrbinr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrbinr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct ALRBINRrs;
impl crate::RegisterSpec for ALRBINRrs {
    type Ux = u32;
}
///`read()` method returns [`alrbinr::R`](R) reader structure
impl crate::Readable for ALRBINRrs {}
///`write(|w| ..)` method takes [`alrbinr::W`](W) writer structure
impl crate::Writable for ALRBINRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets ALR%sBINR to value 0
impl crate::Resettable for ALRBINRrs {}