stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `M5FDRL` reader
pub type R = crate::R<M5FDRLrs>;
///Field `FDATAL` reader - Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error.
pub type FDATAL_R = crate::FieldReader<u32>;
impl R {
    ///Bits 0:31 - Failing data low When an ECC error occurs the FDATAL bitfield contains the LSB part of the data that generated the error. For 32-bit word SRAM, this bitfield contains the full memory word that generated the error.
    #[inline(always)]
    pub fn fdatal(&self) -> FDATAL_R {
        FDATAL_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("M5FDRL").field("fdatal", &self.fdatal()).finish()
    }
}
/**RAMECC monitor 5 failing data low register

You can [`read`](crate::Reg::read) this register and get [`m5fdrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct M5FDRLrs;
impl crate::RegisterSpec for M5FDRLrs {
    type Ux = u32;
}
///`read()` method returns [`m5fdrl::R`](R) reader structure
impl crate::Readable for M5FDRLrs {}
///`reset()` method sets M5FDRL to value 0
impl crate::Resettable for M5FDRLrs {}