stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `CLRFR` writer
pub type W = crate::W<CLRFRrs>;
///Field `PROCENDFC` writer - Clear PKA End of Operation flag
pub type PROCENDFC_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RAMERRFC` writer - Clear PKA RAM error flag
pub type RAMERRFC_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ADDRERRFC` writer - Clear address error flag
pub type ADDRERRFC_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `OPERRFC` writer - Clear operation error flag
pub type OPERRFC_W<'a, REG> = crate::BitWriter<'a, REG>;
impl core::fmt::Debug for crate::generic::Reg<CLRFRrs> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    ///Bit 17 - Clear PKA End of Operation flag
    #[inline(always)]
    pub fn procendfc(&mut self) -> PROCENDFC_W<CLRFRrs> {
        PROCENDFC_W::new(self, 17)
    }
    ///Bit 19 - Clear PKA RAM error flag
    #[inline(always)]
    pub fn ramerrfc(&mut self) -> RAMERRFC_W<CLRFRrs> {
        RAMERRFC_W::new(self, 19)
    }
    ///Bit 20 - Clear address error flag
    #[inline(always)]
    pub fn addrerrfc(&mut self) -> ADDRERRFC_W<CLRFRrs> {
        ADDRERRFC_W::new(self, 20)
    }
    ///Bit 21 - Clear operation error flag
    #[inline(always)]
    pub fn operrfc(&mut self) -> OPERRFC_W<CLRFRrs> {
        OPERRFC_W::new(self, 21)
    }
}
/**PKA clear flag register

You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clrfr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CLRFRrs;
impl crate::RegisterSpec for CLRFRrs {
    type Ux = u32;
}
///`write(|w| ..)` method takes [`clrfr::W`](W) writer structure
impl crate::Writable for CLRFRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CLRFR to value 0
impl crate::Resettable for CLRFRrs {}