stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

///Register `HAINT` reader
pub type R = crate::R<HAINTrs>;
///Field `HAINT` reader - Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
pub type HAINT_R = crate::FieldReader<u16>;
impl R {
    ///Bits 0:15 - Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
    #[inline(always)]
    pub fn haint(&self) -> HAINT_R {
        HAINT_R::new((self.bits & 0xffff) as u16)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HAINT").field("haint", &self.haint()).finish()
    }
}
/**OTG host all channels interrupt register

You can [`read`](crate::Reg::read) this register and get [`haint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct HAINTrs;
impl crate::RegisterSpec for HAINTrs {
    type Ux = u32;
}
///`read()` method returns [`haint::R`](R) reader structure
impl crate::Readable for HAINTrs {}
///`reset()` method sets HAINT to value 0
impl crate::Resettable for HAINTrs {}