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///Register `HFIR` reader
pub type R = crate::R<HFIRrs>;
///Register `HFIR` writer
pub type W = crate::W<HFIRrs>;
///Field `FRIVL` reader - Frame interval
pub type FRIVL_R = crate::FieldReader<u16>;
///Field `FRIVL` writer - Frame interval
pub type FRIVL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
///Field `RLDCTRL` reader - Reload control This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during run time. RLDCTRL = 0 is not recommended.
pub type RLDCTRL_R = crate::BitReader;
///Field `RLDCTRL` writer - Reload control This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during run time. RLDCTRL = 0 is not recommended.
pub type RLDCTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
///Bits 0:15 - Frame interval
#[inline(always)]
pub fn frivl(&self) -> FRIVL_R {
FRIVL_R::new((self.bits & 0xffff) as u16)
}
///Bit 16 - Reload control This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during run time. RLDCTRL = 0 is not recommended.
#[inline(always)]
pub fn rldctrl(&self) -> RLDCTRL_R {
RLDCTRL_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HFIR")
.field("frivl", &self.frivl())
.field("rldctrl", &self.rldctrl())
.finish()
}
}
impl W {
///Bits 0:15 - Frame interval
#[inline(always)]
pub fn frivl(&mut self) -> FRIVL_W<HFIRrs> {
FRIVL_W::new(self, 0)
}
///Bit 16 - Reload control This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value must not be changed during run time. RLDCTRL = 0 is not recommended.
#[inline(always)]
pub fn rldctrl(&mut self) -> RLDCTRL_W<HFIRrs> {
RLDCTRL_W::new(self, 16)
}
}
/**OTG host frame interval register
You can [`read`](crate::Reg::read) this register and get [`hfir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct HFIRrs;
impl crate::RegisterSpec for HFIRrs {
type Ux = u32;
}
///`read()` method returns [`hfir::R`](R) reader structure
impl crate::Readable for HFIRrs {}
///`write(|w| ..)` method takes [`hfir::W`](W) writer structure
impl crate::Writable for HFIRrs {
type Safety = crate::Unsafe;
}
///`reset()` method sets HFIR to value 0xea60
impl crate::Resettable for HFIRrs {
const RESET_VALUE: u32 = 0xea60;
}