stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `SAR` reader
pub type R = crate::R<SARrs>;
///Register `SAR` writer
pub type W = crate::W<SARrs>;
///Field `SAR` reader - source adr base
pub type SAR_R = crate::FieldReader<u32>;
///Field `SAR` writer - source adr base
pub type SAR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
    ///Bits 0:31 - source adr base
    #[inline(always)]
    pub fn sar(&self) -> SAR_R {
        SAR_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAR").field("sar", &self.sar()).finish()
    }
}
impl W {
    ///Bits 0:31 - source adr base
    #[inline(always)]
    pub fn sar(&mut self) -> SAR_W<SARrs> {
        SAR_W::new(self, 0)
    }
}
/**MDMA channel x source address register

You can [`read`](crate::Reg::read) this register and get [`sar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct SARrs;
impl crate::RegisterSpec for SARrs {
    type Ux = u32;
}
///`read()` method returns [`sar::R`](R) reader structure
impl crate::Readable for SARrs {}
///`write(|w| ..)` method takes [`sar::W`](W) writer structure
impl crate::Writable for SARrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets SAR to value 0
impl crate::Resettable for SARrs {}