stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178

///Register `CR` reader
pub type R = crate::R<CRrs>;
///Register `CR` writer
pub type W = crate::W<CRrs>;
///Field `JCEN` reader - JPEG core enable This bit enables the JPEG codec core.
pub type JCEN_R = crate::BitReader;
///Field `JCEN` writer - JPEG core enable This bit enables the JPEG codec core.
pub type JCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IFTIE` reader - Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold.
pub type IFTIE_R = crate::BitReader;
///Field `IFTIE` writer - Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold.
pub type IFTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IFNFIE` reader - Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty.
pub type IFNFIE_R = crate::BitReader;
///Field `IFNFIE` writer - Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty.
pub type IFNFIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `OFTIE` reader - Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold.
pub type OFTIE_R = crate::BitReader;
///Field `OFTIE` writer - Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold.
pub type OFTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `OFNEIE` reader - Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty.
pub type OFNEIE_R = crate::BitReader;
///Field `OFNEIE` writer - Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty.
pub type OFNEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `EOCIE` reader - End of conversion interrupt enable This bit enables interrupt generation at the end of conversion.
pub type EOCIE_R = crate::BitReader;
///Field `EOCIE` writer - End of conversion interrupt enable This bit enables interrupt generation at the end of conversion.
pub type EOCIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `HPDIE` reader - Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation.
pub type HPDIE_R = crate::BitReader;
///Field `HPDIE` writer - Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation.
pub type HPDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IDMAEN` reader - Input DMA enable Enables DMA request generation for the input FIFO.
pub type IDMAEN_R = crate::BitReader;
///Field `IDMAEN` writer - Input DMA enable Enables DMA request generation for the input FIFO.
pub type IDMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ODMAEN` reader - Output DMA enable Enables DMA request generation for the output FIFO.
pub type ODMAEN_R = crate::BitReader;
///Field `ODMAEN` writer - Output DMA enable Enables DMA request generation for the output FIFO.
pub type ODMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IFF` writer - Input FIFO flush This bit flushes the input FIFO. Note: Reads always return 0.
pub type IFF_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `OFF` writer - Output FIFO flush This bit flushes the output FIFO. Note: Reads always return 0.
pub type OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - JPEG core enable This bit enables the JPEG codec core.
    #[inline(always)]
    pub fn jcen(&self) -> JCEN_R {
        JCEN_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold.
    #[inline(always)]
    pub fn iftie(&self) -> IFTIE_R {
        IFTIE_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty.
    #[inline(always)]
    pub fn ifnfie(&self) -> IFNFIE_R {
        IFNFIE_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold.
    #[inline(always)]
    pub fn oftie(&self) -> OFTIE_R {
        OFTIE_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty.
    #[inline(always)]
    pub fn ofneie(&self) -> OFNEIE_R {
        OFNEIE_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - End of conversion interrupt enable This bit enables interrupt generation at the end of conversion.
    #[inline(always)]
    pub fn eocie(&self) -> EOCIE_R {
        EOCIE_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation.
    #[inline(always)]
    pub fn hpdie(&self) -> HPDIE_R {
        HPDIE_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 11 - Input DMA enable Enables DMA request generation for the input FIFO.
    #[inline(always)]
    pub fn idmaen(&self) -> IDMAEN_R {
        IDMAEN_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - Output DMA enable Enables DMA request generation for the output FIFO.
    #[inline(always)]
    pub fn odmaen(&self) -> ODMAEN_R {
        ODMAEN_R::new(((self.bits >> 12) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CR")
            .field("jcen", &self.jcen())
            .field("iftie", &self.iftie())
            .field("ifnfie", &self.ifnfie())
            .field("oftie", &self.oftie())
            .field("ofneie", &self.ofneie())
            .field("eocie", &self.eocie())
            .field("hpdie", &self.hpdie())
            .field("idmaen", &self.idmaen())
            .field("odmaen", &self.odmaen())
            .finish()
    }
}
impl W {
    ///Bit 0 - JPEG core enable This bit enables the JPEG codec core.
    #[inline(always)]
    pub fn jcen(&mut self) -> JCEN_W<CRrs> {
        JCEN_W::new(self, 0)
    }
    ///Bit 1 - Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold.
    #[inline(always)]
    pub fn iftie(&mut self) -> IFTIE_W<CRrs> {
        IFTIE_W::new(self, 1)
    }
    ///Bit 2 - Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty.
    #[inline(always)]
    pub fn ifnfie(&mut self) -> IFNFIE_W<CRrs> {
        IFNFIE_W::new(self, 2)
    }
    ///Bit 3 - Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold.
    #[inline(always)]
    pub fn oftie(&mut self) -> OFTIE_W<CRrs> {
        OFTIE_W::new(self, 3)
    }
    ///Bit 4 - Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty.
    #[inline(always)]
    pub fn ofneie(&mut self) -> OFNEIE_W<CRrs> {
        OFNEIE_W::new(self, 4)
    }
    ///Bit 5 - End of conversion interrupt enable This bit enables interrupt generation at the end of conversion.
    #[inline(always)]
    pub fn eocie(&mut self) -> EOCIE_W<CRrs> {
        EOCIE_W::new(self, 5)
    }
    ///Bit 6 - Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation.
    #[inline(always)]
    pub fn hpdie(&mut self) -> HPDIE_W<CRrs> {
        HPDIE_W::new(self, 6)
    }
    ///Bit 11 - Input DMA enable Enables DMA request generation for the input FIFO.
    #[inline(always)]
    pub fn idmaen(&mut self) -> IDMAEN_W<CRrs> {
        IDMAEN_W::new(self, 11)
    }
    ///Bit 12 - Output DMA enable Enables DMA request generation for the output FIFO.
    #[inline(always)]
    pub fn odmaen(&mut self) -> ODMAEN_W<CRrs> {
        ODMAEN_W::new(self, 12)
    }
    ///Bit 13 - Input FIFO flush This bit flushes the input FIFO. Note: Reads always return 0.
    #[inline(always)]
    pub fn iff(&mut self) -> IFF_W<CRrs> {
        IFF_W::new(self, 13)
    }
    ///Bit 14 - Output FIFO flush This bit flushes the output FIFO. Note: Reads always return 0.
    #[inline(always)]
    pub fn off(&mut self) -> OFF_W<CRrs> {
        OFF_W::new(self, 14)
    }
}
/**JPEG control register

You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CRrs;
impl crate::RegisterSpec for CRrs {
    type Ux = u32;
}
///`read()` method returns [`cr::R`](R) reader structure
impl crate::Readable for CRrs {}
///`write(|w| ..)` method takes [`cr::W`](W) writer structure
impl crate::Writable for CRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CR to value 0
impl crate::Resettable for CRrs {}