stm32h7 0.16.0

///Register `SET1R` reader
pub type R = crate::R<SET1Rrs>;
///Register `SET1R` writer
pub type W = crate::W<SET1Rrs>;
///Timer A compare %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::CMP1;
///Field `CMP(1-4)` reader - Timer A compare %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::CMP_R;
///Field `CMP(1-4)` writer - Timer A compare %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::CMP_W;
///External Event %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::EXTEVNT1;
///Field `EXTEVNT(1-10)` reader - External Event %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::EXTEVNT_R;
///Field `EXTEVNT(1-10)` writer - External Event %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::EXTEVNT_W;
///Master Compare %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::MSTCMP1;
///Field `MSTCMP(1-4)` reader - Master Compare %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::MSTCMP_R;
///Field `MSTCMP(1-4)` writer - Master Compare %s
pub use crate::stm32h757cm7::hrtim_tima::set1r::MSTCMP_W;
///Master Period
pub use crate::stm32h757cm7::hrtim_tima::set1r::MSTPER;
///Field `MSTPER` reader - Master Period
pub use crate::stm32h757cm7::hrtim_tima::set1r::MSTPER_R;
///Field `MSTPER` writer - Master Period
pub use crate::stm32h757cm7::hrtim_tima::set1r::MSTPER_W;
///Timer A Period
pub use crate::stm32h757cm7::hrtim_tima::set1r::PER;
///Field `PER` reader - Timer A Period
pub use crate::stm32h757cm7::hrtim_tima::set1r::PER_R;
///Field `PER` writer - Timer A Period
pub use crate::stm32h757cm7::hrtim_tima::set1r::PER_W;
///Timer A resynchronizaton
pub use crate::stm32h757cm7::hrtim_tima::set1r::RESYNC;
///Field `RESYNC` reader - Timer A resynchronizaton
pub use crate::stm32h757cm7::hrtim_tima::set1r::RESYNC_R;
///Field `RESYNC` writer - Timer A resynchronizaton
pub use crate::stm32h757cm7::hrtim_tima::set1r::RESYNC_W;
///Software Set trigger
pub use crate::stm32h757cm7::hrtim_tima::set1r::SST;
///Field `SST` reader - Software Set trigger
pub use crate::stm32h757cm7::hrtim_tima::set1r::SST_R;
///Field `SST` writer - Software Set trigger
pub use crate::stm32h757cm7::hrtim_tima::set1r::SST_W;
///Timer A Compare 3
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1;
///Field `TIMACMP3` reader - Timer A Compare 3
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMACMP3_R;
///Field `TIMACMP4` reader - Timer A Compare 4
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMACMP4_R;
///Field `TIMBCMP3` reader - Timer B Compare 3
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMBCMP3_R;
///Field `TIMBCMP4` reader - Timer B Compare 4
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMBCMP4_R;
///Field `TIMCCMP1` reader - Timer C Compare 1
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMCCMP1_R;
///Field `TIMCCMP2` reader - Timer C Compare 2
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMCCMP2_R;
///Field `TIMDCMP1` reader - Timer D Compare 1
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMDCMP1_R;
///Field `TIMDCMP2` reader - Timer D Compare 2
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMDCMP2_R;
///Field `TIMDCMP4` reader - Timer D Compare 4
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_R as TIMDCMP4_R;
///Field `TIMACMP3` writer - Timer A Compare 3
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMACMP3_W;
///Field `TIMACMP4` writer - Timer A Compare 4
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMACMP4_W;
///Field `TIMBCMP3` writer - Timer B Compare 3
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMBCMP3_W;
///Field `TIMBCMP4` writer - Timer B Compare 4
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMBCMP4_W;
///Field `TIMCCMP1` writer - Timer C Compare 1
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMCCMP1_W;
///Field `TIMCCMP2` writer - Timer C Compare 2
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMCCMP2_W;
///Field `TIMDCMP1` writer - Timer D Compare 1
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMDCMP1_W;
///Field `TIMDCMP2` writer - Timer D Compare 2
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMDCMP2_W;
///Field `TIMDCMP4` writer - Timer D Compare 4
pub use crate::stm32h757cm7::hrtim_tima::set1r::TIMBCMP1_W as TIMDCMP4_W;
///Registers update (transfer preload to active)
pub use crate::stm32h757cm7::hrtim_tima::set1r::UPDATE;
///Field `UPDATE` reader - Registers update (transfer preload to active)
pub use crate::stm32h757cm7::hrtim_tima::set1r::UPDATE_R;
///Field `UPDATE` writer - Registers update (transfer preload to active)
pub use crate::stm32h757cm7::hrtim_tima::set1r::UPDATE_W;
impl R {
    ///Bit 0 - Software Set trigger
    #[inline(always)]
    pub fn sst(&self) -> SST_R {
        SST_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Timer A resynchronizaton
    #[inline(always)]
    pub fn resync(&self) -> RESYNC_R {
        RESYNC_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Timer A Period
    #[inline(always)]
    pub fn per(&self) -> PER_R {
        PER_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Timer A compare (1-4)
    ///
    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CMP1` field.</div>
    #[inline(always)]
    pub fn cmp(&self, n: u8) -> CMP_R {
        #[allow(clippy::no_effect)] [(); 4][n as usize];
        CMP_R::new(((self.bits >> (n + 3)) & 1) != 0)
    }
    ///Iterator for array of:
    ///Timer A compare (1-4)
    #[inline(always)]
    pub fn cmp_iter(&self) -> impl Iterator<Item = CMP_R> + '_ {
        (0..4).map(move |n| CMP_R::new(((self.bits >> (n + 3)) & 1) != 0))
    }
    ///Bit 3 - Timer A compare 1
    #[inline(always)]
    pub fn cmp1(&self) -> CMP_R {
        CMP_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - Timer A compare 2
    #[inline(always)]
    pub fn cmp2(&self) -> CMP_R {
        CMP_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - Timer A compare 3
    #[inline(always)]
    pub fn cmp3(&self) -> CMP_R {
        CMP_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - Timer A compare 4
    #[inline(always)]
    pub fn cmp4(&self) -> CMP_R {
        CMP_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - Master Period
    #[inline(always)]
    pub fn mstper(&self) -> MSTPER_R {
        MSTPER_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Master Compare (1-4)
    ///
    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MSTCMP1` field.</div>
    #[inline(always)]
    pub fn mstcmp(&self, n: u8) -> MSTCMP_R {
        #[allow(clippy::no_effect)] [(); 4][n as usize];
        MSTCMP_R::new(((self.bits >> (n + 8)) & 1) != 0)
    }
    ///Iterator for array of:
    ///Master Compare (1-4)
    #[inline(always)]
    pub fn mstcmp_iter(&self) -> impl Iterator<Item = MSTCMP_R> + '_ {
        (0..4).map(move |n| MSTCMP_R::new(((self.bits >> (n + 8)) & 1) != 0))
    }
    ///Bit 8 - Master Compare 1
    #[inline(always)]
    pub fn mstcmp1(&self) -> MSTCMP_R {
        MSTCMP_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - Master Compare 2
    #[inline(always)]
    pub fn mstcmp2(&self) -> MSTCMP_R {
        MSTCMP_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - Master Compare 3
    #[inline(always)]
    pub fn mstcmp3(&self) -> MSTCMP_R {
        MSTCMP_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - Master Compare 4
    #[inline(always)]
    pub fn mstcmp4(&self) -> MSTCMP_R {
        MSTCMP_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - Timer A Compare 3
    #[inline(always)]
    pub fn timacmp3(&self) -> TIMACMP3_R {
        TIMACMP3_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - Timer A Compare 4
    #[inline(always)]
    pub fn timacmp4(&self) -> TIMACMP4_R {
        TIMACMP4_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - Timer B Compare 3
    #[inline(always)]
    pub fn timbcmp3(&self) -> TIMBCMP3_R {
        TIMBCMP3_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - Timer B Compare 4
    #[inline(always)]
    pub fn timbcmp4(&self) -> TIMBCMP4_R {
        TIMBCMP4_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - Timer C Compare 1
    #[inline(always)]
    pub fn timccmp1(&self) -> TIMCCMP1_R {
        TIMCCMP1_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - Timer C Compare 2
    #[inline(always)]
    pub fn timccmp2(&self) -> TIMCCMP2_R {
        TIMCCMP2_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - Timer D Compare 1
    #[inline(always)]
    pub fn timdcmp1(&self) -> TIMDCMP1_R {
        TIMDCMP1_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - Timer D Compare 2
    #[inline(always)]
    pub fn timdcmp2(&self) -> TIMDCMP2_R {
        TIMDCMP2_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - Timer D Compare 4
    #[inline(always)]
    pub fn timdcmp4(&self) -> TIMDCMP4_R {
        TIMDCMP4_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///External Event (1-10)
    ///
    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `EXTEVNT1` field.</div>
    #[inline(always)]
    pub fn extevnt(&self, n: u8) -> EXTEVNT_R {
        #[allow(clippy::no_effect)] [(); 10][n as usize];
        EXTEVNT_R::new(((self.bits >> (n + 21)) & 1) != 0)
    }
    ///Iterator for array of:
    ///External Event (1-10)
    #[inline(always)]
    pub fn extevnt_iter(&self) -> impl Iterator<Item = EXTEVNT_R> + '_ {
        (0..10).map(move |n| EXTEVNT_R::new(((self.bits >> (n + 21)) & 1) != 0))
    }
    ///Bit 21 - External Event 1
    #[inline(always)]
    pub fn extevnt1(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - External Event 2
    #[inline(always)]
    pub fn extevnt2(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - External Event 3
    #[inline(always)]
    pub fn extevnt3(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - External Event 4
    #[inline(always)]
    pub fn extevnt4(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - External Event 5
    #[inline(always)]
    pub fn extevnt5(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - External Event 6
    #[inline(always)]
    pub fn extevnt6(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - External Event 7
    #[inline(always)]
    pub fn extevnt7(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - External Event 8
    #[inline(always)]
    pub fn extevnt8(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - External Event 9
    #[inline(always)]
    pub fn extevnt9(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - External Event 10
    #[inline(always)]
    pub fn extevnt10(&self) -> EXTEVNT_R {
        EXTEVNT_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - Registers update (transfer preload to active)
    #[inline(always)]
    pub fn update(&self) -> UPDATE_R {
        UPDATE_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SET1R")
            .field("update", &self.update())
            .field("extevnt1", &self.extevnt1())
            .field("extevnt2", &self.extevnt2())
            .field("extevnt3", &self.extevnt3())
            .field("extevnt4", &self.extevnt4())
            .field("extevnt5", &self.extevnt5())
            .field("extevnt6", &self.extevnt6())
            .field("extevnt7", &self.extevnt7())
            .field("extevnt8", &self.extevnt8())
            .field("extevnt9", &self.extevnt9())
            .field("extevnt10", &self.extevnt10())
            .field("timacmp3", &self.timacmp3())
            .field("timdcmp4", &self.timdcmp4())
            .field("timdcmp2", &self.timdcmp2())
            .field("timdcmp1", &self.timdcmp1())
            .field("timccmp2", &self.timccmp2())
            .field("timccmp1", &self.timccmp1())
            .field("timbcmp4", &self.timbcmp4())
            .field("timbcmp3", &self.timbcmp3())
            .field("timacmp4", &self.timacmp4())
            .field("mstcmp1", &self.mstcmp1())
            .field("mstcmp2", &self.mstcmp2())
            .field("mstcmp3", &self.mstcmp3())
            .field("mstcmp4", &self.mstcmp4())
            .field("mstper", &self.mstper())
            .field("cmp1", &self.cmp1())
            .field("cmp2", &self.cmp2())
            .field("cmp3", &self.cmp3())
            .field("cmp4", &self.cmp4())
            .field("per", &self.per())
            .field("resync", &self.resync())
            .field("sst", &self.sst())
            .finish()
    }
}
impl W {
    ///Bit 0 - Software Set trigger
    #[inline(always)]
    pub fn sst(&mut self) -> SST_W<SET1Rrs> {
        SST_W::new(self, 0)
    }
    ///Bit 1 - Timer A resynchronizaton
    #[inline(always)]
    pub fn resync(&mut self) -> RESYNC_W<SET1Rrs> {
        RESYNC_W::new(self, 1)
    }
    ///Bit 2 - Timer A Period
    #[inline(always)]
    pub fn per(&mut self) -> PER_W<SET1Rrs> {
        PER_W::new(self, 2)
    }
    ///Timer A compare (1-4)
    ///
    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CMP1` field.</div>
    #[inline(always)]
    pub fn cmp(&mut self, n: u8) -> CMP_W<SET1Rrs> {
        #[allow(clippy::no_effect)] [(); 4][n as usize];
        CMP_W::new(self, n + 3)
    }
    ///Bit 3 - Timer A compare 1
    #[inline(always)]
    pub fn cmp1(&mut self) -> CMP_W<SET1Rrs> {
        CMP_W::new(self, 3)
    }
    ///Bit 4 - Timer A compare 2
    #[inline(always)]
    pub fn cmp2(&mut self) -> CMP_W<SET1Rrs> {
        CMP_W::new(self, 4)
    }
    ///Bit 5 - Timer A compare 3
    #[inline(always)]
    pub fn cmp3(&mut self) -> CMP_W<SET1Rrs> {
        CMP_W::new(self, 5)
    }
    ///Bit 6 - Timer A compare 4
    #[inline(always)]
    pub fn cmp4(&mut self) -> CMP_W<SET1Rrs> {
        CMP_W::new(self, 6)
    }
    ///Bit 7 - Master Period
    #[inline(always)]
    pub fn mstper(&mut self) -> MSTPER_W<SET1Rrs> {
        MSTPER_W::new(self, 7)
    }
    ///Master Compare (1-4)
    ///
    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MSTCMP1` field.</div>
    #[inline(always)]
    pub fn mstcmp(&mut self, n: u8) -> MSTCMP_W<SET1Rrs> {
        #[allow(clippy::no_effect)] [(); 4][n as usize];
        MSTCMP_W::new(self, n + 8)
    }
    ///Bit 8 - Master Compare 1
    #[inline(always)]
    pub fn mstcmp1(&mut self) -> MSTCMP_W<SET1Rrs> {
        MSTCMP_W::new(self, 8)
    }
    ///Bit 9 - Master Compare 2
    #[inline(always)]
    pub fn mstcmp2(&mut self) -> MSTCMP_W<SET1Rrs> {
        MSTCMP_W::new(self, 9)
    }
    ///Bit 10 - Master Compare 3
    #[inline(always)]
    pub fn mstcmp3(&mut self) -> MSTCMP_W<SET1Rrs> {
        MSTCMP_W::new(self, 10)
    }
    ///Bit 11 - Master Compare 4
    #[inline(always)]
    pub fn mstcmp4(&mut self) -> MSTCMP_W<SET1Rrs> {
        MSTCMP_W::new(self, 11)
    }
    ///Bit 12 - Timer A Compare 3
    #[inline(always)]
    pub fn timacmp3(&mut self) -> TIMACMP3_W<SET1Rrs> {
        TIMACMP3_W::new(self, 12)
    }
    ///Bit 13 - Timer A Compare 4
    #[inline(always)]
    pub fn timacmp4(&mut self) -> TIMACMP4_W<SET1Rrs> {
        TIMACMP4_W::new(self, 13)
    }
    ///Bit 14 - Timer B Compare 3
    #[inline(always)]
    pub fn timbcmp3(&mut self) -> TIMBCMP3_W<SET1Rrs> {
        TIMBCMP3_W::new(self, 14)
    }
    ///Bit 15 - Timer B Compare 4
    #[inline(always)]
    pub fn timbcmp4(&mut self) -> TIMBCMP4_W<SET1Rrs> {
        TIMBCMP4_W::new(self, 15)
    }
    ///Bit 16 - Timer C Compare 1
    #[inline(always)]
    pub fn timccmp1(&mut self) -> TIMCCMP1_W<SET1Rrs> {
        TIMCCMP1_W::new(self, 16)
    }
    ///Bit 17 - Timer C Compare 2
    #[inline(always)]
    pub fn timccmp2(&mut self) -> TIMCCMP2_W<SET1Rrs> {
        TIMCCMP2_W::new(self, 17)
    }
    ///Bit 18 - Timer D Compare 1
    #[inline(always)]
    pub fn timdcmp1(&mut self) -> TIMDCMP1_W<SET1Rrs> {
        TIMDCMP1_W::new(self, 18)
    }
    ///Bit 19 - Timer D Compare 2
    #[inline(always)]
    pub fn timdcmp2(&mut self) -> TIMDCMP2_W<SET1Rrs> {
        TIMDCMP2_W::new(self, 19)
    }
    ///Bit 20 - Timer D Compare 4
    #[inline(always)]
    pub fn timdcmp4(&mut self) -> TIMDCMP4_W<SET1Rrs> {
        TIMDCMP4_W::new(self, 20)
    }
    ///External Event (1-10)
    ///
    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `EXTEVNT1` field.</div>
    #[inline(always)]
    pub fn extevnt(&mut self, n: u8) -> EXTEVNT_W<SET1Rrs> {
        #[allow(clippy::no_effect)] [(); 10][n as usize];
        EXTEVNT_W::new(self, n + 21)
    }
    ///Bit 21 - External Event 1
    #[inline(always)]
    pub fn extevnt1(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 21)
    }
    ///Bit 22 - External Event 2
    #[inline(always)]
    pub fn extevnt2(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 22)
    }
    ///Bit 23 - External Event 3
    #[inline(always)]
    pub fn extevnt3(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 23)
    }
    ///Bit 24 - External Event 4
    #[inline(always)]
    pub fn extevnt4(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 24)
    }
    ///Bit 25 - External Event 5
    #[inline(always)]
    pub fn extevnt5(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 25)
    }
    ///Bit 26 - External Event 6
    #[inline(always)]
    pub fn extevnt6(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 26)
    }
    ///Bit 27 - External Event 7
    #[inline(always)]
    pub fn extevnt7(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 27)
    }
    ///Bit 28 - External Event 8
    #[inline(always)]
    pub fn extevnt8(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 28)
    }
    ///Bit 29 - External Event 9
    #[inline(always)]
    pub fn extevnt9(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 29)
    }
    ///Bit 30 - External Event 10
    #[inline(always)]
    pub fn extevnt10(&mut self) -> EXTEVNT_W<SET1Rrs> {
        EXTEVNT_W::new(self, 30)
    }
    ///Bit 31 - Registers update (transfer preload to active)
    #[inline(always)]
    pub fn update(&mut self) -> UPDATE_W<SET1Rrs> {
        UPDATE_W::new(self, 31)
    }
}
/**Timerx Output1 Set Register

You can [`read`](crate::Reg::read) this register and get [`set1r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set1r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct SET1Rrs;
impl crate::RegisterSpec for SET1Rrs {
    type Ux = u32;
}
///`read()` method returns [`set1r::R`](R) reader structure
impl crate::Readable for SET1Rrs {}
///`write(|w| ..)` method takes [`set1r::W`](W) writer structure
impl crate::Writable for SET1Rrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets SET1R to value 0
impl crate::Resettable for SET1Rrs {}