stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

#[repr(C)]
#[derive(Debug)]
///Register block
pub struct RegisterBlock {
    cr: CR,
    isr: ISR,
    icr: ICR,
    dier: DIER,
    cntr: CNTR,
    perr: PERR,
    repr: REPR,
    cmp1r: CMP1R,
    _reserved8: [u8; 0x04],
    cmp2r: CMP2R,
    cmp3r: CMP3R,
    cmp4r: CMP4R,
}
impl RegisterBlock {
    ///0x00 - Master Timer Control Register
    #[inline(always)]
    pub const fn cr(&self) -> &CR {
        &self.cr
    }
    ///0x04 - Master Timer Interrupt Status Register
    #[inline(always)]
    pub const fn isr(&self) -> &ISR {
        &self.isr
    }
    ///0x08 - Master Timer Interrupt Clear Register
    #[inline(always)]
    pub const fn icr(&self) -> &ICR {
        &self.icr
    }
    ///0x0c - MDIER4
    #[inline(always)]
    pub const fn dier(&self) -> &DIER {
        &self.dier
    }
    ///0x10 - Master Timer Counter Register
    #[inline(always)]
    pub const fn cntr(&self) -> &CNTR {
        &self.cntr
    }
    ///0x14 - Master Timer Period Register
    #[inline(always)]
    pub const fn perr(&self) -> &PERR {
        &self.perr
    }
    ///0x18 - Master Timer Repetition Register
    #[inline(always)]
    pub const fn repr(&self) -> &REPR {
        &self.repr
    }
    ///0x1c - Master Timer Compare 1 Register
    #[inline(always)]
    pub const fn cmp1r(&self) -> &CMP1R {
        &self.cmp1r
    }
    ///0x24 - Master Timer Compare 2 Register
    #[inline(always)]
    pub const fn cmp2r(&self) -> &CMP2R {
        &self.cmp2r
    }
    ///0x28 - Master Timer Compare 3 Register
    #[inline(always)]
    pub const fn cmp3r(&self) -> &CMP3R {
        &self.cmp3r
    }
    ///0x2c - Master Timer Compare 4 Register
    #[inline(always)]
    pub const fn cmp4r(&self) -> &CMP4R {
        &self.cmp4r
    }
}
/**CR (rw) register accessor: Master Timer Control Register

You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@cr`] module*/
pub type CR = crate::Reg<cr::CRrs>;
///Master Timer Control Register
pub mod cr;
/**ISR (r) register accessor: Master Timer Interrupt Status Register

You can [`read`](crate::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@isr`] module*/
pub type ISR = crate::Reg<isr::ISRrs>;
///Master Timer Interrupt Status Register
pub mod isr;
/**ICR (w) register accessor: Master Timer Interrupt Clear Register

You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@icr`] module*/
pub type ICR = crate::Reg<icr::ICRrs>;
///Master Timer Interrupt Clear Register
pub mod icr;
/**DIER (rw) register accessor: MDIER4

You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@dier`] module*/
pub type DIER = crate::Reg<dier::DIERrs>;
///MDIER4
pub mod dier;
/**CNTR (rw) register accessor: Master Timer Counter Register

You can [`read`](crate::Reg::read) this register and get [`cntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@cntr`] module*/
pub type CNTR = crate::Reg<cntr::CNTRrs>;
///Master Timer Counter Register
pub mod cntr;
/**PERR (rw) register accessor: Master Timer Period Register

You can [`read`](crate::Reg::read) this register and get [`perr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@perr`] module*/
pub type PERR = crate::Reg<perr::PERRrs>;
///Master Timer Period Register
pub mod perr;
/**REPR (rw) register accessor: Master Timer Repetition Register

You can [`read`](crate::Reg::read) this register and get [`repr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`repr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@repr`] module*/
pub type REPR = crate::Reg<repr::REPRrs>;
///Master Timer Repetition Register
pub mod repr;
/**CMP1R (rw) register accessor: Master Timer Compare 1 Register

You can [`read`](crate::Reg::read) this register and get [`cmp1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@cmp1r`] module*/
pub type CMP1R = crate::Reg<cmp1r::CMP1Rrs>;
///Master Timer Compare 1 Register
pub mod cmp1r;
pub use cmp1r as cmp2r;
pub use cmp1r as cmp3r;
pub use cmp1r as cmp4r;
pub use CMP1R as CMP2R;
pub use CMP1R as CMP3R;
pub use CMP1R as CMP4R;