stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `LLR` reader
pub type R = crate::R<LLRrs>;
///Register `LLR` writer
pub type W = crate::W<LLRrs>;
///Field `LA` reader - pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA\[15:20\] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
pub type LA_R = crate::FieldReader<u16>;
///Field `LA` writer - pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA\[15:20\] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
pub type LA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
///Field `ULL` reader - Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer.
pub type ULL_R = crate::BitReader;
///Field `ULL` writer - Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer.
pub type ULL_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UB2` reader - Update HPDMA_CxBR2 from memory This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer.
pub type UB2_R = crate::BitReader;
///Field `UB2` writer - Update HPDMA_CxBR2 from memory This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer.
pub type UB2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UT3` reader - Update HPDMA_CxTR3 from memory This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer.
pub type UT3_R = crate::BitReader;
///Field `UT3` writer - Update HPDMA_CxTR3 from memory This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer.
pub type UT3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UDA` reader - Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer.
pub type UDA_R = crate::BitReader;
///Field `UDA` writer - Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer.
pub type UDA_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `USA` reader - update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.
pub type USA_R = crate::BitReader;
///Field `USA` writer - update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.
pub type USA_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UB1` reader - Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT\[15:0\] is then restored to the programmed value after data transfer is completed and before the link transfer.
pub type UB1_R = crate::BitReader;
///Field `UB1` writer - Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT\[15:0\] is then restored to the programmed value after data transfer is completed and before the link transfer.
pub type UB1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UT2` reader - Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.
pub type UT2_R = crate::BitReader;
///Field `UT2` writer - Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.
pub type UT2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `UT1` reader - Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.
pub type UT1_R = crate::BitReader;
///Field `UT1` writer - Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.
pub type UT1_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bits 2:15 - pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA\[15:20\] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
    #[inline(always)]
    pub fn la(&self) -> LA_R {
        LA_R::new(((self.bits >> 2) & 0x3fff) as u16)
    }
    ///Bit 16 - Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer.
    #[inline(always)]
    pub fn ull(&self) -> ULL_R {
        ULL_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 25 - Update HPDMA_CxBR2 from memory This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer.
    #[inline(always)]
    pub fn ub2(&self) -> UB2_R {
        UB2_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - Update HPDMA_CxTR3 from memory This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer.
    #[inline(always)]
    pub fn ut3(&self) -> UT3_R {
        UT3_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer.
    #[inline(always)]
    pub fn uda(&self) -> UDA_R {
        UDA_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.
    #[inline(always)]
    pub fn usa(&self) -> USA_R {
        USA_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT\[15:0\] is then restored to the programmed value after data transfer is completed and before the link transfer.
    #[inline(always)]
    pub fn ub1(&self) -> UB1_R {
        UB1_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.
    #[inline(always)]
    pub fn ut2(&self) -> UT2_R {
        UT2_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.
    #[inline(always)]
    pub fn ut1(&self) -> UT1_R {
        UT1_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LLR")
            .field("la", &self.la())
            .field("ull", &self.ull())
            .field("ub2", &self.ub2())
            .field("ut3", &self.ut3())
            .field("uda", &self.uda())
            .field("usa", &self.usa())
            .field("ub1", &self.ub1())
            .field("ut2", &self.ut2())
            .field("ut1", &self.ut1())
            .finish()
    }
}
impl W {
    ///Bits 2:15 - pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA\[15:20\] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list HPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and HPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
    #[inline(always)]
    pub fn la(&mut self) -> LA_W<LLRrs> {
        LA_W::new(self, 2)
    }
    ///Bit 16 - Update HPDMA_CxLLR register from memory This bit is used to control the update of HPDMA_CxLLR from the memory during the link transfer.
    #[inline(always)]
    pub fn ull(&mut self) -> ULL_W<LLRrs> {
        ULL_W::new(self, 16)
    }
    ///Bit 25 - Update HPDMA_CxBR2 from memory This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer.
    #[inline(always)]
    pub fn ub2(&mut self) -> UB2_W<LLRrs> {
        UB2_W::new(self, 25)
    }
    ///Bit 26 - Update HPDMA_CxTR3 from memory This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer.
    #[inline(always)]
    pub fn ut3(&mut self) -> UT3_W<LLRrs> {
        UT3_W::new(self, 26)
    }
    ///Bit 27 - Update HPDMA_CxDAR register from memory This bit is used to control the update of HPDMA_CxDAR from the memory during the link transfer.
    #[inline(always)]
    pub fn uda(&mut self) -> UDA_W<LLRrs> {
        UDA_W::new(self, 27)
    }
    ///Bit 28 - update HPDMA_CxSAR from memory This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.
    #[inline(always)]
    pub fn usa(&mut self) -> USA_W<LLRrs> {
        USA_W::new(self, 28)
    }
    ///Bit 29 - Update HPDMA_CxBR1 from memory This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if HPDMA_CxLLR different from 0, the linked-list is not completed. HPDMA_CxBR1.BNDT\[15:0\] is then restored to the programmed value after data transfer is completed and before the link transfer.
    #[inline(always)]
    pub fn ub1(&mut self) -> UB1_W<LLRrs> {
        UB1_W::new(self, 29)
    }
    ///Bit 30 - Update HPDMA_CxTR2 from memory This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.
    #[inline(always)]
    pub fn ut2(&mut self) -> UT2_W<LLRrs> {
        UT2_W::new(self, 30)
    }
    ///Bit 31 - Update HPDMA_CxTR1 from memory This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.
    #[inline(always)]
    pub fn ut1(&mut self) -> UT1_W<LLRrs> {
        UT1_W::new(self, 31)
    }
}
/**HPDMA channel 12 alternate linked-list address register

You can [`read`](crate::Reg::read) this register and get [`llr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`llr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct LLRrs;
impl crate::RegisterSpec for LLRrs {
    type Ux = u32;
}
///`read()` method returns [`llr::R`](R) reader structure
impl crate::Readable for LLRrs {}
///`write(|w| ..)` method takes [`llr::W`](W) writer structure
impl crate::Writable for LLRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets LLR to value 0
impl crate::Resettable for LLRrs {}