stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153

#[repr(C)]
#[derive(Debug)]
///Register block
pub struct RegisterBlock {
    cr: CR,
    sr: SR,
    fcr: FCR,
    _reserved3: [u8; 0x04],
    dvr: DVR,
    dar: DAR,
    _reserved5: [u8; 0x08],
    b0cr: B0CR,
    b1cr: B1CR,
    b2cr: B2CR,
    b3cr: B3CR,
    _reserved9: [u8; 0x0fd0],
    lut: [LUT; 1024],
}
impl RegisterBlock {
    ///0x00 - GFXMMU configuration register
    #[inline(always)]
    pub const fn cr(&self) -> &CR {
        &self.cr
    }
    ///0x04 - GFXMMU status register
    #[inline(always)]
    pub const fn sr(&self) -> &SR {
        &self.sr
    }
    ///0x08 - GFXMMU flag clear register
    #[inline(always)]
    pub const fn fcr(&self) -> &FCR {
        &self.fcr
    }
    ///0x10 - GFXMMU default value register
    #[inline(always)]
    pub const fn dvr(&self) -> &DVR {
        &self.dvr
    }
    ///0x14 - GFXMMU default alpha register
    #[inline(always)]
    pub const fn dar(&self) -> &DAR {
        &self.dar
    }
    ///0x20 - GFXMMU buffer 0 configuration register
    #[inline(always)]
    pub const fn b0cr(&self) -> &B0CR {
        &self.b0cr
    }
    ///0x24 - GFXMMU buffer 1 configuration register
    #[inline(always)]
    pub const fn b1cr(&self) -> &B1CR {
        &self.b1cr
    }
    ///0x28 - GFXMMU buffer 2 configuration register
    #[inline(always)]
    pub const fn b2cr(&self) -> &B2CR {
        &self.b2cr
    }
    ///0x2c - GFXMMU buffer 3 configuration register
    #[inline(always)]
    pub const fn b3cr(&self) -> &B3CR {
        &self.b3cr
    }
    ///0x1000..0x3000 - Cluster LUT%s, containing LUT*L, LUT*H
    #[inline(always)]
    pub const fn lut(&self, n: usize) -> &LUT {
        &self.lut[n]
    }
    ///Iterator for array of:
    ///0x1000..0x3000 - Cluster LUT%s, containing LUT*L, LUT*H
    #[inline(always)]
    pub fn lut_iter(&self) -> impl Iterator<Item = &LUT> {
        self.lut.iter()
    }
}
/**CR (rw) register accessor: GFXMMU configuration register

You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@cr`] module*/
pub type CR = crate::Reg<cr::CRrs>;
///GFXMMU configuration register
pub mod cr;
/**SR (r) register accessor: GFXMMU status register

You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@sr`] module*/
pub type SR = crate::Reg<sr::SRrs>;
///GFXMMU status register
pub mod sr;
/**FCR (rw) register accessor: GFXMMU flag clear register

You can [`read`](crate::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@fcr`] module*/
pub type FCR = crate::Reg<fcr::FCRrs>;
///GFXMMU flag clear register
pub mod fcr;
/**DVR (rw) register accessor: GFXMMU default value register

You can [`read`](crate::Reg::read) this register and get [`dvr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@dvr`] module*/
pub type DVR = crate::Reg<dvr::DVRrs>;
///GFXMMU default value register
pub mod dvr;
/**DAR (rw) register accessor: GFXMMU default alpha register

You can [`read`](crate::Reg::read) this register and get [`dar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@dar`] module*/
pub type DAR = crate::Reg<dar::DARrs>;
///GFXMMU default alpha register
pub mod dar;
/**B0CR (rw) register accessor: GFXMMU buffer 0 configuration register

You can [`read`](crate::Reg::read) this register and get [`b0cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`b0cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@b0cr`] module*/
pub type B0CR = crate::Reg<b0cr::B0CRrs>;
///GFXMMU buffer 0 configuration register
pub mod b0cr;
/**B1CR (rw) register accessor: GFXMMU buffer 1 configuration register

You can [`read`](crate::Reg::read) this register and get [`b1cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`b1cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@b1cr`] module*/
pub type B1CR = crate::Reg<b1cr::B1CRrs>;
///GFXMMU buffer 1 configuration register
pub mod b1cr;
/**B2CR (rw) register accessor: GFXMMU buffer 2 configuration register

You can [`read`](crate::Reg::read) this register and get [`b2cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`b2cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@b2cr`] module*/
pub type B2CR = crate::Reg<b2cr::B2CRrs>;
///GFXMMU buffer 2 configuration register
pub mod b2cr;
/**B3CR (rw) register accessor: GFXMMU buffer 3 configuration register

You can [`read`](crate::Reg::read) this register and get [`b3cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`b3cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [`mod@b3cr`] module*/
pub type B3CR = crate::Reg<b3cr::B3CRrs>;
///GFXMMU buffer 3 configuration register
pub mod b3cr;
///Cluster LUT%s, containing LUT*L, LUT*H
pub use self::lut::LUT;
///Cluster
///Cluster LUT%s, containing LUT*L, LUT*H
pub mod lut;