///Register `ECCR` reader
pub type R = crate::R<ECCRrs>;
///Field `ECC` reader - ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields.
pub type ECC_R = crate::FieldReader<u32>;
impl R {
///Bits 0:31 - ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields.
#[inline(always)]
pub fn ecc(&self) -> ECC_R {
ECC_R::new(self.bits)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECCR").field("ecc", &self.ecc()).finish()
}
}
/**This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
You can [`read`](crate::Reg::read) this register and get [`eccr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct ECCRrs;
impl crate::RegisterSpec for ECCRrs {
type Ux = u32;
}
///`read()` method returns [`eccr::R`](R) reader structure
impl crate::Readable for ECCRrs {}
///`reset()` method sets ECCR to value 0
impl crate::Resettable for ECCRrs {}