///Register `SR` reader
pub type R = crate::R<SRrs>;
///Field `BSY` reader - Bank 1 busy flag BSY1 flag is set when an effective write, erase or option byte change operation is ongoing on bank 1. It is not possible to know what type of operation is being executed. BSY1 cannot be forced to 0. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes.
pub type BSY_R = crate::BitReader;
///Field `WBNE` reader - Bank 1 write buffer not empty flag WBNE1 flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE1 is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW1 bit in FLASH_CR1 the embedded Flash memory detects an error that involves data loss the application software has disabled write operations in this bank This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data.
pub type WBNE_R = crate::BitReader;
///Field `QW` reader - Bank 1 wait queue flag QW1 flag is set when a write, erase or option byte change operation is pending in the command queue buffer of bank 1. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested.
pub type QW_R = crate::BitReader;
///Field `CRC_BUSY` reader - Bank 1 CRC busy flag CRC_BUSY1 flag is set when a CRC calculation is ongoing on bank 1. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation on bank 1.
pub type CRC_BUSY_R = crate::BitReader;
///Field `EOP` reader - Bank 1 end-of-program flag EOP1 flag is set when a programming operation to bank 1 completes. An interrupt is generated if the EOPIE1 is set to 1. It is not necessary to reset EOP1 before starting a new operation. EOP1 bit is cleared by writing 1 to CLR_EOP1 bit in FLASH_CCR1 register.
pub type EOP_R = crate::BitReader;
///Field `WRPERR` reader - Bank 1 write protection error flag WRPERR1 flag is raised when a protection error occurs during a program operation to bank 1. An interrupt is also generated if the WRPERRIE1 is set to 1. Writing 1 to CLR_WRPERR1 bit in FLASH_CCR1 register clears WRPERR1.
pub type WRPERR_R = crate::BitReader;
///Field `PGSERR` reader - Bank 1 programming sequence error flag PGSERR1 flag is raised when a sequence error occurs on bank 1. An interrupt is generated if the PGSERRIE1 bit is set to 1. Writing 1 to CLR_PGSERR1 bit in FLASH_CCR1 register clears PGSERR1.
pub type PGSERR_R = crate::BitReader;
///Field `STRBERR` reader - Bank 1 strobe error flag STRBERR1 flag is raised when a strobe error occurs on bank 1 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE1 bit is set to 1. Writing 1 to CLR_STRBERR1 bit in FLASH_CCR1 register clears STRBERR1.
pub type STRBERR_R = crate::BitReader;
///Field `INCERR` reader - Bank 1 inconsistency error flag INCERR1 flag is raised when a inconsistency error occurs on bank 1. An interrupt is generated if INCERRIE1 is set to 1. Writing 1 to CLR_INCERR1 bit in the FLASH_CCR1 register clears INCERR1.
pub type INCERR_R = crate::BitReader;
///Field `RDPERR` reader - Bank 1 read protection error flag RDPERR1 flag is raised when an read protection error (read access to a PCROP-protected or a RDP-protected area) occurs on bank 1. An interrupt is generated if RDPERRIE1 is set to 1. Writing 1 to CLR_RDPERR1 bit in FLASH_CCR1 register clears RDPERR1.
pub type RDPERR_R = crate::BitReader;
///Field `RDSERR` reader - Bank 1 secure error flag RDSERR1 flag is raised when a read secure error (read access to a secure-only protected word) occurs on bank 1. An interrupt is generated if RDSERRIE1 is set to 1. Writing 1 to CLR_RDSERR1 bit in FLASH_CCR1 register clears RDSERR1.
pub type RDSERR_R = crate::BitReader;
///Field `SNECCERR` reader - Bank 1 single correction error flag SNECCERR1 flag is raised when an ECC single correction error occurs during a read operation from bank 1. An interrupt is generated if SNECCERRIE1 is set to 1. Writing 1 to CLR_SNECCERR1 bit in FLASH_CCR1 register clears SNECCERR1.
pub type SNECCERR_R = crate::BitReader;
///Field `DBECCERR` reader - Bank 1 ECC double detection error flag DBECCERR1 flag is raised when an ECC double detection error occurs during a read operation from bank 1. An interrupt is generated if DBECCERRIE1 is set to 1. Writing 1 to CLR_DBECCERR1 bit in FLASH_CCR1 register clears DBECCERR1.
pub type DBECCERR_R = crate::BitReader;
///Field `CRCEND` reader - Bank 1 CRC end of calculation flag CRCEND1 bit is raised when the CRC computation has completed on bank 1. An interrupt is generated if CRCENDIE1 is set to 1. It is not necessary to reset CRCEND1 before restarting CRC computation. Writing 1 to CLR_CRCEND1 bit in FLASH_CCR1 register clears CRCEND1.
pub type CRCEND_R = crate::BitReader;
///Field `CRCRDERR` reader - Bank 1 CRC read error flag CRCRDERR1 flag is raised when a word is found read protected during a CRC operation on bank 1. An interrupt is generated if CRCRDIE1 and CRCEND1 are set to 1. Writing 1 to CLR_CRCRDERR1 bit in FLASH_CCR1 register clears CRCRDERR1. Note: This flag is valid only when CRCEND1 bit is set to 1
pub type CRCRDERR_R = crate::BitReader;
impl R {
///Bit 0 - Bank 1 busy flag BSY1 flag is set when an effective write, erase or option byte change operation is ongoing on bank 1. It is not possible to know what type of operation is being executed. BSY1 cannot be forced to 0. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes.
#[inline(always)]
pub fn bsy(&self) -> BSY_R {
BSY_R::new((self.bits & 1) != 0)
}
///Bit 1 - Bank 1 write buffer not empty flag WBNE1 flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE1 is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW1 bit in FLASH_CR1 the embedded Flash memory detects an error that involves data loss the application software has disabled write operations in this bank This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data.
#[inline(always)]
pub fn wbne(&self) -> WBNE_R {
WBNE_R::new(((self.bits >> 1) & 1) != 0)
}
///Bit 2 - Bank 1 wait queue flag QW1 flag is set when a write, erase or option byte change operation is pending in the command queue buffer of bank 1. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested.
#[inline(always)]
pub fn qw(&self) -> QW_R {
QW_R::new(((self.bits >> 2) & 1) != 0)
}
///Bit 3 - Bank 1 CRC busy flag CRC_BUSY1 flag is set when a CRC calculation is ongoing on bank 1. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation on bank 1.
#[inline(always)]
pub fn crc_busy(&self) -> CRC_BUSY_R {
CRC_BUSY_R::new(((self.bits >> 3) & 1) != 0)
}
///Bit 16 - Bank 1 end-of-program flag EOP1 flag is set when a programming operation to bank 1 completes. An interrupt is generated if the EOPIE1 is set to 1. It is not necessary to reset EOP1 before starting a new operation. EOP1 bit is cleared by writing 1 to CLR_EOP1 bit in FLASH_CCR1 register.
#[inline(always)]
pub fn eop(&self) -> EOP_R {
EOP_R::new(((self.bits >> 16) & 1) != 0)
}
///Bit 17 - Bank 1 write protection error flag WRPERR1 flag is raised when a protection error occurs during a program operation to bank 1. An interrupt is also generated if the WRPERRIE1 is set to 1. Writing 1 to CLR_WRPERR1 bit in FLASH_CCR1 register clears WRPERR1.
#[inline(always)]
pub fn wrperr(&self) -> WRPERR_R {
WRPERR_R::new(((self.bits >> 17) & 1) != 0)
}
///Bit 18 - Bank 1 programming sequence error flag PGSERR1 flag is raised when a sequence error occurs on bank 1. An interrupt is generated if the PGSERRIE1 bit is set to 1. Writing 1 to CLR_PGSERR1 bit in FLASH_CCR1 register clears PGSERR1.
#[inline(always)]
pub fn pgserr(&self) -> PGSERR_R {
PGSERR_R::new(((self.bits >> 18) & 1) != 0)
}
///Bit 19 - Bank 1 strobe error flag STRBERR1 flag is raised when a strobe error occurs on bank 1 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE1 bit is set to 1. Writing 1 to CLR_STRBERR1 bit in FLASH_CCR1 register clears STRBERR1.
#[inline(always)]
pub fn strberr(&self) -> STRBERR_R {
STRBERR_R::new(((self.bits >> 19) & 1) != 0)
}
///Bit 21 - Bank 1 inconsistency error flag INCERR1 flag is raised when a inconsistency error occurs on bank 1. An interrupt is generated if INCERRIE1 is set to 1. Writing 1 to CLR_INCERR1 bit in the FLASH_CCR1 register clears INCERR1.
#[inline(always)]
pub fn incerr(&self) -> INCERR_R {
INCERR_R::new(((self.bits >> 21) & 1) != 0)
}
///Bit 23 - Bank 1 read protection error flag RDPERR1 flag is raised when an read protection error (read access to a PCROP-protected or a RDP-protected area) occurs on bank 1. An interrupt is generated if RDPERRIE1 is set to 1. Writing 1 to CLR_RDPERR1 bit in FLASH_CCR1 register clears RDPERR1.
#[inline(always)]
pub fn rdperr(&self) -> RDPERR_R {
RDPERR_R::new(((self.bits >> 23) & 1) != 0)
}
///Bit 24 - Bank 1 secure error flag RDSERR1 flag is raised when a read secure error (read access to a secure-only protected word) occurs on bank 1. An interrupt is generated if RDSERRIE1 is set to 1. Writing 1 to CLR_RDSERR1 bit in FLASH_CCR1 register clears RDSERR1.
#[inline(always)]
pub fn rdserr(&self) -> RDSERR_R {
RDSERR_R::new(((self.bits >> 24) & 1) != 0)
}
///Bit 25 - Bank 1 single correction error flag SNECCERR1 flag is raised when an ECC single correction error occurs during a read operation from bank 1. An interrupt is generated if SNECCERRIE1 is set to 1. Writing 1 to CLR_SNECCERR1 bit in FLASH_CCR1 register clears SNECCERR1.
#[inline(always)]
pub fn sneccerr(&self) -> SNECCERR_R {
SNECCERR_R::new(((self.bits >> 25) & 1) != 0)
}
///Bit 26 - Bank 1 ECC double detection error flag DBECCERR1 flag is raised when an ECC double detection error occurs during a read operation from bank 1. An interrupt is generated if DBECCERRIE1 is set to 1. Writing 1 to CLR_DBECCERR1 bit in FLASH_CCR1 register clears DBECCERR1.
#[inline(always)]
pub fn dbeccerr(&self) -> DBECCERR_R {
DBECCERR_R::new(((self.bits >> 26) & 1) != 0)
}
///Bit 27 - Bank 1 CRC end of calculation flag CRCEND1 bit is raised when the CRC computation has completed on bank 1. An interrupt is generated if CRCENDIE1 is set to 1. It is not necessary to reset CRCEND1 before restarting CRC computation. Writing 1 to CLR_CRCEND1 bit in FLASH_CCR1 register clears CRCEND1.
#[inline(always)]
pub fn crcend(&self) -> CRCEND_R {
CRCEND_R::new(((self.bits >> 27) & 1) != 0)
}
///Bit 28 - Bank 1 CRC read error flag CRCRDERR1 flag is raised when a word is found read protected during a CRC operation on bank 1. An interrupt is generated if CRCRDIE1 and CRCEND1 are set to 1. Writing 1 to CLR_CRCRDERR1 bit in FLASH_CCR1 register clears CRCRDERR1. Note: This flag is valid only when CRCEND1 bit is set to 1
#[inline(always)]
pub fn crcrderr(&self) -> CRCRDERR_R {
CRCRDERR_R::new(((self.bits >> 28) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SR")
.field("bsy", &self.bsy())
.field("wbne", &self.wbne())
.field("qw", &self.qw())
.field("crc_busy", &self.crc_busy())
.field("eop", &self.eop())
.field("wrperr", &self.wrperr())
.field("pgserr", &self.pgserr())
.field("strberr", &self.strberr())
.field("incerr", &self.incerr())
.field("rdperr", &self.rdperr())
.field("rdserr", &self.rdserr())
.field("sneccerr", &self.sneccerr())
.field("dbeccerr", &self.dbeccerr())
.field("crcend", &self.crcend())
.field("crcrderr", &self.crcrderr())
.finish()
}
}
/**
You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct SRrs;
impl crate::RegisterSpec for SRrs {
type Ux = u32;
}
///`read()` method returns [`sr::R`](R) reader structure
impl crate::Readable for SRrs {}
///`reset()` method sets SR to value 0
impl crate::Resettable for SRrs {}