stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269

///Register `OPTSR_PRG` reader
pub type R = crate::R<OPTSR_PRGrs>;
///Register `OPTSR_PRG` writer
pub type W = crate::W<OPTSR_PRGrs>;
///Field `BOR_LEV` reader - Brownout level option configuration bit
pub type BOR_LEV_R = crate::FieldReader;
///Field `BOR_LEV` writer - Brownout level option configuration bit
pub type BOR_LEV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
///Field `IWDG_SW` reader - IWDG control mode option configuration bit
pub type IWDG_SW_R = crate::BitReader;
///Field `IWDG_SW` writer - IWDG control mode option configuration bit
pub type IWDG_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IWDG2_SW` reader - IWDG2 control mode option configuration bit
pub type IWDG2_SW_R = crate::BitReader;
///Field `IWDG2_SW` writer - IWDG2 control mode option configuration bit
pub type IWDG2_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `NRST_STOP_D1` reader - D1 domain DStop entry reset option configuration bit
pub type NRST_STOP_D1_R = crate::BitReader;
///Field `NRST_STOP_D1` writer - D1 domain DStop entry reset option configuration bit
pub type NRST_STOP_D1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `NRST_STDY_D1` reader - D1 domain DStandby entry reset option configuration bit
pub type NRST_STDY_D1_R = crate::BitReader;
///Field `NRST_STDY_D1` writer - D1 domain DStandby entry reset option configuration bit
pub type NRST_STDY_D1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RDP` reader - Readout protection level option configuration bits
pub type RDP_R = crate::FieldReader;
///Field `RDP` writer - Readout protection level option configuration bits
pub type RDP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
///Field `IWDG_FZ_STOP` reader - IWDG Stop mode freeze option configuration bit
pub type IWDG_FZ_STOP_R = crate::BitReader;
///Field `IWDG_FZ_STOP` writer - IWDG Stop mode freeze option configuration bit
pub type IWDG_FZ_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IWDG_FZ_SDBY` reader - IWDG Standby mode freeze option configuration bit
pub type IWDG_FZ_SDBY_R = crate::BitReader;
///Field `IWDG_FZ_SDBY` writer - IWDG Standby mode freeze option configuration bit
pub type IWDG_FZ_SDBY_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ST_RAM_SIZE` reader - ST RAM size option configuration bits
pub type ST_RAM_SIZE_R = crate::FieldReader;
///Field `ST_RAM_SIZE` writer - ST RAM size option configuration bits
pub type ST_RAM_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
///Field `SECURITY` reader - Security enable option configuration bit
pub type SECURITY_R = crate::BitReader;
///Field `SECURITY` writer - Security enable option configuration bit
pub type SECURITY_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `BOOT_CM4` reader - Arm Cortex
pub type BOOT_CM4_R = crate::BitReader;
///Field `BOOT_CM4` writer - Arm Cortex
pub type BOOT_CM4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `BOOT_CM7` reader - Arm Cortex
pub type BOOT_CM7_R = crate::BitReader;
///Field `BOOT_CM7` writer - Arm Cortex
pub type BOOT_CM7_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `NRST_STOP_D2` reader - D2 domain DStop entry reset option configuration bit
pub type NRST_STOP_D2_R = crate::BitReader;
///Field `NRST_STOP_D2` writer - D2 domain DStop entry reset option configuration bit
pub type NRST_STOP_D2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `NRST_STBY_D2` reader - D2 domain DStandby entry reset option configuration bit
pub type NRST_STBY_D2_R = crate::BitReader;
///Field `NRST_STBY_D2` writer - D2 domain DStandby entry reset option configuration bit
pub type NRST_STBY_D2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IO_HSLV` reader - I
pub type IO_HSLV_R = crate::BitReader;
///Field `IO_HSLV` writer - I
pub type IO_HSLV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SWAP_BANK_OPT` reader - Bank swapping option configuration bit
pub type SWAP_BANK_OPT_R = crate::BitReader;
///Field `SWAP_BANK_OPT` writer - Bank swapping option configuration bit
pub type SWAP_BANK_OPT_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bits 2:3 - Brownout level option configuration bit
    #[inline(always)]
    pub fn bor_lev(&self) -> BOR_LEV_R {
        BOR_LEV_R::new(((self.bits >> 2) & 3) as u8)
    }
    ///Bit 4 - IWDG control mode option configuration bit
    #[inline(always)]
    pub fn iwdg_sw(&self) -> IWDG_SW_R {
        IWDG_SW_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - IWDG2 control mode option configuration bit
    #[inline(always)]
    pub fn iwdg2_sw(&self) -> IWDG2_SW_R {
        IWDG2_SW_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - D1 domain DStop entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stop_d1(&self) -> NRST_STOP_D1_R {
        NRST_STOP_D1_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - D1 domain DStandby entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stdy_d1(&self) -> NRST_STDY_D1_R {
        NRST_STDY_D1_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bits 8:15 - Readout protection level option configuration bits
    #[inline(always)]
    pub fn rdp(&self) -> RDP_R {
        RDP_R::new(((self.bits >> 8) & 0xff) as u8)
    }
    ///Bit 17 - IWDG Stop mode freeze option configuration bit
    #[inline(always)]
    pub fn iwdg_fz_stop(&self) -> IWDG_FZ_STOP_R {
        IWDG_FZ_STOP_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - IWDG Standby mode freeze option configuration bit
    #[inline(always)]
    pub fn iwdg_fz_sdby(&self) -> IWDG_FZ_SDBY_R {
        IWDG_FZ_SDBY_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bits 19:20 - ST RAM size option configuration bits
    #[inline(always)]
    pub fn st_ram_size(&self) -> ST_RAM_SIZE_R {
        ST_RAM_SIZE_R::new(((self.bits >> 19) & 3) as u8)
    }
    ///Bit 21 - Security enable option configuration bit
    #[inline(always)]
    pub fn security(&self) -> SECURITY_R {
        SECURITY_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - Arm Cortex
    #[inline(always)]
    pub fn boot_cm4(&self) -> BOOT_CM4_R {
        BOOT_CM4_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - Arm Cortex
    #[inline(always)]
    pub fn boot_cm7(&self) -> BOOT_CM7_R {
        BOOT_CM7_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - D2 domain DStop entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stop_d2(&self) -> NRST_STOP_D2_R {
        NRST_STOP_D2_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - D2 domain DStandby entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stby_d2(&self) -> NRST_STBY_D2_R {
        NRST_STBY_D2_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 29 - I
    #[inline(always)]
    pub fn io_hslv(&self) -> IO_HSLV_R {
        IO_HSLV_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 31 - Bank swapping option configuration bit
    #[inline(always)]
    pub fn swap_bank_opt(&self) -> SWAP_BANK_OPT_R {
        SWAP_BANK_OPT_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPTSR_PRG")
            .field("swap_bank_opt", &self.swap_bank_opt())
            .field("io_hslv", &self.io_hslv())
            .field("nrst_stby_d2", &self.nrst_stby_d2())
            .field("nrst_stop_d2", &self.nrst_stop_d2())
            .field("boot_cm7", &self.boot_cm7())
            .field("boot_cm4", &self.boot_cm4())
            .field("security", &self.security())
            .field("st_ram_size", &self.st_ram_size())
            .field("iwdg_fz_sdby", &self.iwdg_fz_sdby())
            .field("iwdg_fz_stop", &self.iwdg_fz_stop())
            .field("rdp", &self.rdp())
            .field("nrst_stdy_d1", &self.nrst_stdy_d1())
            .field("nrst_stop_d1", &self.nrst_stop_d1())
            .field("iwdg2_sw", &self.iwdg2_sw())
            .field("iwdg_sw", &self.iwdg_sw())
            .field("bor_lev", &self.bor_lev())
            .finish()
    }
}
impl W {
    ///Bits 2:3 - Brownout level option configuration bit
    #[inline(always)]
    pub fn bor_lev(&mut self) -> BOR_LEV_W<OPTSR_PRGrs> {
        BOR_LEV_W::new(self, 2)
    }
    ///Bit 4 - IWDG control mode option configuration bit
    #[inline(always)]
    pub fn iwdg_sw(&mut self) -> IWDG_SW_W<OPTSR_PRGrs> {
        IWDG_SW_W::new(self, 4)
    }
    ///Bit 5 - IWDG2 control mode option configuration bit
    #[inline(always)]
    pub fn iwdg2_sw(&mut self) -> IWDG2_SW_W<OPTSR_PRGrs> {
        IWDG2_SW_W::new(self, 5)
    }
    ///Bit 6 - D1 domain DStop entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stop_d1(&mut self) -> NRST_STOP_D1_W<OPTSR_PRGrs> {
        NRST_STOP_D1_W::new(self, 6)
    }
    ///Bit 7 - D1 domain DStandby entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stdy_d1(&mut self) -> NRST_STDY_D1_W<OPTSR_PRGrs> {
        NRST_STDY_D1_W::new(self, 7)
    }
    ///Bits 8:15 - Readout protection level option configuration bits
    #[inline(always)]
    pub fn rdp(&mut self) -> RDP_W<OPTSR_PRGrs> {
        RDP_W::new(self, 8)
    }
    ///Bit 17 - IWDG Stop mode freeze option configuration bit
    #[inline(always)]
    pub fn iwdg_fz_stop(&mut self) -> IWDG_FZ_STOP_W<OPTSR_PRGrs> {
        IWDG_FZ_STOP_W::new(self, 17)
    }
    ///Bit 18 - IWDG Standby mode freeze option configuration bit
    #[inline(always)]
    pub fn iwdg_fz_sdby(&mut self) -> IWDG_FZ_SDBY_W<OPTSR_PRGrs> {
        IWDG_FZ_SDBY_W::new(self, 18)
    }
    ///Bits 19:20 - ST RAM size option configuration bits
    #[inline(always)]
    pub fn st_ram_size(&mut self) -> ST_RAM_SIZE_W<OPTSR_PRGrs> {
        ST_RAM_SIZE_W::new(self, 19)
    }
    ///Bit 21 - Security enable option configuration bit
    #[inline(always)]
    pub fn security(&mut self) -> SECURITY_W<OPTSR_PRGrs> {
        SECURITY_W::new(self, 21)
    }
    ///Bit 22 - Arm Cortex
    #[inline(always)]
    pub fn boot_cm4(&mut self) -> BOOT_CM4_W<OPTSR_PRGrs> {
        BOOT_CM4_W::new(self, 22)
    }
    ///Bit 23 - Arm Cortex
    #[inline(always)]
    pub fn boot_cm7(&mut self) -> BOOT_CM7_W<OPTSR_PRGrs> {
        BOOT_CM7_W::new(self, 23)
    }
    ///Bit 24 - D2 domain DStop entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stop_d2(&mut self) -> NRST_STOP_D2_W<OPTSR_PRGrs> {
        NRST_STOP_D2_W::new(self, 24)
    }
    ///Bit 25 - D2 domain DStandby entry reset option configuration bit
    #[inline(always)]
    pub fn nrst_stby_d2(&mut self) -> NRST_STBY_D2_W<OPTSR_PRGrs> {
        NRST_STBY_D2_W::new(self, 25)
    }
    ///Bit 29 - I
    #[inline(always)]
    pub fn io_hslv(&mut self) -> IO_HSLV_W<OPTSR_PRGrs> {
        IO_HSLV_W::new(self, 29)
    }
    ///Bit 31 - Bank swapping option configuration bit
    #[inline(always)]
    pub fn swap_bank_opt(&mut self) -> SWAP_BANK_OPT_W<OPTSR_PRGrs> {
        SWAP_BANK_OPT_W::new(self, 31)
    }
}
/**FLASH option status register

You can [`read`](crate::Reg::read) this register and get [`optsr_prg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`optsr_prg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct OPTSR_PRGrs;
impl crate::RegisterSpec for OPTSR_PRGrs {
    type Ux = u32;
}
///`read()` method returns [`optsr_prg::R`](R) reader structure
impl crate::Readable for OPTSR_PRGrs {}
///`write(|w| ..)` method takes [`optsr_prg::W`](W) writer structure
impl crate::Writable for OPTSR_PRGrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets OPTSR_PRG to value 0
impl crate::Resettable for OPTSR_PRGrs {}