stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `FGMAR` reader
pub type R = crate::R<FGMARrs>;
///Register `FGMAR` writer
pub type W = crate::W<FGMARrs>;
///Field `MA` reader - Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
pub type MA_R = crate::FieldReader<u32>;
///Field `MA` writer - Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
pub type MA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
    ///Bits 0:31 - Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
    #[inline(always)]
    pub fn ma(&self) -> MA_R {
        MA_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FGMAR").field("ma", &self.ma()).finish()
    }
}
impl W {
    ///Bits 0:31 - Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.
    #[inline(always)]
    pub fn ma(&mut self) -> MA_W<FGMARrs> {
        MA_W::new(self, 0)
    }
}
/**DMA2D foreground memory address register

You can [`read`](crate::Reg::read) this register and get [`fgmar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fgmar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct FGMARrs;
impl crate::RegisterSpec for FGMARrs {
    type Ux = u32;
}
///`read()` method returns [`fgmar::R`](R) reader structure
impl crate::Readable for FGMARrs {}
///`write(|w| ..)` method takes [`fgmar::W`](W) writer structure
impl crate::Writable for FGMARrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets FGMAR to value 0
impl crate::Resettable for FGMARrs {}