stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

///Register `CR` reader
pub type R = crate::R<CRrs>;
///Register `CR` writer
pub type W = crate::W<CRrs>;
///Field `DBGSLEEP_CD` reader - Allow D1 domain debug in Sleep mode
pub type DBGSLEEP_CD_R = crate::BitReader;
///Field `DBGSLEEP_CD` writer - Allow D1 domain debug in Sleep mode
pub type DBGSLEEP_CD_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DBGSTOP_CD` reader - Allow D1 domain debug in Stop mode
pub type DBGSTOP_CD_R = crate::BitReader;
///Field `DBGSTOP_CD` writer - Allow D1 domain debug in Stop mode
pub type DBGSTOP_CD_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DBGSTBY_CD` reader - Allow D1 domain debug in Standby mode
pub type DBGSTBY_CD_R = crate::BitReader;
///Field `DBGSTBY_CD` writer - Allow D1 domain debug in Standby mode
pub type DBGSTBY_CD_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DBGSTOP_SRD` reader - debug in SmartRun domain Stop mode
pub type DBGSTOP_SRD_R = crate::BitReader;
///Field `DBGSTOP_SRD` writer - debug in SmartRun domain Stop mode
pub type DBGSTOP_SRD_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DBGSTBY_SRD` reader - debug in SmartRun domain Standby mode
pub type DBGSTBY_SRD_R = crate::BitReader;
///Field `DBGSTBY_SRD` writer - debug in SmartRun domain Standby mode
pub type DBGSTBY_SRD_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TRACECLKEN` reader - Trace port clock enable
pub type TRACECLKEN_R = crate::BitReader;
///Field `TRACECLKEN` writer - Trace port clock enable
pub type TRACECLKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CDDBGCKEN` reader - CPU domain debug clock enable
pub type CDDBGCKEN_R = crate::BitReader;
///Field `CDDBGCKEN` writer - CPU domain debug clock enable
pub type CDDBGCKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SRDDBGCKEN` reader - SmartRun domain debug clock enable
pub type SRDDBGCKEN_R = crate::BitReader;
///Field `SRDDBGCKEN` writer - SmartRun domain debug clock enable
pub type SRDDBGCKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TRGOEN` reader - External trigger output enable
pub type TRGOEN_R = crate::BitReader;
///Field `TRGOEN` writer - External trigger output enable
pub type TRGOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - Allow D1 domain debug in Sleep mode
    #[inline(always)]
    pub fn dbgsleep_cd(&self) -> DBGSLEEP_CD_R {
        DBGSLEEP_CD_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Allow D1 domain debug in Stop mode
    #[inline(always)]
    pub fn dbgstop_cd(&self) -> DBGSTOP_CD_R {
        DBGSTOP_CD_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Allow D1 domain debug in Standby mode
    #[inline(always)]
    pub fn dbgstby_cd(&self) -> DBGSTBY_CD_R {
        DBGSTBY_CD_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 7 - debug in SmartRun domain Stop mode
    #[inline(always)]
    pub fn dbgstop_srd(&self) -> DBGSTOP_SRD_R {
        DBGSTOP_SRD_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - debug in SmartRun domain Standby mode
    #[inline(always)]
    pub fn dbgstby_srd(&self) -> DBGSTBY_SRD_R {
        DBGSTBY_SRD_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 20 - Trace port clock enable
    #[inline(always)]
    pub fn traceclken(&self) -> TRACECLKEN_R {
        TRACECLKEN_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - CPU domain debug clock enable
    #[inline(always)]
    pub fn cddbgcken(&self) -> CDDBGCKEN_R {
        CDDBGCKEN_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - SmartRun domain debug clock enable
    #[inline(always)]
    pub fn srddbgcken(&self) -> SRDDBGCKEN_R {
        SRDDBGCKEN_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 28 - External trigger output enable
    #[inline(always)]
    pub fn trgoen(&self) -> TRGOEN_R {
        TRGOEN_R::new(((self.bits >> 28) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CR")
            .field("dbgsleep_cd", &self.dbgsleep_cd())
            .field("dbgstop_cd", &self.dbgstop_cd())
            .field("dbgstby_cd", &self.dbgstby_cd())
            .field("dbgstop_srd", &self.dbgstop_srd())
            .field("dbgstby_srd", &self.dbgstby_srd())
            .field("traceclken", &self.traceclken())
            .field("cddbgcken", &self.cddbgcken())
            .field("srddbgcken", &self.srddbgcken())
            .field("trgoen", &self.trgoen())
            .finish()
    }
}
impl W {
    ///Bit 0 - Allow D1 domain debug in Sleep mode
    #[inline(always)]
    pub fn dbgsleep_cd(&mut self) -> DBGSLEEP_CD_W<CRrs> {
        DBGSLEEP_CD_W::new(self, 0)
    }
    ///Bit 1 - Allow D1 domain debug in Stop mode
    #[inline(always)]
    pub fn dbgstop_cd(&mut self) -> DBGSTOP_CD_W<CRrs> {
        DBGSTOP_CD_W::new(self, 1)
    }
    ///Bit 2 - Allow D1 domain debug in Standby mode
    #[inline(always)]
    pub fn dbgstby_cd(&mut self) -> DBGSTBY_CD_W<CRrs> {
        DBGSTBY_CD_W::new(self, 2)
    }
    ///Bit 7 - debug in SmartRun domain Stop mode
    #[inline(always)]
    pub fn dbgstop_srd(&mut self) -> DBGSTOP_SRD_W<CRrs> {
        DBGSTOP_SRD_W::new(self, 7)
    }
    ///Bit 8 - debug in SmartRun domain Standby mode
    #[inline(always)]
    pub fn dbgstby_srd(&mut self) -> DBGSTBY_SRD_W<CRrs> {
        DBGSTBY_SRD_W::new(self, 8)
    }
    ///Bit 20 - Trace port clock enable
    #[inline(always)]
    pub fn traceclken(&mut self) -> TRACECLKEN_W<CRrs> {
        TRACECLKEN_W::new(self, 20)
    }
    ///Bit 21 - CPU domain debug clock enable
    #[inline(always)]
    pub fn cddbgcken(&mut self) -> CDDBGCKEN_W<CRrs> {
        CDDBGCKEN_W::new(self, 21)
    }
    ///Bit 22 - SmartRun domain debug clock enable
    #[inline(always)]
    pub fn srddbgcken(&mut self) -> SRDDBGCKEN_W<CRrs> {
        SRDDBGCKEN_W::new(self, 22)
    }
    ///Bit 28 - External trigger output enable
    #[inline(always)]
    pub fn trgoen(&mut self) -> TRGOEN_W<CRrs> {
        TRGOEN_W::new(self, 28)
    }
}
/**DBGMCU Configuration Register

You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CRrs;
impl crate::RegisterSpec for CRrs {
    type Ux = u32;
}
///`read()` method returns [`cr::R`](R) reader structure
impl crate::Readable for CRrs {}
///`write(|w| ..)` method takes [`cr::W`](W) writer structure
impl crate::Writable for CRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CR to value 0
impl crate::Resettable for CRrs {}