stm32h7 0.5.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - PWR control register 1"]
    pub pwr_cr1: PWR_CR1,
    #[doc = "0x04 - PWR control status register 1"]
    pub pwr_csr1: PWR_CSR1,
    #[doc = "0x08 - This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection."]
    pub pwr_cr2: PWR_CR2,
    #[doc = "0x0c - Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value."]
    pub pwr_cr3: PWR_CR3,
    #[doc = "0x10 - This register allows controlling CPU1 power."]
    pub pwr_cpucr: PWR_CPUCR,
    _reserved0: [u8; 4usize],
    #[doc = "0x18 - This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software"]
    pub pwr_d3cr: PWR_D3CR,
    _reserved1: [u8; 4usize],
    #[doc = "0x20 - reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)."]
    pub pwr_wkupcr: PWR_WKUPCR,
    #[doc = "0x24 - reset only by system reset, not reset by wakeup from Standby mode"]
    pub pwr_wkupfr: PWR_WKUPFR,
    #[doc = "0x28 - Reset only by system reset, not reset by wakeup from Standby mode"]
    pub pwr_wkupepr: PWR_WKUPEPR,
}
#[doc = "PWR control register 1"]
pub struct PWR_CR1 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWR control register 1"]
pub mod pwr_cr1;
#[doc = "PWR control status register 1"]
pub struct PWR_CSR1 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "PWR control status register 1"]
pub mod pwr_csr1;
#[doc = "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection."]
pub struct PWR_CR2 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection."]
pub mod pwr_cr2;
#[doc = "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value."]
pub struct PWR_CR3 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value."]
pub mod pwr_cr3;
#[doc = "This register allows controlling CPU1 power."]
pub struct PWR_CPUCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "This register allows controlling CPU1 power."]
pub mod pwr_cpucr;
#[doc = "This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software"]
pub struct PWR_D3CR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software"]
pub mod pwr_d3cr;
#[doc = "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)."]
pub struct PWR_WKUPCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)."]
pub mod pwr_wkupcr;
#[doc = "reset only by system reset, not reset by wakeup from Standby mode"]
pub struct PWR_WKUPFR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "reset only by system reset, not reset by wakeup from Standby mode"]
pub mod pwr_wkupfr;
#[doc = "Reset only by system reset, not reset by wakeup from Standby mode"]
pub struct PWR_WKUPEPR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Reset only by system reset, not reset by wakeup from Standby mode"]
pub mod pwr_wkupepr;