stm32h7 0.5.0

Device support crates for STM32H7 devices
Documentation 
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#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - DMA2D control register"]
    pub dma2d_cr: DMA2D_CR,
    #[doc = "0x04 - DMA2D Interrupt Status Register"]
    pub dma2d_isr: DMA2D_ISR,
    #[doc = "0x08 - DMA2D interrupt flag clear register"]
    pub dma2d_ifcr: DMA2D_IFCR,
    #[doc = "0x0c - DMA2D foreground memory address register"]
    pub dma2d_fgmar: DMA2D_FGMAR,
    #[doc = "0x10 - DMA2D foreground offset register"]
    pub dma2d_fgor: DMA2D_FGOR,
    #[doc = "0x14 - DMA2D background memory address register"]
    pub dma2d_bgmar: DMA2D_BGMAR,
    #[doc = "0x18 - DMA2D background offset register"]
    pub dma2d_bgor: DMA2D_BGOR,
    #[doc = "0x1c - DMA2D foreground PFC control register"]
    pub dma2d_fgpfccr: DMA2D_FGPFCCR,
    #[doc = "0x20 - DMA2D foreground color register"]
    pub dma2d_fgcolr: DMA2D_FGCOLR,
    #[doc = "0x24 - DMA2D background PFC control register"]
    pub dma2d_bgpfccr: DMA2D_BGPFCCR,
    #[doc = "0x28 - DMA2D background color register"]
    pub dma2d_bgcolr: DMA2D_BGCOLR,
    #[doc = "0x2c - DMA2D foreground CLUT memory address register"]
    pub dma2d_fgcmar: DMA2D_FGCMAR,
    #[doc = "0x30 - DMA2D background CLUT memory address register"]
    pub dma2d_bgcmar: DMA2D_BGCMAR,
    #[doc = "0x34 - DMA2D output PFC control register"]
    pub dma2d_opfccr: DMA2D_OPFCCR,
    #[doc = "0x38 - DMA2D output color register"]
    pub dma2d_ocolr: DMA2D_OCOLR,
    #[doc = "0x3c - DMA2D output memory address register"]
    pub dma2d_omar: DMA2D_OMAR,
    #[doc = "0x40 - DMA2D output offset register"]
    pub dma2d_oor: DMA2D_OOR,
    #[doc = "0x44 - DMA2D number of line register"]
    pub dma2d_nlr: DMA2D_NLR,
    #[doc = "0x48 - DMA2D line watermark register"]
    pub dma2d_lwr: DMA2D_LWR,
    #[doc = "0x4c - DMA2D AXI master timer configuration register"]
    pub dma2d_amtcr: DMA2D_AMTCR,
}
#[doc = "DMA2D control register"]
pub struct DMA2D_CR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D control register"]
pub mod dma2d_cr;
#[doc = "DMA2D Interrupt Status Register"]
pub struct DMA2D_ISR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D Interrupt Status Register"]
pub mod dma2d_isr;
#[doc = "DMA2D interrupt flag clear register"]
pub struct DMA2D_IFCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D interrupt flag clear register"]
pub mod dma2d_ifcr;
#[doc = "DMA2D foreground memory address register"]
pub struct DMA2D_FGMAR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D foreground memory address register"]
pub mod dma2d_fgmar;
#[doc = "DMA2D foreground offset register"]
pub struct DMA2D_FGOR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D foreground offset register"]
pub mod dma2d_fgor;
#[doc = "DMA2D background memory address register"]
pub struct DMA2D_BGMAR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D background memory address register"]
pub mod dma2d_bgmar;
#[doc = "DMA2D background offset register"]
pub struct DMA2D_BGOR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D background offset register"]
pub mod dma2d_bgor;
#[doc = "DMA2D foreground PFC control register"]
pub struct DMA2D_FGPFCCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D foreground PFC control register"]
pub mod dma2d_fgpfccr;
#[doc = "DMA2D foreground color register"]
pub struct DMA2D_FGCOLR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D foreground color register"]
pub mod dma2d_fgcolr;
#[doc = "DMA2D background PFC control register"]
pub struct DMA2D_BGPFCCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D background PFC control register"]
pub mod dma2d_bgpfccr;
#[doc = "DMA2D background color register"]
pub struct DMA2D_BGCOLR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D background color register"]
pub mod dma2d_bgcolr;
#[doc = "DMA2D foreground CLUT memory address register"]
pub struct DMA2D_FGCMAR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D foreground CLUT memory address register"]
pub mod dma2d_fgcmar;
#[doc = "DMA2D background CLUT memory address register"]
pub struct DMA2D_BGCMAR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D background CLUT memory address register"]
pub mod dma2d_bgcmar;
#[doc = "DMA2D output PFC control register"]
pub struct DMA2D_OPFCCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D output PFC control register"]
pub mod dma2d_opfccr;
#[doc = "DMA2D output color register"]
pub struct DMA2D_OCOLR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D output color register"]
pub mod dma2d_ocolr;
#[doc = "DMA2D output memory address register"]
pub struct DMA2D_OMAR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D output memory address register"]
pub mod dma2d_omar;
#[doc = "DMA2D output offset register"]
pub struct DMA2D_OOR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D output offset register"]
pub mod dma2d_oor;
#[doc = "DMA2D number of line register"]
pub struct DMA2D_NLR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D number of line register"]
pub mod dma2d_nlr;
#[doc = "DMA2D line watermark register"]
pub struct DMA2D_LWR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D line watermark register"]
pub mod dma2d_lwr;
#[doc = "DMA2D AXI master timer configuration register"]
pub struct DMA2D_AMTCR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "DMA2D AXI master timer configuration register"]
pub mod dma2d_amtcr;