stm32h5/stm32h573/
tim13.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x0a],
7    dier: DIER,
8    sr: SR,
9    egr: EGR,
10    _reserved4: [u8; 0x02],
11    _reserved_4_ccmr1: [u8; 0x04],
12    _reserved5: [u8; 0x04],
13    ccer: CCER,
14    _reserved6: [u8; 0x02],
15    cnt: CNT,
16    psc: PSC,
17    _reserved8: [u8; 0x02],
18    arr: ARR,
19    _reserved9: [u8; 0x04],
20    ccr: [CCR; 1],
21    _reserved10: [u8; 0x24],
22    tisel: TISEL,
23}
24impl RegisterBlock {
25    ///0x00 - TIM13 control register 1
26    #[inline(always)]
27    pub const fn cr1(&self) -> &CR1 {
28        &self.cr1
29    }
30    ///0x0c - TIM13 DMA/Interrupt enable register
31    #[inline(always)]
32    pub const fn dier(&self) -> &DIER {
33        &self.dier
34    }
35    ///0x10 - TIM13 status register
36    #[inline(always)]
37    pub const fn sr(&self) -> &SR {
38        &self.sr
39    }
40    ///0x14 - TIM13 event generation register
41    #[inline(always)]
42    pub const fn egr(&self) -> &EGR {
43        &self.egr
44    }
45    ///0x18 - TIM13 capture/compare mode register 1 \[alternate\]
46    #[inline(always)]
47    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
48        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
49    }
50    ///0x18 - TIM13 capture/compare mode register 1 \[alternate\]
51    #[inline(always)]
52    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
53        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
54    }
55    ///0x20 - TIM13 capture/compare enable register
56    #[inline(always)]
57    pub const fn ccer(&self) -> &CCER {
58        &self.ccer
59    }
60    ///0x24 - TIM13 counter
61    #[inline(always)]
62    pub const fn cnt(&self) -> &CNT {
63        &self.cnt
64    }
65    ///0x28 - TIM13 prescaler
66    #[inline(always)]
67    pub const fn psc(&self) -> &PSC {
68        &self.psc
69    }
70    ///0x2c - TIM13 auto-reload register
71    #[inline(always)]
72    pub const fn arr(&self) -> &ARR {
73        &self.arr
74    }
75    ///0x34 - capture/compare register
76    ///
77    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
78    #[inline(always)]
79    pub const fn ccr(&self, n: usize) -> &CCR {
80        &self.ccr[n]
81    }
82    ///Iterator for array of:
83    ///0x34 - capture/compare register
84    #[inline(always)]
85    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
86        self.ccr.iter()
87    }
88    ///0x34 - capture/compare register
89    #[inline(always)]
90    pub const fn ccr1(&self) -> &CCR {
91        self.ccr(0)
92    }
93    ///0x5c - TIM13 timer input selection register
94    #[inline(always)]
95    pub const fn tisel(&self) -> &TISEL {
96        &self.tisel
97    }
98}
99/**CR1 (rw) register accessor: TIM13 control register 1
100
101You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
102
103See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:CR1)
104
105For information about available fields see [`mod@cr1`] module*/
106pub type CR1 = crate::Reg<cr1::CR1rs>;
107///TIM13 control register 1
108pub mod cr1;
109/**DIER (rw) register accessor: TIM13 DMA/Interrupt enable register
110
111You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
112
113See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:DIER)
114
115For information about available fields see [`mod@dier`] module*/
116pub type DIER = crate::Reg<dier::DIERrs>;
117///TIM13 DMA/Interrupt enable register
118pub mod dier;
119/**SR (rw) register accessor: TIM13 status register
120
121You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
122
123See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:SR)
124
125For information about available fields see [`mod@sr`] module*/
126pub type SR = crate::Reg<sr::SRrs>;
127///TIM13 status register
128pub mod sr;
129/**EGR (w) register accessor: TIM13 event generation register
130
131You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:EGR)
134
135For information about available fields see [`mod@egr`] module*/
136pub type EGR = crate::Reg<egr::EGRrs>;
137///TIM13 event generation register
138pub mod egr;
139/**CCMR1_Input (rw) register accessor: TIM13 capture/compare mode register 1 \[alternate\]
140
141You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
142
143See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:CCMR1_Input)
144
145For information about available fields see [`mod@ccmr1_input`] module*/
146#[doc(alias = "CCMR1_Input")]
147pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
148///TIM13 capture/compare mode register 1 \[alternate\]
149pub mod ccmr1_input;
150/**CCMR1_Output (rw) register accessor: TIM13 capture/compare mode register 1 \[alternate\]
151
152You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:CCMR1_Output)
155
156For information about available fields see [`mod@ccmr1_output`] module*/
157#[doc(alias = "CCMR1_Output")]
158pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
159///TIM13 capture/compare mode register 1 \[alternate\]
160pub mod ccmr1_output;
161/**CCER (rw) register accessor: TIM13 capture/compare enable register
162
163You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
164
165See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:CCER)
166
167For information about available fields see [`mod@ccer`] module*/
168pub type CCER = crate::Reg<ccer::CCERrs>;
169///TIM13 capture/compare enable register
170pub mod ccer;
171/**CNT (rw) register accessor: TIM13 counter
172
173You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
174
175See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:CNT)
176
177For information about available fields see [`mod@cnt`] module*/
178pub type CNT = crate::Reg<cnt::CNTrs>;
179///TIM13 counter
180pub mod cnt;
181/**PSC (rw) register accessor: TIM13 prescaler
182
183You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
184
185See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:PSC)
186
187For information about available fields see [`mod@psc`] module*/
188pub type PSC = crate::Reg<psc::PSCrs>;
189///TIM13 prescaler
190pub mod psc;
191/**ARR (rw) register accessor: TIM13 auto-reload register
192
193You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
194
195See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:ARR)
196
197For information about available fields see [`mod@arr`] module*/
198pub type ARR = crate::Reg<arr::ARRrs>;
199///TIM13 auto-reload register
200pub mod arr;
201/**CCR (rw) register accessor: capture/compare register
202
203You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
204
205See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:CCR[1])
206
207For information about available fields see [`mod@ccr`] module*/
208pub type CCR = crate::Reg<ccr::CCRrs>;
209///capture/compare register
210pub mod ccr;
211/**TISEL (rw) register accessor: TIM13 timer input selection register
212
213You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
214
215See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#TIM13:TISEL)
216
217For information about available fields see [`mod@tisel`] module*/
218pub type TISEL = crate::Reg<tisel::TISELrs>;
219///TIM13 timer input selection register
220pub mod tisel;
stm32h5/stm32h573/tim13.rs

stm32h5/stm32h573/
tim13.rs
