stm32h5/stm32h562/tim2/
cnt.rs

1///Register `CNT` reader
2pub type R = crate::R<CNTrs>;
3///Register `CNT` writer
4pub type W = crate::W<CNTrs>;
5///Field `CNT` reader - Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part. The fractional part is not available.
6pub type CNT_R = crate::FieldReader<u32>;
7///Field `CNT` writer - Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part. The fractional part is not available.
8pub type CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
9/**Read-only copy of the UIF bit of the TIMx_ISR register
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum UIFCPYR {
15    ///0: No update occurred
16    NoUpdateOccurred = 0,
17    ///1: Update interrupt pending
18    UpdatePending = 1,
19}
20impl From<UIFCPYR> for bool {
21    #[inline(always)]
22    fn from(variant: UIFCPYR) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `UIFCPY` reader - Read-only copy of the UIF bit of the TIMx_ISR register
27pub type UIFCPY_R = crate::BitReader<UIFCPYR>;
28impl UIFCPY_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> UIFCPYR {
32        match self.bits {
33            false => UIFCPYR::NoUpdateOccurred,
34            true => UIFCPYR::UpdatePending,
35        }
36    }
37    ///No update occurred
38    #[inline(always)]
39    pub fn is_no_update_occurred(&self) -> bool {
40        *self == UIFCPYR::NoUpdateOccurred
41    }
42    ///Update interrupt pending
43    #[inline(always)]
44    pub fn is_update_pending(&self) -> bool {
45        *self == UIFCPYR::UpdatePending
46    }
47}
48impl R {
49    ///Bits 0:31 - Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part. The fractional part is not available.
50    #[inline(always)]
51    pub fn cnt(&self) -> CNT_R {
52        CNT_R::new(self.bits)
53    }
54    ///Bit 31 - Read-only copy of the UIF bit of the TIMx_ISR register
55    #[inline(always)]
56    pub fn uifcpy(&self) -> UIFCPY_R {
57        UIFCPY_R::new(((self.bits >> 31) & 1) != 0)
58    }
59}
60impl core::fmt::Debug for R {
61    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
62        f.debug_struct("CNT")
63            .field("cnt", &self.cnt())
64            .field("uifcpy", &self.uifcpy())
65            .finish()
66    }
67}
68impl W {
69    ///Bits 0:31 - Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part. The fractional part is not available.
70    #[inline(always)]
71    pub fn cnt(&mut self) -> CNT_W<CNTrs> {
72        CNT_W::new(self, 0)
73    }
74}
75/**TIM2 counter
76
77You can [`read`](crate::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H562.html#TIM2:CNT)*/
80pub struct CNTrs;
81impl crate::RegisterSpec for CNTrs {
82    type Ux = u32;
83}
84///`read()` method returns [`cnt::R`](R) reader structure
85impl crate::Readable for CNTrs {}
86///`write(|w| ..)` method takes [`cnt::W`](W) writer structure
87impl crate::Writable for CNTrs {
88    type Safety = crate::Safe;
89}
90///`reset()` method sets CNT to value 0
91impl crate::Resettable for CNTrs {}
stm32h5/stm32h562/tim2/cnt.rs

stm32h5/stm32h562/tim2/
cnt.rs
