stm32h5 0.16.0

Device support crates for STM32H5 devices
Documentation 
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///Register `PSC` reader
pub type R = crate::R<PSCrs>;
///Register `PSC` writer
pub type W = crate::W<PSCrs>;
///Field `PSC` reader - Prescaler value The counter clock frequency ftim_cnt_ck is equal to ftim_psc_ck / (PSC\[15:0\] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register.
pub type PSC_R = crate::FieldReader<u16>;
///Field `PSC` writer - Prescaler value The counter clock frequency ftim_cnt_ck is equal to ftim_psc_ck / (PSC\[15:0\] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register.
pub type PSC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16, crate::Safe>;
impl R {
    ///Bits 0:15 - Prescaler value The counter clock frequency ftim_cnt_ck is equal to ftim_psc_ck / (PSC\[15:0\] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register.
    #[inline(always)]
    pub fn psc(&self) -> PSC_R {
        PSC_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PSC").field("psc", &self.psc()).finish()
    }
}
impl W {
    ///Bits 0:15 - Prescaler value The counter clock frequency ftim_cnt_ck is equal to ftim_psc_ck / (PSC\[15:0\] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register.
    #[inline(always)]
    pub fn psc(&mut self) -> PSC_W<PSCrs> {
        PSC_W::new(self, 0)
    }
}
/**TIM6 prescaler

You can [`read`](crate::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H503.html#TIM6:PSC)*/
pub struct PSCrs;
impl crate::RegisterSpec for PSCrs {
    type Ux = u16;
}
///`read()` method returns [`psc::R`](R) reader structure
impl crate::Readable for PSCrs {}
///`write(|w| ..)` method takes [`psc::W`](W) writer structure
impl crate::Writable for PSCrs {
    type Safety = crate::Safe;
}
///`reset()` method sets PSC to value 0
impl crate::Resettable for PSCrs {}